AR0230CS

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Technical content

Features

• Superior low−light performance
• Latest 3.0 μm pixel with ON Semiconductor DR−Pix™ technology with Dual Conversion Gain
• Full HD support at up to 1080P 60 fps for superior video performance
• Linear or high dynamic range capture
• Optional adaptive local tone mapping (ALTM)
• Pixel or Line interleaved T1/T2 output
• Support for external mechanical shutter
• On−chip phase−locked loop (PLL) oscillator
• Integrated position−based color and lens shading correction
• Slave mode for precise frame−rate control
• Stereo/3D camera support
• Statistics engine
• Data interfaces: four−lane serial high−speed pixel interface (HiSPi) differential signaling (SLVS and HiVCM), or parallel
• Auto black level calibration
• High−speed configurable context switching
• Temperature sensor

Applications

• Video surveillance
• 1080p60 (Surveillance) video applications
• High dynamic range imaging IBGA80 10 /C0121 10 CASE 503AN

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ORDERING INFORMATION

Table 2. AVAILABLE PART NUMBERS Specification Brochure, BRD8011/D. please visit our web site at www.onsemi.com. (master) mode or in single frame trigger mode. black level correction, and on−board temperature sensor. temperature range of −30°C to +85°C ambient. single master input clock running between 6 and 48 MHz.

Figure 1. Block Diagram of AR0230CS on−chip to produce a single image at 16−bit per pixel value. value with close to zero loss in image quality.

1. All power supplies must be adequately decoupled
2. ON Semiconductor recommends a resistor value of 1.5kΩ, but a greater value may be used for
3. The parallel interface output pads can be left unconnected if the serial output interface is used.
4. ON Semiconductor recommends that 0.1 μF and 10 μF decoupling capacitors for each power

schematics for circuit recommendations.

1. ON Semiconductor recommends that analog power planes are placed in a manner such that

coupling with the digital power planes is minimized.

1. I/O signals voltage must be configured to match V

Figure 2. Typical Configuration: Serial Four−Lane HiSPi Interface

Figure 3. Typical Configuration: Serial Four−Lane HiSPi Interface

1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5kΩ, but a greater value may be used for
3. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output
4. ON Semiconductor recommends that 0.1 μF and 10 μF decoupling capacitors for each power

schematics for circuit recommendations.

1. ON Semiconductor recommends that analog power planes are placed in a manner such that

coupling with the digital power planes is minimized.

1. I/O signals voltage must be configured to match V
2. The EXTCLK input is limited to 6−48 MHz

Figure 4. 80−Ball IBGA Package

Table 3. PIN DESCRIPTION, 80−BALL IBGA SLVS0_P A2 Output HiSPi serial data, lane 0, differential P. SLVS1_P A3 Output HiSPi serial data, lane 1, differential P. SLVSC_P A4 Output HiSPi serial DDR clock differential P. SLVS2_P A5 Output HiSPi serial data, lane 2, differential P. SLVS3_P A6 Output HiSPi serial data, lane 3, differential P. SLVS0_N B2 Output HiSPi serial data, lane 0, differential N. SLVS1_N B3 Output HiSPi serial data, lane 1, differential N. SLVSC_N B4 Output HiSPi serial DDR clock differential N. SLVS2_N B5 Output HiSPi serial data, lane 2, differential N. SLVS3_N B6 Output HiSPi serial data, lane 3, differential N. SHUTTER B9 Output Control for external mechanical shutter. Can be left floating if not used. VAA C1, G1, D9, F9 Power Analog power. AGND C2, G2, D8, E8, F8 Power Analog ground. (R0x306E[9]) bit to 1 when configuring VDD_SLVS to 1.7 – 1.9V. EXTCLK D3 Input External input clock. PIXCLK D4 Output Pixel clock out. Dout is valid on rising edge of this clock. TRIGGER D6 Input Exposure synchronization input. VAA_PIX E9 Power Pixel power. SDATA E3 I/O Two−Wire Serial data I/O. FLASH E4 Output Flash control output. FRAME_VALID E5 Output Asserted when Dout frame data is valid. SCLK E6 Input Two−Wire Serial clock input. DOUT10 F4 Output Parallel pixel data output. DOUT9 F5 Output Parallel pixel data output. LINE_VALID F6 Output Asserted when Dout line data is valid. DOUT8 G4 Output Parallel pixel data output. DOUT7 G5 Output Parallel pixel data output. DOUT6 G6 Output Parallel pixel data output. DOUT5 H4 Output Parallel pixel data output. DOUT4 H5 Output Parallel pixel data output. DOUT3 H6 Output Parallel pixel data output. TEST H8 Input. Manufacturing test enable pin (connect to Dgnd).

Table 3. PIN DESCRIPTION, 80−BALL IBGA (continued) DOUT2 J1 Output Parallel pixel data output. DOUT1 J3 Output Parallel pixel data output. OE_BAR J8 Input Output enable (active LOW). pixels to improve image uniformity within the active area. Not all dummy pixels or barrier pixels can be read out. Figure 5. Pixel Array Description

www.onsemi.com FEATURES OVERVIEW For a complete description, recommendations, and usage guidelines for product features, refer to the AR0230CS Developer Guide. 3.0 /C0109m Dual Conversion Gain Pixel To improve the low light performance and keep the high dynamic range, a large (3.0um) dual conversion gain pixel is implemented for better image optimization. With a dual conversion gain pixel, the conversion gain of the pixel may be dynamically changed to better adapt the pixel response based on dynamic range of the scene. This gain can be switched manually or automatically by an auto exposure control module. HDR By default, the sensor powers up in HDR Mode. The HDR scheme used is multi−exposure HDR. This allows the sensor to handle up to 96 dB of dynamic range. In HDR mode, the sensor sequentially captures two exposures by maintaining two separate read and reset pointers that are interleaved within the rolling shutter readout. The intermediate pixel values are stored in line buffers while waiting for the two exposure values to be present. As soon as a pixel’s two exposure values are available, they are combined to create a linearized 16−bit value for each pixel’s response. The exposure ratio may be set to 4x, 8x, 16x, or 32x. Depending on whether HiSPi or Parallel mode is selected, the full 16 bit value may be output, it can be compressed to 12 bits using Adaptive Local Tone Mapping (ALTM), or companded to 12 or 14 bits. Options to output T1 only, T2 only, or pixel interleaved data are also available. Individual exposures may be read out in a line interleaved mode as described in the T1/T2 Line Interleaved Mode section. Resolution The active array supports a maximum of 1928x1088 pixels to support 1080p resolution. Utilizing a 3.0um pixel will result in an optical format of 1/2.7−inch (approximately 6.6mm diagonal). Frame Rate At full (1080p) resolution, the AR0230CS is capable of running up to 3060 fps. Image Acquisition Mode The AR0230CS supports two image acquisition modes:

• Electronic rolling shutter (ERS) mode This is the normal mode of operation. When the AR0230CS is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When ERS mode is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between row reset and row readout. For each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. When the integration time is changed (by using the two−wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the AR0230CS switches cleanly from the old integration time to the new while only generating frames with uniform integration. See “Changes to Integration Time” in the AR0230CS Register Reference.
• Global reset mode. This mode can be used to acquire a single image at the current resolution. In this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the AR0230CS provides control signals to interface to that shutter. The benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particularly at low frame rates, because an ERS image effectively integrates each row of the pixel array at a different point in time. Embedded Data and Statistics The AR0230CS has the capability to output image data and statistics embedded within the frame timing. There are two types of information embedded within the frame readout.
• Embedded Data: If enabled, these are displayed on the two rows immediately before the first active pixel row is displayed.
• Embedded Statistics: If enabled, these are displayed on the two rows immediately after the last active pixel row is displayed.

controls for multi−camera (stereo) support. context A the sensor will reference the context A registers. Table 4. LIST OF CONFIGURABLE REGISTERS FOR potentially be visible and might look like a ghosting effect.

www.onsemi.com Tone Mapping Real−world scenes often have a very high dynamic range (HDR) that far exceeds the electrical dynamic range of the imager. Dynamic range is defined as the luminance ratio between the brightest and the darkest objects in a scene. Even though the AR0230CS can capture full dynamic range images, the images are still limited by the low dynamic range of display devices. Today’s typical LCD monitor has a contrast ratio around 1,000:1 while it is not atypical for an HDR image having a contrast ratio of around 250,000:1. Therefore, in order to reproduce HDR images on a low dynamic range display device, the captured high dynamic range must be compressed to the available range of the display device. This is commonly called tone mapping. The AR0230CS has implemented an adaptive local tone mapping (ALTM) feature to reproduce visually appealing images that increase the local contrast and the visibility of the images. Adaptive Color Difference (ADACD) Noise Filtering A good noise reduction filter will remove noise from an image while retaining as much image detail as possible. To retain image detail, the noise reduction filter must adapt to the image signal. To remove noise, the noise reduction filter must adapt to the noise level of the image signal. The key is to remove the appropriate amount of noise. Over−filtering will cause image blurring while under−filtering will leave noise in the image. The AdaCD algorithm relies on a noise model derived from characterization data to aid in separating noise from signal. The AR0230CS AdaCD algorithm performs pixel−by−pixel color noise correction for each of the red, blue, and green color planes. Each pixel is corrected based on surrounding pixel values on the same color plane and a noise model. The noise model is based on characterization data, and takes into account applied analog gain. Fast Mode Switch (Combi Mode) To facilitate faster switching between linear and HDR modes, the AR0230CS includes a Combi Mode feature. When enabled, Combi Mode loads a single (HDR) sequencer. When switching from HDR to linear modes, the sequencer remains the same, but only the T1 image is output. While not optimized for linear mode operation, it allows faster mode switching as a new sequencer load is not needed. Switching between modes may result in the output of one bad frame. Analog/Digital Gain A programmable analog gain of 1.5x to 12x (HDR) and 1.5x to 16x (linear) applied simultaneously to all color channels will be featured along with a digital gain of 1x to 16x that may be configured on a per color channel basis. Skipping/Binning Modes The AR0230CS supports subsampling. Subsampling allows the sensor to read out a smaller set of active pixels by either skipping, binning, or summing pixels within the readout window. Horizontal binning is achieved in the digital readout. The sensor will sample the combined 2x adjacent pixels within the same color plane. Vertical row binning is applied in the pixel readout. Row binning can be configured as 2x rows within the same color plane. Pixel skipping can be configured up to 2x in both the x−direction and y−direction. Skipping pixels in the x−direction will not reduce the row time. Skipping pixels in the y direction will reduce the number of rows from the sensor effectively reducing the frame time. Skipping will introduce image artifacts from aliasing. The AR0230CS supports row wise vertical binning. Row wise vertical summing is not supported. Clocking Options The sensor contains a phase−locked loop (PLL) that is used for timing generation and control. The required VCO clock frequency is attained through the use of a pre−PLL clock divider followed by a multiplier. The PLL multiplier should be an even integer. If an odd integer (M) is programmed, the PLL will default to the lower (M−1) value to maintain an even multiplier value. The multiplier is followed by a set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces. Use of the PLL is required when using the HiSPi interface. Temperature Sensor The AR0230CS sensor has a built−in PTA T−based temperature sensor, accessible through registers, that is capable of measuring die junction temperature. The value read out from the temperature sensor register is an ADC output value that needs to be converted downstream to a final temperature value in degrees Celsius. Since the PTAT device characteristic response is quite linear in the temperature range of operation required, a simple linear function can be used to convert the ADC output value to the final temperature in degrees Celsius. A single reference point will be made available via register read as well as a slope for back−calculating the junction temperature value. An error of +/−5% or better over the full specified operating range of the sensor is to be expected. Silicon / Firmware / Sequencer Revision Information A revision register will be provided to read out (via I/C0050C) silicon and sequencer/OTPM revision information. This will be helpful to distinguish among different lots of material if there are future OTPM or sequencer revisions. Lens Shading Correction The latest lens shading correction algorithm will be included for potential low Z height applications. Companding The 16−bit linearized HDR image may be compressed to 12− or 14− bits using on−chip companding. This is useful if

www.onsemi.com on−chip ALTM will not be used and the ISP cannot handle 16 bit data. Compression When the AR0230CS is configured for linear mode operation, the sensor can optionally compress 12−bit data to 10−bit using A−law compression. The A−law compression is disabled by default. Packaging The AR0230CS will be offered in a 10x10 80−iBGA package (parallel and HiSPi). The package will have anti−reflective coating on both sides of the cover glass. Parallel Interface The parallel pixel data interface uses these output−only signals:

• FRAME_V ALID
• LINE_V ALID
• PIXCLK
• DOUT[11:0] The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. High Speed Serial Pixel (HiSPi) Interface The HiSPi interface supports three protocols, Streaming−S, Streaming−SP, and Packetized SP. The streaming protocols conform to a standard video application where each line of active or intra−frame blanking provided by the sensor is transmitted at the same length. The Packetized SP protocol will transmit only the active data ignoring line−to−line and frame−to−frame blanking data. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. The AR0230CS supports serial data widths of 10, 12, 14, 16, or 20 bits on one, two, or four lanes. The specification includes a DLL to compensate for differences in group delay for each data lane. The DLL is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. Once the DLL has gained phase lock, each lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in PCB design. Delay compensation may be set for clock and/or data lines in the hispi_timing register R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x0000 to reduce jitter, skew, and power dissipation. Sensor Control Interface The two−wire serial interface bus enables read/write access to control and status registers within the AR0230CS. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (S CLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off−chip by a 1.5kΩ resistor. Either the slave or master device can drive S DATA LOW−the interface protocol determines which device is allowed to drive S DATA at any given time. The two−wire serial interface can run at 100 kHz or 400 kHz. T1/T2 Line Interleaved Mode The AR0230CS has the capability to output the T1 and T2 exposures separately, in a line interleaved format. The purpose of this is to enable off chip HDR linear combination and processing. See the AR0230CS Developer Guide for more information.

Table 5. TWO−WIRE SERIAL BUS CHARACTERISTICS Hold time (repeated) START condition.

1. This table is based on I /C0050C standard (v2.1 January 2000). Philips Semiconductor.
2. Two−wire control is I /C0050C−compatible.
3. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
4. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
5. A Fast−mode I /C0050C−bus device can be used in a Standard−mode I2C−bus system, but the requirement tSU;DAT 250 ns must then be met.

Standard−mode I2C−bus specification) before the SCLK line is released.

1. Cb = total capacitance of one bus line in pF.

Figure 10. I/O Timing Diagram Table 6. I/O TIMING CHARACTERISTICS

1. I/O timing characteristics are measured under the following conditions:

Table 7. DC ELECTRICAL CHARACTERISTICS this specification is not implied. Table 8. ABSOLUTE MAXIMUM RATINGS

1. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Table 9. 1080p30 HDR (ALTM) 74 MHz Parallel 2.8V

1. Operating currents are measured in mA at the following conditions:

Table 10. 1080p30 Linear 74MHz Parallel 2.8V

1. Operating currents are measured in mA at the following conditions:

Table 11. 1080p30 HDR (ALTM) 74MHz Parallel 1.8V

1. Operating currents are measured in mA at the following conditions:

Table 12. 1080p30 Linear 74 MHz Parallel 1.8V

1. Operating currents are measured in mA at the following conditions:

Table 13. 1080p30 HDR (ALTM) 74 MHz HiSPi SLVS (Low Power Mode)

1. Operating currents are measured in mA at the following conditions:

Table 14. 1080p30 Linear 74 MHz HiSPi SLVS

1. Operating currents are measured in mA at the following conditions:

Table 15. 1080p30 HDR (ALTM) 74 MHz HiSPi HiVcm (Low Power Mode)

1. Operating currents are measured in mA at the following conditions:

Table 16. 1080p30 Linear 74Mhz HiSPi HiVcm

1. Operating currents are measured in mA at the following conditions:

Table 17. Line Interleaved HiSPi SLVS Table 18. Line Interleaved HiSPi HiVcm

1. Operating currents are measured in mA at the following conditions:

Table 19. CHANNEL SKEW

VAA_PIX) must have the separation specified below.

1. Turn on VDD_PLL power supply.
2. After 100μs, turn on VAA and VAA_PIX power
3. After 100μs, turn on VDD_IO power supply.
4. After 100μs, turn on VDD power supply.
5. After 100μs, turn on VDD_SLVS power supply.
6. After the last power supply is stable, enable
7. Assert RESET_BAR for at least 1ms. The parallel

interface will be tri−stated during this time.

1. Wait 150000 EXTCLKs (for internal initialization
2. Configure PLL, output, and image settings to
3. Wait 1ms for the PLL to lock.
4. Set streaming mode (R0x301a[2] = 1).

Figure 11. Power Up Table 20. POWER−UP SEQUENCE 12.Xtal settling time is component−dependent, usually taking about 10 – 100 ms. RC time must include the all power rail settle time and Xtal settle time. current draw on this supply.

VAA_PIX) must have the separation specified below.

1. Disable streaming if output is active by setting
2. The soft standby state is reached after the current

Figure 12. Power Down Table 21. POWER−DOWN SEQUENCE

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