AR0135CS2M25SUEA0-DPBR1

AR0135CS ONSEMI | Alldatasheet

Document overview

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Technical content

Features

• ON Semiconductor’s Next Generation Global Shutter Technology
• Superior Low-light Performance
• HD Video (720p60)
• Video/Single Frame Mode
• Flexible Row-skip Modes
• On-chip AE and Statistics Engine
• Parallel and Serial Output
• Support for External LED or Flash
• Auto Black Level Calibration
• Context Switching

Applications

• Barcode Scanner
• 3D Scanning
• Positional Tracking
• Iris Scanning
• Augmented Reality
• Virtual Reality
• Biometrics
• Machine Vision
• Gesture Control See detailed ordering and shipping information on page 2 of this data sheet.

ORDERING INFORMATION

www.onsemi.com Table 2. ORDERABLE PART NUMBERS (master) mode or in frame trigger mode. dedicated pins, along with a synchronized pixel clock. external LED or flash exposure illumination. temperature sensor, and row skip and digital binning modes.

a single master input clock running between 6 and 50MHz. a block diagram of the sensor. Figure 1. Block Diagram

74.25 Mp/s, in parallel to frame and line synchronization

features to enhance functionality and to increase versatility.

• Operating Modes The AR0135CS works in master (video), trigger (single frame), or Auto Trigger modes. In master mode, the sensor generates the integration and readout timing. In trigger mode, it accepts an external trigger to start exposure, then generates the exposure and readout timing. The exposure time is programmed through the two-wire serial interface for both modes. Trigger mode is not compatible with the HiSPi interface.
• Window Control Configurable window size and blanking times allow a wide range of resolutions and frame rates. Digital binning and skipping modes are supported, as are vertical and horizontal mirror operations.
• Context Switching Context switching may be used to rapidly switch between two sets of register values. Refer to the AR0135CS Developer Guide for a complete set of context switchable registers.
• Gain The AR0135CS Global Shutter sensor can be configured for analog gain of up to 8x, and digital gain of up to 8x.
• Automatic Exposure Control The integrated automatic exposure control may be used to ensure optimal settings of exposure and gain are computed and updated every other frame. Refer to the AR0135CS Developer Guide for more details.
• HiSPi The AR0135CS Global Shutter image sensor supports two or three lanes of Packetized-SP protocols of ON Semiconductor’s High-Speed Serial Pixel Interface.
• PLL An on chip PLL provides reference clock flexibility and supports spread spectrum sources for improved EMI performance.

• Reset The AR0135CS may be reset by a register write, or by a dedicated input pin.
• Output Enable The AR0135CS output pins may be tri-stated using a dedicated output enable pin.
• Temperature Sensor The temperature sensor is only guaranteed to be functional when the AR0135CS is initially powered-up or is reset at temperatures at or above 0°C.
• Black Level Correction
• Row Noise Correction
• Column Correction
• Test Patterns Several test patterns may be enabled for debug purposes. These include a solid color, color bar, fade to grey, and a walking 1s test pattern. PIXEL DATA FORMAT Pixel Array Structure The AR0135CS pixel array is configured as 1412 columns by 1028 rows, (see Figure 2). The dark pixels are optically black and are used internally to monitor black level. Of the right 108 columns, 64 are dark pixels used for row noise correction. Of the top 24 rows of pixels, 12 of the dark rows are used for black level correction. There are 1288 columns by 972 rows of optically active pixels that can be readable. While the sensor’s format is 1280 × 960, the additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Not all dummy pixels or barrier pixels can be read out. The optical center of the readable active pixels can be found between X_ADDR 643 and 644, and between Y_ADDR 485 and 486.

Figure 2. Pixel Array Description

4 Extra Active +

2 Light Dummy +

4 Barrier +

24 Dark +

10 Barrier

2 Extra Active +

100 Dark +

4 Barrier

6 Extra Active +

Figure 5. Serial 4-lane HiSPi Interface

1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on S CLK at all times.
4. The parallel interface output pads can be left unconnected if the serial output interface is used.
5. ON Semiconductor recommends that 0.1 /C0109F and 10 /C0109F decoupling capacitors for each power supply are mounted as close as possible

headboard schematics for circuit recommendations.

1. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s
2. Although 4 serial lanes are shown, the AR0135CS supports only 2- or 3-lane HiSPi.

Figure 6. Parallel Pixel Data Interface

1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on S CLK at all times.
4. The serial interface output pads can be left unconnected if the parallel output interface is used.
5. ON Semiconductor recommends that 0.1 /C0109F and 10 /C0109F decoupling capacitors for each power supply are mounted as close as possible

headboard schematics for circuit recommendations.

1. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s

Figure 7. 9 /C0121 9 mm 60-ball IBGA Package Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE

Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE (continued)

www.onsemi.com TWO-WIRE SERIAL REGISTER INTERFACE The two-wire serial interface bus enables read/write access to control and status registers within the AR0135CS. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (S DATA). SDATA is pulled up to VDD_IO off-chip by a 1.5 k /C0087 resistor. Either the slave or master device can drive S DATA LOW − the interface protocol determines which device is allowed to drive S DATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the AR0135CS uses SCLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both S CLK and S DATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on S DATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on S DATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each S CLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The default slave addresses used by the AR0135CS are 0x20 (write address) and 0x21 (read address) in accordance with the specification. Alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the S ADDR input. An alternate slave address can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the S CLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases S DATA. The receiver indicates an acknowledge bit by driving S DATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive S DATA LOW during the S CLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indicates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave’s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit.

PIXCLK frequency = 74.25 MHz; HiSPi off. Figure 14. Two-Wire Serial Bus Timing Parameters NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 4. TWO-WIRE SERIAL BUS CHARACTERISTICS

Table 4. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued)

1. This table is based on I 2C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I 2C-compatible.
3. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
4. The maximum t HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
5. A Fast-mode I 2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This

I2C-bus specification) before the SCLK line is released.

1. Cb = total capacitance of one bus line in pF.

for I/O timing (AC) characteristics. Figure 15. I/O Timing Diagram Table 5. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (1.8 V VDD_IO) (Note 1)

Table 5. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (1.8 V VDD_IO) (Note 1) (continued)

1. Jitter from PIXCLK is already taken into account in the data for all of the output parameters.

Table 6. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (2.8 V VDD_IO) (Note 1)

1. Jitter from PIXCLK is already taken into account in the data for all of the output parameters.

Table 7. I/O RISE SLEW RATE (2.8 V VDD_IO) (Note 1)

Table 8. I/O FALL SLEW RATE (2.8 V VDD_IO) (Note 1) Table 9. I/O RISE SLEW RATE (1.8 V VDD_IO) (Note 1) Table 10. I/O FALL SLEW RATE (1.8 V VDD_IO) (Note 1)

Table 12, Table 13, Table 14, and Table 15. Table 11. DC ELECTRICAL CHARACTERISTICS specification is not implied. Table 12. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.

1. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Table 13. OPERATING CURRENT CONSUMPTION FOR PARALLEL OUTPUT

Table 14. OPERATING CURRENT CONSUMPTION FOR HiSPi OUTPUT Table 15. STANDBY CURRENT CONSUMPTION electrical specifications are listed at 700 MHz. Table 16. INPUT VOLTAGE AND CURRENT (HiSPi POWER SUPPLY 0.4 V)

Figure 16. Differential Output Voltage for Clock and Data Pairs

0 V (Diff)

Table 17. RISE AND FALL TIMES

1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.
2. Taken from 0 V crossing point.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates

so the rise and fall times do not exceed the maximum 0.3 UI.

1. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
2. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
3. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two

must have the separation specified below.

1. Turn on VDD_PLL power supply.
2. After 0–10 /C0109s, turn on VAA and VAA_PIX power
3. After 0–10 /C0109s, turn on VDD_IO power supply.
4. After the last power supply is stable, enable
5. If RESET_BAR is in a LOW state, hold

RESET_BAR LOW for at least 1 ms. RESET_BAR for at least 1 ms.

1. Wait 160000 EXTCLKs (for internal initialization
2. Configure PLL, output, and image settings to
3. Wait 1 ms for the PLL to lock.
4. Set streaming mode (R0x301A[2] = 1).

Figure 19. Power Up Table 18. POWER-UP SEQUENCE

1. Xtal settling time is component-dependent, usually taking about 10–100 ms.
2. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the

RC time must include the all power rail settle time and Xtal settle time.

1. It is critical that V DD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the

high current draw on this supply.

VAA_PIX) must have the separation specified below.

1. Disable streaming if output is active by setting
2. The soft standby state is reached after the current

Figure 20. Power Down Table 19. POWER-DOWN SEQUENCE

1. t 4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.

timing if the EXTCLK is to be disabled during standby. Figure 21. Enter Standby Timing

750 EXTCLKs

50 EXTCLKs

Figure 22. Exit Standby Timing

10 EXTCLKs

28 Rows + CIT

Figure 25. Chief Ray Angle − 25/C0053

www.onsemi.com PACKAGE DIMENSIONS IBGA63 9x9 CASE 503AZ ISSUE O Notes: AR Coating: 530−570 nm R < 1%; 420−700 nm R < 2%. ball pad.

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