AR0134CSSM00SPD20

AR0134CS ONSEMI | Alldatasheet

Document overview

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Technical content

Features

• ON Semiconductor’s 3rd Generation Global Shutter Technology
• Superior Low-light Performance
• HD Video (720p60)
• Video/Single Frame Mode
• Flexible Row-skip Modes
• On-chip AE and Statistics Engine
• Parallel and Serial Output
• Support for External LED or Flash
• Auto Black Level Calibration
• Context Switching

Applications

• Scene Processing
• Scanning and Machine Vision
• 720p60 Video Applications See detailed ordering and shipping information on page 2 of this data sheet.

ORDERING INFORMATION

www.onsemi.com Table 2. ORDERABLE PART NUMBERS please visit our web site at www.onsemi.com. (master) mode or in frame trigger mode. dedicated pins, along with a synchronized pixel clock. external LED or flash exposure illumination. temperature sensor, and row skip and digital binning modes. single master input clock running between 6 and 50 MHz. a block diagram of the sensor. Figure 1. Block Diagram

www.onsemi.com User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 1.2 Mp Active-Pixel Sensor array. The AR0134CS features global shutter technology for accurate capture of moving images. The exposure of the entire array is controlled by programming the integration time by register setting. All rows simultaneously integrate light prior to readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog-to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The pixel data are output at a rate of up to

74.25 Mp/s, in parallel to frame and line synchronization

signals. FEATURES OVERVIEW The AR0134CS Global Sensor shutter has a wide array of features to enhance functionality and to increase versatility. A summary of features follows. Please refer to the AR0134CS Developer Guide for detailed feature descriptions, register settings, and tuning guidelines and recommendations.

• Operating Modes The AR0134CS works in master (video), trigger (single frame), or Auto Trigger modes. In master mode, the sensor generates the integration and readout timing. In trigger mode, it accepts an external trigger to start exposure, then generates the exposure and readout timing. The exposure time is programmed through the two-wire serial interface for both modes. Trigger mode is not compatible with the HiSPi interface.
• Window Control Configurable window size and blanking times allow a wide range of resolutions and frame rates. Digital binning and skipping modes are supported, as are vertical and horizontal mirror operations.
• Context Switching Context switching may be used to rapidly switch between two sets of register values. Refer to the AR0134CS Developer Guide for a complete set of context switchable registers.
• Gain The AR0134CS Global Shutter sensor can be configured for analog gain of up to 8x, and digital gain of up to 8x.
• Automatic Exposure Control The integrated automatic exposure control may be used to ensure optimal settings of exposure and gain are computed and updated every other frame. Refer to the AR0134CS Developer Guide for more details.
• HiSPi The AR0134CS Global Shutter image sensor supports two or three lanes of Streaming-SP or Packetized-SP protocols of ON Semiconductor’s High-Speed Serial Pixel Interface.
• PLL An on chip PLL provides reference clock flexibility and supports spread spectrum sources for improved EMI performance.
• Reset The AR0134CS may be reset by a register write, or by a dedicated input pin.
• Output Enable The AR0134CS output pins may be tri-stated using a dedicated output enable pin.
• Temperature Sensor The temperature sensor is only guaranteed to be functional when the AR0134CS is initially powered-up or is reset at temperatures at or above 0°C.
• Black Level Correction
• Row Noise Correction
• Column Correction
• Test Patterns Several test patterns may be enabled for debug purposes. These include a solid color, color bar, fade to grey, and a walking 1s test pattern.

dummy pixels or barrier pixels can be read out. Figure 2. Pixel Array Description

2 Light Dummy +

4 Barrier +

24 Dark +

6 Dark Dummy

100 Dark +

4 Barrier

Figure 3. Pixel Color Pattern Detail (Top Right Corner)

Figure 4. Serial 4-lane HiSPi Interface

1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on S CLK at all times.
4. The parallel interface output pads can be left unconnected if the serial output interface is used.
5. ON Semiconductor recommends that 0.1 /C0109F and 10 /C0109F decoupling capacitors for each power supply are mounted as close as possible

board schematics for circuit recommendations.

1. ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is mini-
2. Although 4 serial lanes are shown, the AR0134CS supports only 2- or 3-lane HiSPi.

Figure 5. Parallel Pixel Data Interface

1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on S CLK at all times.
4. The serial interface output pads can be left unconnected if the parallel output interface is used.
5. ON Semiconductor recommends that 0.1 /C0109F and 10 /C0109F decoupling capacitors for each power supply are mounted as close as possible

board schematics for circuit recommendations.

1. ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is mini-

Figure 6. 9 /C0121 9 mm 63-ball iBGA Package Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE

Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE (continued)

Figure 7. 10 /C0121 10 mm 48-pin iLCC Package, Parallel Output Table 4. PIN DESCRIPTIONS − 48-PIN ILCC PACKAGE, PARALLEL

1 DOUT4 Output Parallel pixel data output

2 DOUT5 Output Parallel pixel data output

3 DOUT6 Output Parallel pixel data output

4 VDD_PLL Power PLL power

5 EXTCLK Input External input clock

6 DGND Power Digital ground

7 DOUT7 Output Parallel pixel data output

8 DOUT8 Output Parallel pixel data output

9 DOUT9 Output Parallel pixel data output

Table 4. PIN DESCRIPTIONS − 48-PIN ILCC PACKAGE, PARALLEL (continued)

10 DOUT10 Output Parallel pixel data output

11 DOUT11 Output Parallel pixel data output (MSB)

12 VDD_IO Power I/O supply power

14 VDD Power Digital power

15 SCLK Input Two-Wire Serial clock input

16 SDATA I/O Two-Wire Serial data I/O

18 VDD_IO Power I/O supply power

19 VDD Power Digital power

20 NC No connection

21 NC No connection

22 STANDBY Input Standby-mode enable pin (active HIGH)

23 OE_BAR Input Output enable (active LOW)

24 SADDR Input Two-Wire Serial address select

25 TEST Input Manufacturing test enable pin (connect to DGND)

26 FLASH Output Flash output control

27 TRIGGER Input Exposure synchronization input

28 FRAME_VALID Output Asserted when DOUT frame data is valid

29 LINE_VALID Output Asserted when DOUT line data is valid

30 DGND Power Digital ground

31 Reserved N/A Reserved (do not connect)

32 Reserved N/A Reserved (do not connect)

33 Reserved N/A Reserved (do not connect)

34 VAA Power Analog power

35 AGND Power Analog ground

36 VAA Power Analog power

37 VAA_PIX Power Pixel power

38 VAA_PIX Power Pixel power

39 AGND Power Analog ground

40 VAA Power Analog power

41 NC No connection

42 NC No connection

43 NC No connection

44 DGND Power Digital ground

45 DOUT0 Output Parallel pixel data output (LSB)

46 DOUT1 Output Parallel pixel data output

47 DOUT2 Output Parallel pixel data output

48 DOUT3 Output Parallel pixel data output

www.onsemi.com TWO-WIRE SERIAL REGISTER INTERFACE The two-wire serial interface bus enables read/write access to control and status registers within the AR0134CS. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (S DATA). S DATA is pulled up to VDD_IO off-chip by a 1.5 k /C0087 resistor. Either the slave or master device can drive SDATA LOW − the interface protocol determines which device is allowed to drive S DATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the AR0134CS uses SCLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both S CLK and S DATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on S DATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The default slave addresses used by the AR0134CS are 0x20 (write address) and 0x21 (read address) in accordance with the specification. Alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the S ADDR input. An alternate slave address can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the S CLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases S DATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive S DATA LOW during the S CLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indicates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave’s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit.

Figure 14. Two-Wire Serial Bus Timing Parameters NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 5. TWO-WIRE SERIAL BUS CHARACTERISTICS

Table 5. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued)

1. This table is based on I 2C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I 2C-compatible.
3. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
4. The maximum t HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
5. A Fast-mode I 2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This

I2C-bus specification) before the SCLK line is released.

1. Cb = total capacitance of one bus line in pF.

for I/O timing (AC) characteristics. Figure 15. I/O Timing Diagram Table 6. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (1.8 V VDD_IO) (Note 8)

Table 6. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (1.8 V VDD_IO) (Note 8) (continued)

1. Jitter from PIXCLK is already taken into account in the data for all of the output parameters.

Table 7. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (2.8 V VDD_IO) (Note 10)

1. Jitter from PIXCLK is already taken into account in the data for all of the output parameters.

Table 8. I/O RISE SLEW RATE (2.8 V VDD_IO) (Note 12)

Table 9. I/O FALL SLEW RATE (2.8 V VDD_IO) (Note 13) Table 10. I/O RISE SLEW RATE (1.8 V VDD_IO) (Note 14) Table 11. I/O FALL SLEW RATE (1.8 V VDD_IO) (Note 15)

Table 13, Table 14, and Table 15. Table 12. DC ELECTRICAL CHARACTERISTICS specification is not implied. Table 13. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected. 16.Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 14. OPERATING CURRENT CONSUMPTION FOR PARALLEL OUTPUT

Table 15. STANDBY CURRENT CONSUMPTION electrical specifications are listed at 700 MHz. Table 16. INPUT VOLTAGE AND CURRENT (HiSPi POWER SUPPLY 0.4 V)

Figure 16. Differential Output Voltage for Clock and Data Pairs

0 V (Diff)

Table 17. RISE AND FALL TIMES 17.One UI is defined as the normalized mean time between one edge and the following edge of the clock. 18.Taken from 0 V crossing point. so the rise and fall times do not exceed the maximum 0.3 UI. 20.The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges. 21.The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges.

must have the separation specified below.

1. Turn on VDD_PLL power supply.
2. After 0−10 /C0109s, turn on VAA and VAA_PIX power
3. After 0−10 /C0109s, turn on VDD_IO power supply.
4. After the last power supply is stable, enable
5. If RESET_BAR is in a LOW state, hold

RESET_BAR LOW for at least 1 ms. RESET_BAR for at least 1 ms.

1. Wait 160000 EXTCLKs (for internal initialization
2. Configure PLL, output, and image settings to
3. Wait 1 ms for the PLL to lock.
4. Set streaming mode (R0x301a[2] = 1).

Figure 19. Power Up Table 18. POWER-UP SEQUENCE 23.Xtal settling time is component-dependent, usually taking about 10–100 ms. RC time must include the all power rail settle time and Xtal settle time. high current draw on this supply.

VAA_PIX) must have the separation specified below.

1. Disable streaming if output is active by setting
2. The soft standby state is reached after the current

Figure 20. Power Down Table 19. POWER-DOWN SEQUENCE 26.t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.

timing if the EXTCLK is to be disabled during standby. Figure 21. Enter Standby Timing

750 EXTCLKs

50 EXTCLKs

Figure 22. Exit Standby Timing

10 EXTCLKs

28 Rows + CIT

Figure 25. Chief Ray Angle − 25/C0053 Mono

www.onsemi.com PACKAGE DIMENSIONS IBGA63 9x9 CASE 503AG ISSUE O Notes: 1. Dimensions in mm. Dimensions in () are for reference only. 2. Encapsulant: Epoxy. 3. Substrate material: Plastic laminate 0.25 thickness. 4. Lid material: Borosilicate glass 0.4 ±0.04 thickness. 5. Refractive index at 20C = 1.5255 @ 546 nm and 1.5231 @ 588 nm. 6. Double side AR Coating: 530−570 nm R< 1%; 420−700 nm R < 2%. 7. Image sensor die: 0.2 mm thickness. 8. Solder ball material: SAC305 (95% Sn, 3% Ag, 0.5% Cu). 9. Dimensions apply to solder balls post reflow. Pre-flow ball is 0.5 on a ∅0.4 SMD ball pad. 10.Maximum rotation of optical area relative to pack- age edges: 1°. 11. Maximum tilt of optical area relative to substrate plane D: 25 /C0109m. 12.Maximum tilt of cover glass relative to optical area plane E: 50 /C0109m.

www.onsemi.com PACKAGE DIMENSIONS ILCC48 10x10 CASE 847AE ISSUE O Notes: 1. Dimensions in mm. Dimensions in () are for reference only. 2. Encapsulant: Epoxy. 3. Substrate material: Plastic laminate 0.25 thickness. 4. Lid material: Borosilicate glass 0.4 ±0.04 thickness. 5. Refractive index at 20C = 1.5255 @ 546 nm and 1.5231 @ 588 nm. 6. Double side AR Coating: 530−570 nm R< 1%; 420−700 nm R < 2%. 7. Lead finish: Gold plating, 0.5 /C0109m min. thickness. 8. Image sensor die: 0.2 mm thickness. 9. Maximum rotation of optical area relative to package edges: 0.75°. 10.Maximum tilt of optical area relative to substrate plane D: 25 /C0109m. 11. Maximum tilt of cover glass relative to optical area plane E: 50 /C0109m.

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