APT7M120B_09 MICROSEMI | Alldatasheet
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Thermal and Mechanical Characteristics G D S Single die MOSFET Unit A V mJ A Unit W °C/W oz g in·lbf N·m Ratings ±30 575 Min Typ Max 335 0.37 0.11 -55 150 300 0.22 6.2 1.1 Parameter Continuous Drain Current @ T C = 25°C Continuous Drain Current @ TC = 100°C Pulsed Drain Current 1 Gate-Source Voltage Single Pulse Avalanche Energy 2 Avalanche Current, Repetitive or Non-Repetitive Characteristic Total Power Dissipation @ TC = 25°C Junction to Case Thermal Resistance Case to Sink Thermal Resistance, Flat, Greased Surface Operating and Storage Junction Temperature Range Soldering Temperature for 10 Seconds (1.6mm from case) Package Weight Mounting Torque ( TO-247 Package), 6-32 or M3 screw Symbol I D IDM VGS EAS IAR Symbol PD RθJC RθCS TJ,TSTG TL WT Torque TYPICAL APPLICATIONS PFC and other boost converter Buck converter Two switch forward (asymmetrical bridge) Single switch forward Flyback Inverters
FEATURES
Fast switching with low EMI/RFI Low R DS(on) Ultra low C rss for improved noise immunity Low gate charge Avalanche energy rated RoHS compliant TO-247 D3PAK APT7M120B APT7M120S 1200V, 8A, 2.1Ω Max APT7M120B APT7M120S Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET. A proprietary planar stripe design yields excellent reliability and manufacturability. Low switching loss is achieved with low input capacitance and ultra low C rss "Miller" capaci- tance. The intrinsic gate resistance and capacitance of the poly-silicon gate structure help control slew rates during switching, resulting in low EMI and reliable paralleling, even when switching at very high frequency. Reliability in fl yback, boost, forward, and other circuits is enhanced by the high avalanche energy capability. Microsemi Website - http://www.microsemi.com 050-8104 Rev B 5-2009
Static Characteristics T J = 25°C unless otherwise specifi ed Source-Drain Diode Characteristics Dynamic Characteristics T J = 25°C unless otherwise specifi ed 1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature. 2 Starting at TJ = 25°C, L = 127.78mH, RG = 4.7Ω, IAS = 3A. 3 Pulse test: Pulse Width < 380µs, duty cycle < 2%. 4 Co(cr) is defi ned as a fi xed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS. 5 C o(er) is defi ned as a fi xed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of V DS less than V(BR)DSS, use this equation: Co(er) = -1.17E-7/VDS^2 + 1.42E-8/VDS + 2.01E-11. 6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452) Microsemi reserves the right to change, without notice, the specifi cations and information contained herein. G D S Unit V V/°C Ω V mV/°C µA nA Unit A V ns µC V/ns Unit S pF nC ns Min Typ Max 1200 1.41 1.50 2.1 3 4 5 -10 100 500 ±100 Min Typ Max 1.0 1165 Min Typ Max 2565 190 Test Conditions VGS = 0V, ID = 250µA Reference to 25°C, ID = 250µA VGS = 10V, ID = 3A VGS = VDS, ID = 1mA V DS = 1200V T J = 25°C V GS = 0V T J = 125°C VGS = ±30V Test Conditions VDS = 50V, ID = 3A VGS = 0V, VDS = 25V f = 1MHz VGS = 0V, VDS = 0V to 800V VGS = 0 to 10V, ID = 3A, VDS = 600V Resistive Switching VDD = 800V, ID = 3A RG = 4.7Ω 6 , VGG = 15V Test Conditions MOSFET symbol showing the integral reverse p-n junction diode (body diode) I SD = 3A, TJ = 25°C, VGS = 0V ISD = 3A, VDD = 100V 3 diSD/dt = 100A/µs, TJ = 25°C ISD ≤ 3A, di/dt ≤1000A/µs, VDD = 800V, TJ = 125°C Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coeffi cient Drain-Source On Resistance 3 Gate-Source Threshold Voltage Threshold Voltage Temperature Coeffi cient Zero Gate Voltage Drain Current Gate-Source Leakage Current Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Peak Recovery dv/dt Parameter Forward Transconductance Input Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance, Charge Related Effective Output Capacitance, Energy Related Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Current Rise Time Turn-Off Delay Time Current Fall Time Symbol VBR(DSS) ΔVBR(DSS)/ΔTJ RDS(on) VGS(th) ΔVGS(th)/ΔTJ IDSS IGSS Symbol IS ISM VSD trr Qrr dv/dt Symbol gfs Ciss Crss Coss Co(cr) Co(er) Qg Qgs Qgd td(on) tr td(off) tf 050-8104 Rev B 5-2009 APT7M120B_S