APM32F003X4X6 GEEHY | Alldatasheet
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www.geehy.com Page 0 Version:V2.2 APM32F003x4x6 Arm® Cortex®-M0+ based 32-bit MCU Datasheet
www.geehy.com Page 1 1. Product Characteristics ◼ Systems Architecture - 32-bit Arm® Cortex®-M0+ core - The maximum working frequency is 48MHz - AHB bus, APB bus ◼ Power, clock and reset - Power supply voltage is 2.4~5.5V - Clock: built-in factory calibrated 48MHz high-speed clock, built- in factory calibrated 128KHz low-speed clock, and external 1MHz-24MHz crystal oscillator - Reset: power-on reset and power-down reset ◼ Memories - Up to 32Kbytes Flash - Up to 4Kbytes SRAM ◼ Low power consumption mode - Support three low power consumption modes: wait, active-halt and halt ◼ I/O - Up to 16 I/O, all of which can be mapped to external interrupt controllers ◼ Timer and PWM - Two 16-bit advanced timers with 4-channel capture comparison function, PWM complementary output and dead time control - 1 16-bit general timer, which supports PWM mode and 3- channel capture comparison function - 1 8-bit basic timer - 2 watchdog timers - 1 system tick timer - 1 automatic wake-up timer ◼ ADC - 1 12bit resolution, 8 external channels, supporting differential input ◼ communication interface - 3 USART - 1 I2C - 1 SPI ◼ 1 BUZZER ◼ Serial wire debugging SWD interface ◼ Chip package - TSSOP20/QFN20/SOP20 ◼ 96-bit UID ◼ Application field - Smart home - Medical equipment - Motor driver - Industrial sensor - Auto parts
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www.geehy.com Page 5 2. Product Information See the following table for specific APM32F003x4x6 product functions and peripheral configuration. Table 1 The APM32F003x4x6 product functions and peripheral configuration Products APM32F003x4x6 F4P6 F6P6 F4U6 F6U6 F4M6 F6M6 Encapsulation TSSOP20 TSSOP20 QFN20 QFN20 SOP20 SOP20 Flash(Kbytes) 16 32 16 32 16 32 SRAM(Kbytes) 2 4 2 4 2 4 Timer Advanced （16bit） General (16bit) Basic (8bit) SysTick (24bit) WUPT 1 WDT 2 Communication Interface USART 3 I2C 1 SPI 1 12bit ADC unit 1 channels 8 GPIOs 16 BUZZER 1 Core Arm® Cortex®-M0+ Frequency 48MHz Service voltage 2.4~5.5V
www.geehy.com Page 6 3. Pin Information Pin Distribution Figure 1 Pin configuration diagram of QFN20 Figure 2 Pin configuration diagram of TSSOP20 and SOP20 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD PA3 PB5 PB4 PC3 6 7 8 9 10 PD1 PC7 PC6 PC5 PC4
1617181920 PD6
/SOP20
www.geehy.com Page 7 Pin Function Description Table 2 Pin definition of APM32F003x4x6(20PIN) Pin number Pin name Type (1) Input Output Function after reset Redefinin g functions TSSOP20 SOP20 QFN20 floating wpu Ext.interrupt High sink Speed OD PP 1 1 18 PD4 BUZZER TMR2_CH1 USART1_CK TMR1A_CH2 I/O X X X HS O3 X X PD4 - 2 2 19 PD5 AIN5 USART1_TX TMR1A_CH3 VAIN2 [TMR1A_CH1N] I/O X X X HS O3 X X PD5 TMR1A_C H1N [AFR5] 3 3 20 PD6 AIN6 USART1_RX TMR1A_CH4 VAIP2 [TMR1A_CH2N] I/O X X X HS O3 X X PD6 TMR1A_C H2N [AFR5] 4 4 1 NRST I/O - X - - - - - Reset - 5 5 2 PA1 OSCIN(2) I/O X X X - O1 X X PA1 - 6 6 3 PA2 OSCOUT I/O X X X - O1 X X PA2 - 1.5V regulat /capaci tor
www.geehy.com Page 8 Pin number Pin name Type (1) Input Output Function after reset Redefinin g functions TSSOP20 SOP20 QFN20 floating wpu Ext.interrupt High sink Speed OD PP 10 10 7 PA3 TMR2_CH3 TMR1_ETR USART3_CK [SPI_NSS] I/O X X X HS O3 X X PA3 SPI_NSS [AFR1] 11 11 8 PB5 I2C_SDA USART3_RX [TMR1_BKIN] I/O X - X O1 T - PB5 TMR1_BKI N [AFR4] 12 12 9 PB4 I2C_SCL USART3_TX [ADC_ETR] I/O X - X O1 T - PB4 ADC_ETR [AFR4] 13 13 10 PC3 TMR1_CH3 AIN7 VAIN3 [TLI] [TMR1_CH1N] I/O X X X HS O3 X X PC3 TLI [AFR3] TMR1_CH [AFR7] 14 14 11 PC4 TMR1_CH4 CLK_CCO AIN2 VAIP1 [TMR2_CH2N] I/O X X X HS O3 X X PC4 TMR1_CH [AFR7] 15 15 12 PC5 SPI_SCK AIN0 VAIP0 [TMR2_CH1] I/O X X X HS O3 X X PC5 [TMR2_CH [AFR0] 16 16 13 PC6 SPI_MOSI AIN1 VAIN0 [TMR1_CH1] I/O X X X HS O3 X X PC6 TMR1_CH [AFR0]
www.geehy.com Page 9 Pin number Pin name Type (1) Input Output Function after reset Redefinin g functions TSSOP20 SOP20 QFN20 floating wpu Ext.interrupt High sink Speed OD PP 17 17 14 PC7 SPI_MISO [TMR1_CH2] I/O X X X HS O3 X X PC7 TMR1_CH [AFR0] 18 18 15 PD1 SWD USART2_CK TMR1A_CH1 I/O X X X HS O4 X X PD1 - 19 19 16 PD2 AIN3 SWCLK USART2_RX TMR1A_BKIN VAIN1 [TMR2_CH3] I/O X X X HS O3 X X PD2 TMR2_CH [AFR1] 20 20 17 PD3 AIN4 TMR2_CH2 ADC_ETR USART2_TX TMR1A_ETR VAIP3 I/O X X X HS O3 X X PD3 - Note: (1) I= input, O= output, S= power supply (2) X: initial state after reset (3) T: true open drain I/O (4) Floating= high resistance, HS= maximum sink current, OD= open drain, PP= push pull, wpu= weak pull up (5) Speed: O1 = low speed, maximum 2M; O2= high speed, up to 10M；; O3= compatible with high and low speed, low speed at startup; O4= Compatible with high and low speed, high speed at startup (6) PA1 does not support halt mode or wake up in active halt mode (7) After the low power consumption mode is turned on, PA1 can only maintain the input state and cannot drive the output state
www.geehy.com Page 10 4. Function Description System Architecture 4.1.1. System block diagram Figure 3 System block diagram of APM32F003x4x6 series Bus matrix Flash SRAM System bus APB1 bus WWDT IWDT USART1/2/3 I2C Arm® Cortex®-M0+ (Fmax:48MHz) SWD NVIC SCB STK AHB bus RCM FMC TMR1/1A/2/4 PMU EINT ADC SPI AHB/APB1 bridge BUZZER
www.geehy.com Page 11 4.1.2. Address mapping Figure 4 Address map of APM32F003x4x6 series Peripheral 0xFFFF FFFF 0xE010 0000 0xE000 0000 Cortex-M0+ 0xC000 0000 0xA000 0000 0x8000 0000 0x6000 0000 0x4000 0000 0x2000 0000 0x0000 0000 SRAM Code 0x0000 0000 - 0x0000 7FFF ROM 0x0002 0400 - 0x0002 07FF reserved Option byte Flash Interface 0x4001 1400 - 0x4001 14FF 0x4001 1000 - 0x4001 13FF RCM 0x4001 0400 - 0x4001 0FFF 0x4001 0000 - 0x4001 03FF USART3 ADC 0x4000 4400 - 0x4000 47FF 0x4000 4800–0x4000 4BFF TMR4 TMR2 TMR1 0x4000 4000 - 0x4000 43FF 0x4000 3C00 - 0x4000 3FFF 0x4000 3800 - 0x4000 3BFF USART1 I2C 0x4000 3400 - 0x4000 37FF 0x4000 3000 - 0x4000 33FF SPI BUZZER WUPT 0x4000 2C00 - 0x4000 2FFF 0x4000 2800 - 0x4000 2BFF 0x4000 2400 - 0x4000 27FF IWDT WWDT EINT 0x4000 2000 - 0x4000 23FF 0x4000 1C00 - 0x4000 1FFF 0x4000 1800 - 0x4000 1BFF USART2 GPIOD GPIOC GPIOB GPIOA 0x4000 1400 - 0x4000 17FF TMR1A 0x4000 1000 - 0x4000 13FF 0x4000 0C00 - 0x4000 0FFF 0x4000 0800 - 0x4000 0BFF 0x4000 0400 - 0x4000 07FF 0x4000 0000 - 0x4000 03FF CMU 0x4001 0000 - 0x4001 03FF 0x0000 8000 - 0x0002 03FF
www.geehy.com Page 12 Core The Arm® Cortex®-M0+ core is built into the product, and the working frequency is 24MHz, which is compatible with mainstream Arm tools and software. The system block diagram of APM32F003x4x6 series chips is shown in Figure Interrupt controller 4.3.1. Nested Vector Interrupt Controller (NVIC) The APM32F003x4x6 series chips are embedded with a nested vector interrupt controller, which can handle up to 23 masked interrupt channels (excluding Cortex®-M0+interrupt lines) and 4 priorities. Nested Vector Interrupt Controller (NVIC) has tightly coupled NVIC interface, which can directly transmit interrupt vector entry address to kernel, and can achieve low-latency interrupt response processing. In addition, it can give priority to high-priority interrupts, automatically save processor state, and automatically recover when interrupts return, without extra instruction overhead. The module provides flexible interrupt management with minimal interrupt delay. 4.3.2. External interrupt controller (EINT) The external interrupt controller includes four edge detectors for generating interrupt requests. Each interrupt line can be independently configured with trigger events and can be individually shielded. All I/O pins have external interrupt capability, and each port has an independent interrupt vector. Memory See the following table for details of memory: Table 3 Memory description Memory Max bytes Function Built-in Flash 32Kbytes Used to store programs and data. Built-in SRAM 4Kbytes It can be accessed in bytes, half words (16 bits) or full words (32 bits).
www.geehy.com Page 13 Clock The four clock sources HXT, HXT user-ext, HIRC and LIRC can be the master clock, as shown in the following table: Table 4 It can be used as the clock source of the master clock Clock source description HXT 1-24MHz high speed external crystal oscillator HXT user-ext Maximum 24MHz high-speed external clock signal HIRC 48MHz high speed internal RC oscillator LIRC 128KHz low speed internal RC oscillator Each clock source can be turned on or off independently to optimize power consumption. In order to make the system start quickly, the clock controller automatically uses HIRC's divide by 8 (HIRC/8) as the master clock after reset. The reason is that the stabilization time of HIRC is short, and the HIRC/8 can ensure the safe start of the system under poor VDD conditions. Once other clock sources are stable, the user program can switch the master clock to another clock source.
www.geehy.com Page 14 4.5.1. Clock tree Figure 5 Clock tree of APM32F003x4x6 series HXT OSC 1-24MHz LIRC 128KHz HIRC RC 48MHz HIRCDIV[2] /1,3 HIRCDIV[1:0] /1,2,4,8 CSS IWDTCLK WUPTHXT clock HIRC HXT LIRC fMASTER fCPU /1,2,4,8,16 ,32,64 HIRCDIV Peripheral clock CCO CPU prescale fCPUOSC_OUT OSC_IN fMASTER MCC[7:0] Note: the counter of WUPT is not provided by fMASTER, so even if the clock of the register has been turned off, the peripheral can continue to run. Power management 4.6.1. Power supply scheme Table 5 Power supply scheme Name Abbreviation of name Voltage range Main power supply VDD/VSS 2.4~5.5V The VDD/VSS pin can supply power to the internal main voltage regulator (MVR) and the internal low power voltage regulator (LPVR), and the outputs of these two regulators together provide 1.5V power supply to the core, Flash and SRAM. 4.6.2. Power supply monitor Two circuits of power-on reset (POR) and power-down reset (PDR), are
www.geehy.com Page 15 integrated inside the product. The two circuits are always in working state, ensuring the normal operation of the system when the power supply exceeds 2V. When the power supply voltage is monitored to be lower than the specified threshold value VPOR/PDR, the system keeps the reset state without an external reset circuit. See 8. Electrical Characteristics for details of VPOR/PDR. Low power consumption mode The product supports three low power consumption modes: Wait mode, Halt mode and Active Halt mode, which can be switched between these modes by setting, as shown in the following table: Table 6 Low power consumption mode Mode type description Wait mode ‒ In the wait mode, the contents of all registers and RAM remain unchanged, and the previously defined clock (master clock state register CLK_CMSR) configuration also remains unchanged. ‒ When an internal or external interrupt request is generated, the CPU wakes up from the wait mode and resumes working. Halt mode ‒ In halt mode, the contents of all registers and RAM remain unchanged, and the configuration of clock (master clock status register CLK_CMSR) remains unchanged by default. ‒ In this mode, in order to save power consumption, the main voltage regulator is turned off, and only the low voltage regulator (and power-down reset) is in working state. ‒ HIRC starts up faster than HXT (see electrical characteristic parameters in data manual). Therefore, in order to reduce the wake- up time of MCU, it is recommended to select HIRC as the clock source of fMASTER before entering pause mode. Active halt mode (Active halt) mode ‒ Active halt mode is similar to halt mode, but it does not require external interrupt wake-up. It uses WUPT to generate an internal wake-up event after a certain delay, and the delayed time can be programmed by the user. ‒ In default status, the main voltage regulator is active and can wake up quickly from active halt mode, but its current consumption cannot be ignored. ‒ In active halt mode, fast wake-up can reduce the response time of CPU and make the switching time between MCU running state and low power consumption mode shortest. General purpose input/output port (GPIO)
16 GPIO pins are embedded, which can switch between input (pull-up, floating),
www.geehy.com Page 16 output (push-pull, open drain) or multiplexing functions. Most GPIO pins are shared with multiplexed peripherals. In addition, some pins have redefined functions, such as analog input, external interrupt, and input/output of chip peripherals, but only one function can be mapped to a pin at the same time. The remapping of multiplexing functions can be realized by controlling option bytes. Please refer to the description of option bytes in the data manual. Communication interface 4.9.1. Universal asynchronous transceiver (USART) Embedded with three USART communication interfaces, USART interface can support 2.5Mbit/s communication rate, and it has SPI emulation, high-precision baud rate generator, smart card emulation, IrDA SIR codec, LIN main mode and single-line half-duplex mode. Table 7 Communication mode of universal asynchronous transceiver Communication mode description Asynchronous communication (USART mode) Full duplex NRZ standard format communication (mark/space) Programmable transmission and reception baud rate is up to 2.5Mbit/s, which can follow any standard baud rate at input frequency Independent enable bits for sending and receiving There are two wake-up modes: address bit (MSB) and idle line (interrupt) Transmission error detection and interrupt generation Parity control Synchronous communication Full duplex synchronous transmission SPI main operation 8-bit data communication Maximum speed: 1mbit/s at 16MHz (fcpu/16) LIN main mode Transmit: generate a 13-bit synchronous interrupt frame Receive: detect an 11-bit interrupt frame 4.9.2. I2C bus Embedded with an I2C interface, it is led out through data pin (SDA) and clock pin (SCL), and can turn on or interrupt disable. It can work in multi-master mode
www.geehy.com Page 17 or slave mode, supports 7-bit and 10-bit addressing, and allows connection to standard (up to 100kHz) or fast (up to 400kHz) I2C bus. I2C can receive and send data, convert serial data into parallel data when receiving, and convert parallel data into serial data when sending. I2C bus functions are as follows: Table 8 I2C bus function Name description I2C main function Generate start and end clocks I2C slave function Programmable I2C address detection Stop bit detection I2C Other functions General generation and detection of 7-bit /10-bit addressing Support different communication rates: Standard speed (up to 100KHz) Fastest speed (up to 400KHz) 4.9.3. Serial peripheral interface (SPI) Embedded with an SPI interface, it allows the chip to communicate with external devices in half/full duplex serial mode. It can be configured as master mode or slave mode, with 8 bits per frame. Full-duplex and half-duplex communication rates can support 8 Mbit/s. SPI interface has wake-up function. Table 9 Characteristics of serial peripheral interface Characteristics description Maximum speed Master/slave 8Mbit/s(fMASTER/2) Full duplex synchronous transmission Synchronous transmission is transmitted on two data lines with or without bidirectional transmission Master-slave operation with two choices Hardware or software CRC calculation - Tx and Rx buffers 1 byte Slave/master select input pin - Analog/digital converter (ADC) ADC is a 12-bit successive comparison analog-to-digital converter, which can provide 8 multifunctional external input channels and 1 internal channel. channels AIN0~AIN7 come from IO channel, while channel AIN8 comes from
www.geehy.com Page 18 on-chip VREF_BUFFER (a relatively stable standard voltage of 1.2V). ADC supports differential input mode in addition to single-ended mode, but channel AIN8 only supports single-ended input mode. The analog watchdog function allows one channel, multiple channels or all selected channels to be monitored very accurately. When the monitored signal exceeds the preset threshold, an interrupt will be generated. Events generated by the advanced control timer (TMR1) can cascade trigger ADC respectively, and applications can synchronize AD conversion with clock. Table 10 ADC product features Product features description Input voltage value 0 to VDD Conversion mode Single, continuous and buffered continuous conversion mode Buffer Size (10x12 bits) Conversion channel 9, which can be converted once or continuously Differential input Four pairs Analog watchdog Programmable upper and lower limits of analog watchdog Analog watchdog interrupt Convenient handling of analog watchdog events External trigger input It can be triggered by a rising edge event on the ADC_ETR pin Triggered from TMR1 TRGO Yes End of conversion interrupt Settable Timer The product includes two advanced control timers (TMR1 and TMR1A), one general timer (TMR2), one basic timer (TMR4), two watchdog timers, one system tick timer and one automatic wake-up timer. 4.11.1. Advanced control timer (TMR1 and TMR1A) Advanced timer functions are shown in the following table: Table 11 Advanced control timer Timer type Advanced control timer Timer TMR1 TMR1A
www.geehy.com Page 19 Timer type Advanced control timer Counting resolution 16 bits 16 bits Counter type Up, down, up/down Up, down, up/down Prescaler coefficient Any integer between 1 and 65536 Any integer between 1 and 65536 Capture/ Comparison Channels 4 4 Complementary output Yes Yes Function description ‒ Control the synchronous mode of timer with external signal ‒ When the braking signal appears, the timer can be forced to output to a specific state ‒ Two complementary outputs and software controllable dead time channels ‒ Encoder mode ‒ Interrupt source: 4 input capture/output comparison, 1 overflow/update and 1 brake signal interrupt This is a high-end timer, which is suitable for various control applications. Its complementary output, dead-time control and center- aligned PWM functions make its application fields extend to motor control, lighting and half-bridge driving modes. 4.11.2. General timer (TMR2) General timer functions are shown in the following table: Table 12 General timer Timer type General timer Timer TMR2 Counting resolution 16 bits Counter type Up Prescaler coefficient Exponential power of 2 between 1 and 32768 Capture/ Comparison Channels Complementary output - Function description Use external signal to control timer and synchronization circuit interconnected by timer Interrupt generation event: ‒ Update: the counter overflows upwards, and the counter initializes (via software) ‒ Input capture ‒ Output comparison
www.geehy.com Page 20 4.11.3. Basic timer (TMR4) The basic timer functions are as follows: Table 13 Basic timer Timer type Basic timer Timer TMR4 Counting resolution 8 bits Counter type Up Prescaler coefficient Exponential power of any 2 from 1 to 128 Capture/ Comparison Channels Complementary output - Function description ‒ Used to connect with external signals or cascade timers. ‒ Interrupt generation. [When the counter is updated (the counter overflows) and when the trigger signal is input] 4.11.4. Watchdog (WDT) Two watchdogs (independent watchdog and window watchdog) are embedded in the product, which can be used to detect and solve faults caused by software errors, thus improving the system security. The following table shows the comparative data of two watchdogs. Table 14 Watchdog (WDT) Name Counter Resolver Counter type Prescaler coefficient Function description Independent watchdog (IWDT) 8 bits down Between 4 and 256 Any exponential power of 2 ‒ It is driven by an internal independent 128kHz LIRC RC oscillator as a clock source, so it still works as usual even if the master clock fails. ‒ The whole system can be reset in case of problems. ‒ It can provide timeout management for applications. ‒ It can be configured as a software or hardware startup watchdog. Window watchdog （WWDT） 7 bits down - ‒ Used to detect software faults, when it happens is generated by external interference or unexpected logic conditions, which causes the application
www.geehy.com Page 21 Name Counter Resolver Counter type Prescaler coefficient Function description to abandon its normal sequence. ‒ Driven by the master clock, it has early interrupt warning function. ‒ It can be configured as a software or hardware startup watchdog. 4.11.5. System tick timer (SysTick) System tick timer is a standard 24-bit down counter with automatic reloading function. When the counter is 0, it can generate a masked system interrupt. 4.11.6. Automatic wake-up timer (WUPT) WUPT can provide an internal wake-up time reference when MCU enters low power Active Halt mode. The clock of the time reference is provided by the internal low-speed RC oscillator clock (LIRC) or the pre-divided HXT crystal oscillator clock. BUZZER (Buzzer) Embedded with a buzzer, when the LS clock works at 128kHz, it can generate a buzzer signal with frequency of 1kHz, 2kHz or 4kHz.
www.geehy.com Page 22 5. Electrical Specification Test condition Unless otherwise specified, all voltage parameters are referenced to VSS. 5.1.1. Maximum and minimum value Unless otherwise specified, all products are tested on the production line at TA = 25℃. Its maximum and minimum values can support the worst environmental temperature, power supply voltage and clock frequency. In the notes at the bottom of each table, it is stated that the data obtained through comprehensive evaluation, design simulation or process characteristics are not tested on the production line; On the basis of comprehensive evaluation, after passing the sample test, take the average value and add and subtract three times the standard deviation (average ±3∑) to get the maximum and minimum values. 5.1.2. Typical value Unless otherwise specified, typical data are based on TA=25°C and VDD=3.3V and 5V. 5.1.3. Typical curve Unless otherwise specified, typical curves are only used for design guidance.
www.geehy.com Page 24 Figure 7 Pin input voltage measurement scheme APM32F003x4x6 pin VIN Testing under general working conditions Table 15 General working conditions Symbol Parameter Condition Min Max Unit fHCLK Internal AHB clock frequency - - 48 MHz VDD Standard operating voltage - 2.4 5.5 V VCAP VCORE external capacitance - 470 3300 nF Absolute maximum rating If the load on the device exceeds the absolute maximum rating, it will cause permanent damage to the device. Only the maximum load that can be borne is given here, and there is no guarantee that the device functions normally under this condition. 5.3.1. Maximum temperature characteristics Table 16 Temperature characteristics Symbol description Numerical value Unit TSTG Storage temperature range -65 ~150 °C TJ Maximum junction temperature 150 °C 5.3.2. Maximum rated voltage characteristics Table 17 Maximum rated voltage characteristics Symbol description Min Max Unit VDD-VSS External main supply voltage 0.3 - V
www.geehy.com Page 25 Symbol description Min Max Unit VIN Input voltage on the true open drain pin VSS-0.3 6.5 Input voltage on other pins VSS-0.3 VDD+0.3 |VDDx-VDD| Voltage difference between different power supply pins - 50 mV |VSSx-VSS| Voltage difference between different grounding pins - 50 5.3.3. Maximum rated current characteristics Table 18 Maximum rated current characteristics Symbol description Max Unit IVDD Total current through VDD power line (supply current) 100 mA IVSS Total current through VSS ground (outflow current) 80 IIO Current sink on any I/O and control pins 20 Pull current on any I/O and control pins -20 IINJ(PIN) Injection current of NRST pin ±4 Injection current of OSC_IN pin of HXT and OSC_IN pin of LXT Injection current of other pins ±4 ΣIINJ(PIN) Total injection current on all I/O and control pins ±20 5.3.4. Maximum electrostatic characteristics Table 19 Electrostatic discharge (ESD) （1） Symbol Parameter Condition Max Unit VESD(HBM) Electrostatic discharge voltage (manikin) TA=+25°C 8000 V VESD(CDM) Electrostatic discharge voltage (charging equipment model) TA=+25°C 2000 Note: Samples are measured by a third-party testing organization and are not tested in production. 5.3.5. Static latch Table 20 Static latch Symbol Parameter Condition Type LU Static latch class TA=+25°C/105°C A
www.geehy.com Page 26 Flash memory characteristics Table 21 Flash storage characteristics Symbol Parameter Condition Min Typ Max Unit tprog 16-bit programming time TA=-40~105°C VDD=2.95~5.0V 22.4 22.97 23.8 μs tERASE Page (1kbyte) erase time TA=-40~105°C VDD=2.95~5.0V 1.48 1.55 1.64 ms tME Whole erase time TA=25°C VDD=3.3V 6.32 6.57 6.96 ms Vprog Programming voltage TA=-40~105°C 2 - 5.5 V tRET Data saving time TA=125°C 18 - - years NRW Erase cycle TA=25°C 100K - - cycles Clock 5.5.1. External clock source characteristics High Speed External Clock Generated by Crystal Resonator (HXT osc) For detailed parameters (frequency, package, precision, etc.) of crystal resonator, please consult the corresponding manufacturer. Table 22 Characteristics of HXT 1-24MHz oscillator Symbol Parameter Condition Min Typ Max Unit fHXT Oscillator frequency - 1 - 24 MHz RF Feedback resistance - - 300 - kΩ C Recommended load capacitance - - - 20 pF IDD(HXT) HXT oscillator power consumption C=20pF, fOSC=16MHz - - 6 (startup) 1.6 (stabilized) mA C=10pF, fOSC=16MHz - - 6 (startup) 1.2 (stabilized) tSU(HXT) Startup time VDD is stable - 1 - ms 5.5.2. Internal clock source characteristics Test of High Speed Internal (HIRC) Oscillator Table 23 HIRC oscillator characteristics Symbol Parameter Condition Min Typ Max Unit fHIRC Frequency - - 48 - MHz
www.geehy.com Page 27 Low speed internal (LIRC) oscillator test Table 24 LIRC oscillator characteristics Symbol Parameter Min Typ Max Unit fLIRC Frequency - 128 - KHz ACCLIRC Accuracy of oscillator (VDD=3.3-5V,-40°C≤TA≤105°C) -5 - 5 % tSU(LIRC) Startup time of LIRC oscillator - - 5 μs IDD(LIRC) LIRC oscillator power consumption - 5 - μA Time to wake up from low power mode HIRC is used as the clock source for wake-up. Table 25 Wake-up time in low power mode Symbol Parameter Condition Typ Max Unit tWU(WFI) Wake-up time from waiting to running fCPU=fMASTER=48MHz 0.61 - us fCPU=fMASTER=24MHz 1.17 - fCPU=fMASTER=12MHz 2.36 - fCPU=fMASTER=6MHz 4.67 - tWU(AH) Wake-up time from active shutdown MVR on Flash running HIRC after wake-up 5.52 8.36 ACCHIRC Accuracy of HIRC oscillator User calibration Given VDD and TA, the user uses the CLK_HIRCTRI MR register for calibration. -1 - 1 % Factory calibration VDD=3.3-5V, 40°C≤TA≤105° C -5 - 5 % tSU(HIRC) HIRC oscillator start-up time (including calibration) - - - 0.8 μs IDD(HIRC) HIRC oscillator power consumption - - 120 μA
www.geehy.com Page 28 Symbol Parameter Condition Typ Max Unit mode to run mode MVR off Flash running HIRC after wake-up 53.13 55 tWU(H) Wake-up time from shutdown to operation Flash running mode 55.21 - Power-on/power-down reset characteristic test Table 26 Power-on/power-down reset working conditions (TA=25℃) Symbol Parameter Condition Min Typ Max Unit tTEMP Reset release delay VDD rising 0.58 0.79 0.92 ms VIT+ Power-on reset threshold - 1.79 2.00 2.10 V VIT- Power failure reset threshold - 1.70 1.73 1.76 V VHYS(BOR) BOR hysteresis - - 100 - mV Power consumption The current consumption of MCU is affected by many parameters, such as voltage, temperature, IO status, program location in memory, software configuration, frequency and so on. The current values given in this section are measured by executing CRC algorithm, compiling environment Keil V5 and compiling optimization level L0. The microcontroller is under the following conditions: ⚫ All I/O pins are in input mode and connected to a static level VDD or VSS (non-loaded). ⚫ Unless otherwise specified, all peripherals are turned off. ⚫ Unless otherwise specified, typical values are measured at 25℃, 3.3V or 5V. ⚫ Unless otherwise specified, the maximum values are measured at 105℃ and 5.5V power supply. Table 27 Typical operating mode power consumption Symbol Parameter Condition Voltage(TA=25℃) Unit 3.3V 5V IDD HXT=24MHz，FCPU=24MHz 2.5 3.1 mA
www.geehy.com Page 29 Table 28 Maximum power consumption in operation mode Symbol Parameter Condition Voltage (TA=105℃) Unit 3.3V 5V 5.5V IDD Supply current in running mode in RAM HXT=24MHz，FCPU=24MHz 2.68 3.30 3.56 mA HXT=16MHz，FCPU=16MHz 2.14 2.75 2.99 HIRC=48MHz，FCPU=48MHz 3.63 3.70 3.75 HIRC=48MHz，FCPU=24MHz 2.42 2.47 2.54 HIRC=48MHz，FCPU=375KHz 1.11 1.13 1.22 HIRC=48MHz，FCPU=46.875KHz 0.63 0.64 0.74 HIRC=16MHz，FCPU=16MHz 1.57 1.58 1.68 HIRC=16MHz，FCPU=125KHz 0.73 0.74 0.84 HIRC=16MHz，FCPU=15.625MHz 0.58 0.58 0.68 LIRC=128KHz，FCPU=128KHz 0.43 0.43 0.55 Supply current in HXT=24MHz，FCPU=24MHz 4.61 5.30 5.49 HXT=16MHz，FCPU=16MHz 3.42 4.10 4.30 Supply current in running mode in RAM HXT=16MHz，FCPU=16MHz 2 2.6 HIRC=48MHz，FCPU=48MHz 3.2 3.2 HIRC=48MHz，FCPU=24MHz 2.2 2.2 HIRC=48MHz，FCPU=375KHz 0.94 0.96 HIRC=48MHz，FCPU=46.875KHz 0.51 0.51 HIRC=16MHz，FCPU=16MHz 1.4 1.4 HIRC=16MHz，FCPU=125KHz 0.61 0.61 HIRC=16MHz，FCPU=15.625MHz 0.47 0.47 LIRC=128KHz，FCPU=128KHz 0.33 0.34 Supply current in running mode in Flash HXT=24MHz，FCPU=24MHz 4.2 4.7 HXT=16MHz，FCPU=16MHz 3.1 3.7 HIRC=48MHz，FCPU=48MHz 4.8 4.8 HIRC=48MHz，FCPU=24MHz 3.8 3.8 HIRC=48MHz，FCPU=375KHz 0.97 0.97 HIRC=48MHz，FCPU=46.875KHz 0.51 0.52 HIRC=16MHz，FCPU=16MHz 2.5 2.6 HIRC=16MHz，FCPU=125KHz 0.62 0.63 HIRC=16MHz，FCPU=15.625KHz 0.47 0.47 LIRC=128KHz，FCPU=128KHz 0.34 0.34
www.geehy.com Page 30 Symbol Parameter Condition Voltage (TA=105℃) Unit 3.3V 5V 5.5V running mode in Flash HIRC=48MHz，FCPU=48MHz 5.47 5.62 5.64 HIRC=48MHz，FCPU=24MHz 4.35 4.47 4.50 HIRC=48MHz，FCPU=375KHz 1.14 1.25 1.28 HIRC=48MHz，FCPU=46.875KHz 0.63 0.73 0.77 HIRC=16MHz，FCPU=16MHz 2.85 2.86 2.96 HIRC=16MHz，FCPU=125KHz 0.75 0.75 0.85 HIRC=16MHz，FCPU=15.625KHz 0.58 0.58 0.68 LIRC=128KHz，FCPU=128KHz 0.44 0.55 0.58 Table 29 Typical power consumption in WAIT mode Symbol Parameter Condition Voltage (TA=25℃) Unit 3.3V 5V IDD Supply current in WAIT mode HXT=24MHz，FCPU=24MHz 1.5 2.04 mA HXT=16MHz，FCPU=16MHz 1.32 1.9 HIRC=48MHz，FCPU=48MHz 1.2 1.2 HIRC=48MHz，FCPU=24MHz 1.1 1.1 HIRC=48MHz，FCPU=375KHz 0.93 0.93 HIRC=48MHz,FCPU=46.875KHz 0.51 0.51 HIRC=16MHz，FCPU=16MHz 0.68 0.69 HIRC=16MHz，FCPU=125KHz 0.60 0.61 HIRC=16MHz,FCPU=15.625MHz 0.46 0.47 LIRC=128KHz，FCPU=128KHz 0.33 0.33 Table 30 Maximum power consumption in WAIT mode Symbol Parameter Condition Voltage (TA=105℃) Unit 3.3V 5V 5.5V IDD Supply current in WAIT mode HXT=24MHz，FCPU=24MHz 1.55 2.10 2.40 mA HXT=16MHz，FCPU=16MHz 1.39 1.95 2.21 HIRC=48MHz，FCPU=48MHz 1.36 1.36 1.45 HIRC=48MHz，FCPU=24MHz 1.27 1.27 1.37 HIRC=48MHz，FCPU=375KHz 1.09 1.09 1.18 HIRC=48MHz,FCPU=46.875KHz 0.62 0.63 0.71 HIRC=16MHz，FCPU=16MHz 0.82 0.83 0.90 HIRC=16MHz，FCPU=125KHz 0.73 0.73 0.86
www.geehy.com Page 31 HIRC=16MHz,FCPU=15.625MHz 0.58 0.58 0.71 LIRC=128KHz，FCPU=128KHz 0.43 0.43 0.51 Table 31 Typical power consumption in active halt mode Symbol Parameter Condition Voltage (TA=25℃) Unit MVR Flash mode Clock source 3.3V 5V IDD Supply current in active shutdown mode Turn on Operation HXT=16MHz 780 1360 µA Turn on Operation HXT=24MHz 800 1390 Turn on Power down HXT=16MHz 780 1360 Turn on Power down HXT=24MHz 800 1390 Turn on Operation LIRC=128KHz 17.1 18.8 Turn on Power down LIRC=128KHz 17.0 18.5 Turn off Operation LIRC=128KHz 4.9 6.6 Turn off Power down LIRC=128KHz 4.8 6.4 Table 32 Maximum power consumption in active halt mode Symbol Parameter Condition Voltage (TA=105℃) Unit MVR Flash mode Clock source 3.3V 5V 5.5V IDD Supply current in active shutdown mode Turn on Operation HXT=16MHz 780 1350 1640 µA Turn on Operation HXT=24MHz 810 1380 1670 Turn on Power down HXT=16MHz 780 1350 1630 Turn on Power down HXT=24MHz 800 1380 1670 Turn on Operation LIRC=128KHz 55.64 57.72 59.82 Turn on Power down LIRC=128KHz 48.24 50.98 52.42 Turn off Operation LIRC=128KHz 32.30 34.34 35.34 Turn off Power down LIRC=128KHz 26.44 28.53 29.46 Table 33 Typical power consumption in halt mode Symbol Parameter Condition Voltage (TA=25℃) Unit 3.3V 5V IDD Supply current in halt mode Running mode of Flash, HIRC as clock source after wake up 3.53 5.2 µA Flash power-down mode, HIRC as clock source after wake up 3.43 5.0
www.geehy.com Page 32 Table 34 Maximum power consumption in shutdown mode Symbol Parameter Condition Voltage (TA=105℃) Unit 3.3V 5V 5.5V IDD Supply current in halt mode Running mode of Flash, HIRC as clock source after wake up 30.65 32.39 33.77 µA Flash power-down mode, HIRC as clock source after wake up 24.70 26.72 27.44 Table 35 Typical value of peripheral power consumption (VDD=5V,TA=25℃) Symbol Parameter 16MHz 48MHz Unit IDD(TMR1) TMR1 supply current 98 300 µA IDD(TMR1A) TMR1A supply current 58 170 IDD(TMR2) TMR2 supply current 56 168 IDD(TMR4) TMR4 timer supply current 15 46 IDD(USART1) USART1 supply current 56 168 IDD(USART2) USART2 supply current 100 310 IDD(USART3) USART3 supply current 55 170 IDD(SPI) SPI supply current 23 68 IDD(I2C) I2C supply current 37 110 IDD(ADC1) Supply current during ADC1 conversion 290 680 I/O port characteristics Table 36 I/O static characteristics and AC characteristics (VDD=2.4~5.5V, TA=-40~105°C) Symbol Parameter Condition Min Typ Max Unit VIL Input low level voltage VDD=5V -0.3 - 0.3xVDD V VIH Input high level voltage 0.7xVDD - VDD+0.3 Vhys Voltage hysteresis - 700 - mV Rpu pull up resistor VDD=5V,VIN=VSS 55 63 66 kΩ tR,tF Rise and fall time (10%-90%) Fast I/O port with load capacitance of 50pF - - 17 nS Standard and high sinkI/O port, load capacitance 50pF - - 17 Ilkg Digital input leakage current VSS≤VIN≤VDD - - ±1 μA
www.geehy.com Page 33 Table 37 Output drive current (true open drain port) Symbol Parameter Condition Max Unit VOL Output low level IIO=10mA，VDD=5.0V 0.8 V Output low level IIO=10mA，VDD=3.3V 0.7 Output low level IIO=20mA，VDD=5.0V 1.2 V Table 38 Output drive current (high sink current port) Symbol Parameter Condition Min Max Unit VOL Output low level IIO=10mA，VDD=5.0V - 0.4 Output low level IIO=10mA，VDD=3.3V - 0.6 V Output low level IIO=20mA，VDD=5.0V - 0.9 VOH Output high level IIO=10mA，VDD=5.0V 4.4 - V Output high level IIO=10mA，VDD=3.3V 2.5 - Output high level IIO=20mA，VDD=5.0V 3.8 - NRST pin characteristics The NRST pin input drive adopts CMOS process, which is connected with a permanent pull-up resistor RPU. Table 39 NRST pin characteristics Symbol Parameter Condition Min Typ Max Unit VIL(NRST) NRST input low voltage - -0.3V - 0.3xVDD V VIH(NRST) NRST input high voltage - 0.7xVDD - VDD+0.3 VOL(NRST) NRST outputs a low voltage IOL=2mA - - 0.5 V Vhys(NRST) NRST Schmitt trigger Voltage hysteresis - - 600 - mV RPU pull up resistor - 30 60 80 kΩ VF(NRST) NRST input filter pulse - - - 75 ns VNF(NRST) NRST input unfiltered pulse - 500 - - ns tOP(NRST) Output pulse width of NRST - 20 - - us
www.geehy.com Page 34 Communication interface 5.10.1. I2C interface characteristics Table 40 I2C interface characteristics Symbol Parameter Standard I2C Fast I2C Unit Min Max Min Max tw(SCLL) SCL clock low time 5.03 - 1.73 - μs tw(SCLH) SCL clock high time 4.90 - 0.72 - tsu(SDA) SDA setup time 4420 - 1120 - ns th(SDA) SDA data holding time 0 313.09 0(1) 335.97 tr(SDA) tr(SCL) SDA and SCL rise time - 300.12 - 301.24 tf(SDA) tf(SCL) SDA and SCL fall time - 21.3 - 21.51 th(STA) Start condition holding time 4.98 - 0.82 - μs tsu(STA) Repeated start condition setup time 4.95 - 0.87 - tsu(STO) Setup time of stop condition 4.94 - 0.84 - μs tw(STO:STA) Time from stop condition to start condition (bus idle) 5.4 - 2.08 - μs Note: (1) In order to facilitate bridging of undefined areas along the falling edge of SCL, it is recommended that the device provide a minimum hold time of 300ns internally for the SDA signal. Figure 8 Bus AC waveform and test circuit I²C Bus VDD VDD 4.7KΩ 4.7KΩ SCL SDA Repeated start condition Start condition tsu(STA) tsu(STO) tsu(STO:STA)Stop condition Start condition th(SDA) tf(STA) SDA tr(SDA) tsu(SDA) tf(SCL)tf(SCL)tw(SCLL) SCL th(STA) tw(SCLH) MCU
www.geehy.com Page 35 5.10.2. SPI interface characteristics Table 41 SPI characteristics Symbol Parameter Condition Min Max Unit fSCK 1/tc(SCK) SPI clock frequency holotype 8 MHz Slave mode 8 tr(SCK) tf(SCK) SPI clock rise and fall time Load capacitance: C=30pF - 16.854 ns tsu(NSS) NSS setup time Slave mode 433.33 - th(NSS) NSS holding time Slave mode 115.43 - tw(SCKH) tw(SCKL) SCK high and low time holotype 54.592 57.4723 tsu(MI) tsu(SI) Data input setup time holotype 30.304 - Slave mode 50.889 - th(MI) th(SI) Data input holding time holotype 64.746 - Slave mode 52.22 - ta(SO) Data output access time Slave mode 2.530 12.272 tdis(SO) Data output prohibition time Slave mode 25.235 - tv(SO) Effective time of data output Slave mode (after enable edge) - 29.605 tv(MO) Effective time of data output Master mode (after enable edge) - 7.220 th(SO) Data output holding time Slave mode (after enable edge) 16.222 - th(MO) Master mode (after enable edge) 8.356 - Figure 9 SPI timing diagram—slave mode and CPHA=0 NSS Input MOSI Input MISO Output CPHA=0 CPOL=0 CPHA=0 CPOL=1 MSB OUT BIT 6~1 OUT LSB OUT LSB INMSB IN BIT 6~1 IN th(NSS)tc(SCK) tr(SCK) tf(SCK) tdls(SO)th(SO)tV(SO) ta(SO) tSU(SI) tSU(NSS) th(SCKH) tW(SCKL) SCK Input
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www.geehy.com Page 38 Symbol Parameter Condition Min Typ Max Unit tS Sampling time fADC=14MHz - 0.107 - μs TCONV Sampling and conversion time fADC=14MHz - 1 - μs Figure 12 Typical application of ADC RAIN CADC VADC RADC SAR CAIN Note: Users can choose whether to increase parasitic capacitance based on their actual application(Capacitance value to be selected as needed). The formula for calculating the maximum external input impedance is as follows： Formula 1: formula of maximum RAIN RAIN< 𝑇𝑆 𝐶𝐴𝐷𝐶 Ｘ ln(2𝑁+2) -RADC Table 43 12-bit ADC accuracy Symbol Parameter Condition Typ Max Unit |ET| Total uncorrected error 3.3V~5V 6.5 - LSB |EO| offset error 3.3V~5V 2 - |EG| Gain error 3.3V~5V 4.5 - |ED| Differential linear error 3.3V~5V 1.5 - |EL| Integral linearity error 3.3V~5V 2.8 -
www.geehy.com Page 39 Figure 13 ADC Accuracy Characteristics 10211 2 3 4 5 6 7 1022 1023 1024 1021 1022 1023 EO EG (1) (3) (2) ED
1 LSB IDEAL
Note: (1)The ideal transfer curve,(2)End point correlation line, (3)Example of an actual transfer curve 1LSBIDEAL Formula : 1LSBIDEAL=（VDD-VSS）/1024 Table 44 Explanation of the Parameter Meaning of ADC Accuracy Characteristics Symbol Parameter Description ET Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves EO Offset Error deviation between the first actual transition and the first ideal one EG Gain Error deviation between the last ideal transition and the last actual one ED Differential Linearity Error maximum deviation between actual steps and the ideal one EL Integral Linearity Error maximum deviation between any actual transition and the end point correlation line
www.geehy.com Page 40 6. Package Information Table 45 APM32F003x4x6 Package Name Size Marking of Apex samples TSSOP20、 SOP20 6.5*4.4*0.9 LLLLLLL ZZ YYWW 32F003x4Product model LOT batch Pin Revision Code Date Code Arm authorization markGeehy Logo QFN20 3*3*0.55 F003x4Product model LOT batch Pin YYWW ：Date Code ZZ ： Revision Code LLLLLLL YYWW ZZ Figure 14 Package diagram of TSSOP20 PIN 1 eb E A A D Θ DETAILA H L C Table 46 Package dimensions of TSS0P20 SYMBOL Dimensions IN Millimeters Dimensions IN Inches MIN MAX MIN MAX D 6.400 6.600 0.252 0.259 E 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012
www.geehy.com Page 41 SYMBOL Dimensions IN Millimeters Dimensions IN Inches MIN MAX MIN MAX c 0.090 0.200 0.004 0.008 E1 6.250 6.550 0.246 0.258 A - 1.200 - 0.047 A2 0.800 1.000 0.031 0.039 A1 0.050 0.150 0.002 0.006 e 0.65(BSC) 0.026(BSC) L 0.500 0.700 0.020 0.028 H 0.25(TYP) 0.01(TYP) θ 1 (1) Dimensions are displayed in mm (2) BSC is a unit without error, in this case mm Figure 15 TSSOP20 Recommended Welding Layout
www.geehy.com Page 42 Figure 16 Package diagram of SOP20 E1 E A C L Θ b e D Table 47 Package dimensions of SOP20 SYMBOL Dimensions IN Millimeters Dimensions IN Inches MIN MAX MIN MAX A 2.350 2.650 0.093 0.104 A1 0.100 0.300 0.004 0.012 A2 2.100 2.500 0.083 0.098 b 0.330 0.510 0.013 0.020 c 0.204 0.330 0.008 0.013 D 12.520 13.000 0.493 0.512 E 7.400 7.600 0.291 0.299 E1 10.210 10.610 0.402 0.418 e 1.270(BSC) 0.050(BSC) L 0.400 1.270 0.016 0.050 θ 0 (1) Dimensions are displayed in mm (2) BSC is a unit without error, in this case mm
www.geehy.com Page 43 Figure 17 Package diagram of QFN20 Table 48 Package dimensions of QFN20 - SYMBOL MIN NOM MAX TOTAL THICKNESS A 0.50 0.55 0.60 STAND OFF A1 0 0.02 0.05 LEAD WIDTH b 0.20 0.25 0.30 BODY SIZE X D 2.90 3.00 3.10 Y E 2.90 3.00 3.10 LEAD PITCH e 0.50BSC LEAD LENGTH L 0.30 0.35 0.40 L1 0.50 0.55 0.60 (1) Dimensions are displayed in mm (2) BSC is a unit without error, in this case mm
www.geehy.com Page 45 Table 49 Tape packaging parameter specification table Device Package Type Pins SPQ Reel Diameter (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant APM32F003F6P7 TSSOP 20 9000 330 6.8 6.9 8 1.5 16 Q1 APM32F003F6P6 TSSOP 20 9000 330 6.8 6.9 8 1.5 16 Q1 APM32F003F4P6 TSSOP 20 9000 330 6.8 6.9 8 1.5 16 Q1 Figure 21 Pin1 Orientation and tray chamfer
www.geehy.com Page 46 Figure 22 Tray Dimensions Table 50 Tray packaging parameter specification table Device Package Type Pins SPQ X-Dimension (mm) Y-Dimension (mm) X-Pitch (mm) Y-Pitch (mm) Tray Length (mm) Tray Width (mm)
www.geehy.com Page 47 Figure 23 Package drawing of SOP&TSSOP material pipe left right Table 51 Specification table of SOP&TSSOP material tube packaging parameters Device Package Type Pins Qty Per Tube SPQ L (mm) W (mm) H (mm) APM32F003F6P6 TSSOP20 20 46 14720 327 8.5 3.2 APM32F003F4P6 TSSOP20 20 46 14720 327 8.5 3.2 APM32F003F6M6 SOP20 20 35 11200 516 12.7 5 APM32F003F4M6 SOP20 20 35 11200 516 12.7 5
www.geehy.com Page 48 8. Ordering Information APM32 F 003 F 6 P 6 XXX Product series APM32=Arm-based 32-bit MCU Product type F=Foundation Product subseries 003=Entry-level Number of pins F = 20 pins Flash memory capacity 4 = 16 Kbytes 6 = 32 Kbytes Package U = QFN M=SOP P=TSSOP Temperature range 6 = -40 ~85 7 = -40 ~105 Option XXX=Programmed device code R=Reel package Blank=Tray package T=Tube package Table 52 Order information list Order code Flash(KB) SRAM(KB) Packaging SPQ Temperature range APM32F003F4P6-T 16 2 TSSOP20 14720 Industrial grade -40℃~85℃ APM32F003F6P6-T 32 4 TSSOP20 14720 Industrial grade -40℃~85℃ APM32F003F4P6-R 16 2 TSSOP 20 9000 Industrial grade -40℃~85℃ APM32F003F4U6 16 2 QFN20 6240 Industrial grade -40℃~85℃
www.geehy.com Page 49 Order code Flash(KB) SRAM(KB) Packaging SPQ Temperature range APM32F003F6P6-R 32 4 TSSOP20 9000 Industrial grade -40℃~85℃ APM32F003F6P7-R 32 4 TSSOP20 9000 Industrial grade -40℃~105℃ APM32F003F6U6 32 4 QFN20 6240 Industrial grade -40℃~85℃ APM32F003F4M6-T 16 2 SOP20 11200 Industrial grade -40℃~85℃ APM32F003F6M6-T 32 4 SOP20 11200 Industrial grade -40℃~85℃
www.geehy.com Page 50 9. Naming of Common Functional Modules Table 53 Naming of common functional modules Naming of common functional modules Full name Abbreviations Reset and clock management unit RCM External interrupt EINT Universal IO GPIO Wake up controller WUPT Buzzer BUZZER Timer TMR Power management unit PMU Digital analogue converter ADC I2C interface I2C serial peripheral interface SPI Universal asynchronous synchronous transceiver USART Flash interface control unit FMC
www.geehy.com Page 51 10. Version History Table 54 Document Version History Date Version Change History 2019.12.27 V1.0.0 New 2020.6.19 V1.0.1 Delete P1 information of table 49 2020.7.6 V1.0.2 Modify the cover page and directory format 2020.9.4 V1.1 (1) Modify the error in Table 14 （Pin definition of APM32F003x4x6(20PIN)）; (2) Adjust the document font; (3) Modify the naming rules in the Ordering Information（Chapter 10）; (4) Modify the order code in Table 48 （Ordering information list） and add a column of minimum number of packages（SPQ） 2021.6.22 V1.2 Modify the page header, cover, and logo 2021.7.20 V1.3 Modify the pin definition of PC4 in Table 14 APM32F003x4x6 (20PIN) Pin Definition 2021.11.9 V1.4 Added PA1 pin function description 2021.12.1 V1.5 Added TSSOP20 braided packing 2022.3.9 V1.6 (1) Adjust the overall structure of the document (2) Added PA1 pin function description 2022.6.22 V1.7 (1) Modify Arm trademark (2) Add the statement (3) Modify product naming rules figure 2023.2.16 V1.8 (1) Add the package size description (2) Modify the clock source description of SysTick (3) Modify system block diagram (4) Modify QFN20 Package Information and add BSC comment 2023.6.21 V1.9 (1) Added typical applications of ADC, calculation formula for maximum external input impedance, and explanation of ADC accuracy characteristics (2) Modify table and image formats 2023.11.27 V2.0 (1) Supplementary I2C interface characteristic information explanation (2) Modify the power supply voltage and power on reset threshold 2024.2.5 V2.1 (1) Modify TSSOP20 braided packaging and ordering information 2024.10 V2.2 (1) Added TSSOP20 Recommended Welding Layout (2) Modify Table22 (HXT frequency) (3) Add flash storage time and erase cycle
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