APA750-PQGB

APA1000-FFGG1152I ACTEL | Alldatasheet

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© 2008 Actel Corporation See the Actel website for the latest version of the datasheet. v5.7 ProASICPLUS® Flash Family FPGAs Features and Benefits High Capacity Commercial and Industrial

• 75,000 to 1 Million System Gates  27 k to 198 kbits of Two-Port SRAM  66 to 712 User I/Os Military  300, 000 to 1 million System Gates  72 k to 198 kbits of Two Port SRAM  158 to 712 User I/Os Reprogrammable Flash Technology  0.22 µm 4 LM Flash-Based CMOS Process  Live At Power-Up (LAPU) Level 0 Support  Single-Chip Solution  No Configuration Device Required  Retains Programmed Design during Power-Down/Up Cycles  Mil/Aero Devices Operate over Full Military Temperature Range Performance  3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military temperature)  Two Integrated PLLs  External System Performance up to 150 MHz Secure Programming  The Industry’s Most Effective Security Key (FlashLock®) Low Power  Low Impedance Flash Switches  Segmented Hierarchical Routing Structure  Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells High Performance Routing Hierarchy  Ultra-Fast Local and Long-Line Network  High-Speed Very Long-Line Network  High-Performance, Low Skew, Splittable Global Network  100% Routability and Utilization I/O  Schmitt-Trigger Option on Every Input  2.5 V/3.3 V Support with Indivi dually-Selectable Voltage and Slew Rate  Bidirectional Global I/Os  Compliance with PCI Spec ification Revision 2.2  Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant  Pin Compatible Packages across the ProASIC PLUS Family Unique Clock Conditioning Circuitry  PLL with Flexible Phase, Multiply/Divide and Delay Capabilities  Internal and/or External Dynamic PLL Configuration  Two LVPECL Differential Pa irs for Clock or Data Inputs Standard FPGA and ASIC Design Flow  Flexibility with Choice of In dustry-Standard Front-End Tools  Efficient Design through Front-End Timing and Gate Optimization ISP Support  In-System Programming (ISP) via JTAG Port SRAMs and FIFOs  SmartGen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks  24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical) Table 1 • ProASICPLUS Product Profile Device APA075 APA150 APA300 1 APA450 APA600 1 APA750 APA1000 1 Maximum System Gates 75,000 150,000 300,000 450,000 600,000 750,000 1,000,000 Tiles (Registers) 3,072 6,144 8,192 12,288 21,504 32,768 56,320 Embedded RAM Bits (k=1,024 bits) 27 k 36k 72 k 108 k 126 k 144 k 198 k Embedded RAM Blocks (256x9) 12 16 32 48 56 64 88 L V P E C L 222 2 2 2 2 P L L 222 2 2 2 2 Global Networks 4 4 4 4 4 4 4 Maximum Clocks 24 32 32 48 56 64 88 Maximum User I/Os 158 242 290 344 454 562 712 JTAG ISP Yes Yes Yes Yes Yes Yes Yes PCI Yes Yes Yes Yes Yes Yes Yes Package (by pin count) TQFP 100, 144 100 – – – – – PQFP 208 208 208 208 208 208 208 PBGA – 456 456 456 456 456 456 FBGA 144 144, 256 144, 256 144, 256, 484 256, 484, 676 676, 896 896, 1152 CQFP 2 208, 352 208, 352 208, 352 CCGA/LGA2 624 624 Notes: 1. Available as Commerci al/Industrial and Military/MIL-STD-883B devices. 2. These packages are available only for Military/MIL-STD-883B devices. v5.7

ProASICPLUS Flash Family FPGAs ii v5.7

Ordering Information

APA1000 FG _ Part Number Speed Grade Blank = Standard Speed F F = 20% Slower than Standard Package Type PQ = Plastic Quad Flat Pack (0.5 mm pitch) TQ = Thin Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) BG = Plastic Ball Grid Array (1.27 mm pitch) CQ = Ceramic Quad Flat Pack (1.05 mm pitch) CG = Ceramic Column Grid Array (1.27 mm pitch) LG = Land Grid Array (1.27 mm pitch) 1152 I Package Lead Count Application (Ambient Temperature Range) G Lead-free packaging Blank = Standard Packaging G = RoHS Compliant Packaging Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) PP = Pre-production ES = Engineering Silicon (Room Temperature Only) M = Military (-55˚C to 125˚C) B = MIL-STD-883 Class B 150,000 Equivalent System GatesAPA150 = 75,000 Equivalent System GatesAPA075 = APA300 300,000 Equivalent System Gates= APA450 450,000 Equivalent System Gates= APA600 600,000 Equivalent System Gates= APA750 750,000 Equivalent System Gates= APA1000 1,000,000 Equivalent System Gates=

ProASICPLUS Flash Family FPGAs v5.7 iii Device Resources General Guideline Maximum performance numbers in this datasheet are based on characterized data. Actel does not guarantee performance beyond the limits specified within the datasheet. User I/Os2 Commercial/Industrial Military/MIL-STD-883B Device TQFP 100-Pin TQFP 144-Pin PQFP 208-Pin PBGA 456-Pin FBGA 144-Pin FBGA 256-Pin FBGA 484-Pin FBGA 676-Pin FBGA 896-Pin FBGA 1152-Pin CQFP 208-Pin CQFP 352-Pin CCGA/ LGA 624-Pin APA075 66 107 158 100 APA150 66 158 242 100 186 3 APA300 158 4 290 4 100 4 186 3, 4 158 248 APA450 158 344 100 186 3 344 3 APA600 158 4 356 4 186 3, 4 370 3 454 158 248 440 APA750 158 356 454 562 5 APA1000 158 4 356 4 642 4, 5 712 5 158 248 440 Notes: 1. Package Definitions: TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array, CQFP = Ceramic Quad Flat Pack, CCGA = Ceramic Column Grid Array, LGA = Land Grid Array 2. Each pair of PECL I/Os is counted as one user I/O. 3. FG256 and FG484 are footprint-compatible packages. 4. Military Temperature Plastic Package Offering 5. FG896 and FG1152 are footprint-compatible packages.

ProASICPLUS Flash Family FPGAs iv v5.7 Temperature Grade Offerings Speed Grade and Temperature Matrix TQ100 C, I C, I TQ144 C, I PQ208 C, I C, I C, I, M C, I C, I, M C, I C, I, M BG456 C, I C, I, M C, I C, I, M C, I C, I, M FG144 C, I C, I C, I, M C, I FG256 C, I C, I, M C, I C, I, M FG484 C, I C, I, M FG676 C, I, M C, I FG896 C, I C, I, M FG1152 C, I CQ208 M, B M, B M, B CQ352 M, B M, B M, B CG624 M, B M, B Note: C = Commercial I = Industrial M = Military B = MIL-STD-883 –F Std. C ✓✓ I ✓ M, B ✓ Note: C = Commercial I = Industrial M = Military B = MIL-STD-883

v5.7 v Table of Contents ProASICPLUS Flash Family FPGAs General Description Recommended Design Practice for V Package Pin Assignments Datasheet Information

ProASICPLUS Flash Family FPGAs v5.7 1-1 General Description The ProASIC PLUS family of devices, Actel’s second- generation Flash FPGAs, offers enhanced performance over Actel’s ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to creat e high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASIC PLUS family offers a unique clock conditioning circuit based on two on-board phase-locked loops (PLLs). The family offers up to one million system gates, supported with up to 198 kbits of two-port SRAM and up to 712 user I/Os, all providing 50 MHz PCI performance. Advantages to the de signer extend beyond performance. Unlike SRAM-bas ed FPGAs, four levels of routing hierarchy simplify routing, while the use of Flash technology allows all functionality to be live at power- up. No external boot PROM is required to support device programming. While on-board security mechanisms prevent access to th e program information, reprogramming can be performed in-system to support future design iterations and field upgrades. The device’s architecture mitigates the complexity of ASIC migration at higher user volume . This makes ProASIC PLUS a cost- effective solution for applic ations in the networking, communications, computing, and avionics markets. The ProASIC PLUS family achieves its nonvolatility and reprogrammability through an advanced Flash-based 0.22 μm LVCMOS process with four layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs. This results in predictable performance compatible with gate arrays. The ProASIC PLUS architecture provides granularity comparable to gate arrays. Th e device core consists of a Sea-of-Tiles™. Each tile can be configured as a flip-flop, latch, or three-input/one-output logic function by programming the appropri ate Flash switches. The combination of fine granul arity, flexible routing resources, and abundant Flash switches allow 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a four-level routing hierarchy. Embedded two-port SRAM blocks with built-in FIFO/RAM control logic can have user-defined depths and widths. Users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking. The unique clock conditioning circuitry in each device includes two clock conditioning blocks. Each block provides a PLL core, delay lines, phase shifts (0 ° and 180°), and clock multipliers/d ividers, as well as the circuitry needed to provide bidirectional access to the PLL. The PLL block contains four programmable frequency dividers which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit also delays or advances the incoming reference clock up to 8 ns (in increments of 0.25 ns). The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high-speed clock and data inputs. To support customer needs for more comprehensive, lower-cost, board-level testing, Actel’s ProASIC PLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. For more information concerning the Flash FPGA implementation, please refer to the "Boundary Scan (JTAG)" section on page 1-11. ProASIC PLUS devices are available in a variety of high- performance plastic packages . Those packages and the performance features discussed above are described in more detail in the following sections.

ProASICPLUS Flash Family FPGAs v5.7 1-3 Live at Power-Up The Actel Flash-based ProASIC PLUS devices support Level 0 of the live at power-up (LAPU) classification standard. This feature he lps in system component initialization, executing cr itical tasks before the processor wakes up, setting up and configuring memory blocks, clock generation, and bus activity management. The LAPU feature of Flash-based ProASIC PLUS devices greatly simplifies total system design and reduces total system cost, often elimin ating the need for Complex Programmable Logic Device (CPLD) and clock generation PLLs that are used for th is purpose in a system. In addition, glitches and brow nouts in system power will not corrupt the ProASIC PLUS device's Flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when syst em power is restored. This enables the reduction or complete removal of the configuration PROM, expe nsive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC PLUS devices simplify total system design, and reduce cost and design risk, while increasing system relia bility and improving system initialization time. Flash Switch Unlike SRAM FPGAs, ProASICPLUS uses a live-on-power-up ISP Flash switch as its programming element. In the ProASICPLUS Flash switch, two transistors share the floating gate, which stores the programming information. One is the sens ing transistor, which is only used for writing and verification of the floating gate voltage. The other is the sw itching transistor. It can be used in the architecture to connect/separate routing nets or to configure logic. It is also used to erase the floating gate (Figure 1-2 on page 1-2). Logic Tile The logic tile cell ( Figure 1-3) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra-fast local and efficient long-line routing resources). Any three-input, one-output logic function (except a three-input XOR) can be configured as one tile. The tile can be conf igured as a latch with clear or set or as a flip-flop with clear or set. Thus, the tiles can flexibly map logic and sequential gates of a design. Figure 1-3  Core Logic Tile Local Routing In 1 In 2 (CLK) In 3 (Reset) Efficient Long-Line Routing

ProASICPLUS Flash Family FPGAs 1-4 v5.7 Routing Resources The routing structure of ProASIC PLUS devices is designed to provide high performance through a flexible four- level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very long-line resources, and high performance global networks. The ultra-fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 1-4). The efficient long-line res ources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASIC PLUS device (Figure 1-5 on page 1-5). Each tile can drive signals onto the efficient long-line resources, which can in turn access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. The high-speed, very long-line resources, which span the entire device with minimal delay, are used to route very long or very high fanout nets. (Figure 1-6 on page 1-6). The high-performance globa l networks are low-skew, high fanout nets that are accessible from external pins or from internal logic ( Figure 1-7 on page 1-7 ). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically with signals accessing every input on all tiles. Figure 1-4  Ultra-Fast Local Resources L L L LL L Inputs Output Ultra-Fast Local Lines (connects a tile to the adjacent tile, I/O buffer, or memory block) L LL

ProASICPLUS Flash Family FPGAs v5.7 1-5 Figure 1-5  Efficient Long-Line Resources LL LLLL LLL L L L LL LLLL LL LLLL LL LLLL Logic Cell Spans 1 Tile Spans 2 Tiles Spans 4 Tiles Spans 1 TileSpans 2 TilesSpans 4 Tiles Logic Tile

ProASICPLUS Flash Family FPGAs 1-6 v5.7 Clock Resources The ProASIC PLUS family offers powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has two clock conditioning blocks containing a phase-locked lo op (PLL) core, delay lines, phase shifter (0 ° and 180°), clock multiplier/dividers, and all the circuitry needed for the selection and interconnection of inputs to the global network (thus providing bidirectional access to the PLL). This permits the PLL block to drive inputs and/or outputs via the two global lines on each side of the chip (four total lines). This circuitry is discussed in more detail in the "ProASICPLUS Clock Management System" section on page 1-13. Clock Trees One of the main architectural benefits of ProASIC PLUS is the set of power- and delay-friendly global networks. ProASIC PLUS offers four global trees. Each of these trees is based on a network of spines and ribs that reach all the tiles in their regions ( Figure 1-7 on page 1-7 ). This flexible clock tree architecture allows users to map up to 88 different internal/exter nal clocks in an APA1000 device. Details on the clock spines and various numbers of the family are given in Table 1-1 on page 1-7. The flexible use of the ProASIC PLUS clock spine allows the designer to cope with several design requirements. Users implementing clock-resource intensive applications can easily route external or gated internal clocks using global routing spines. Users can also drastically reduce delay penalties and save buffering resources by mapping critical high fanout nets to spines. For design hints on using these features, refer to Actel’s Efficient Use of ProASIC Clock Trees application note. Figure 1-6  High-Speed, Very Long-Line Resources PAD RING PAD RING PAD RING I/O RING I/O RING High Speed Very Long-Line Resouces SRAM SRAM

ProASICPLUS Flash Family FPGAs v5.7 1-7 Note: This figure shows routing for only one global path. Figure 1-7  High-Performance Global Network Table 1-1  Clock Spines APA075 APA150 APA300 APA450 APA600 APA750 APA1000 Global Clock Networks (Trees) 4 4 4 4 4 4 4 Clock Spines/Tree 6 8 8 12 14 16 22 Total Spines 24 32 32 48 56 64 88 Top or Bottom Spine Height (Tiles) 16 24 32 32 48 64 80 Tiles in Each Top or Bottom Spine 512 768 1,024 1,024 1,536 2,048 2,560 Total Tiles 3,072 6,144 8,192 12,288 21,504 32,768 56,320 Top Spine Bottom Spine Global Pads Global Pads Global Networks Global Spine Global Ribs High-Performance Global Network Scope of Spine (Shaded area plus local RAMs and I/Os) PAD RING PAD RING PAD RING I/O RING I/O RING

ProASICPLUS Flash Family FPGAs 1-8 v5.7 Array Coordinates During many place-and-rout e operations in Actel’s Designer software tool, it is possible to set constraints that require array coordinates. Table 1-2 is provided as a reference. The array coordinates are measured from the lower left (0,0). They can be used in region constraints for specific groups of core cells, I/Os, and RAM blocks. Wild cards are also allowed. I/O and cell coordinates ar e used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O cells and core cells. In addition, the I/O coordinate system changes depending on the die/package combination. Core cell coordinates start at the lower left corner (represented as (1,1)) or at (1,5) if memory blocks are present at the bottom. Memory coordinates use the same system and are indicated in Table 1-2. The memory coordinates for an APA1000 are illustrated in Figure 1-8. For more information on how to use constraints, see the Designer User’s Guide or online help for ProASIC PLUS software tools. Table 1-2  Array Coordinates Device Logic Tile Memory Rows AllMin. Max. Bottom Top xy x y y y M i n . M a x . APA075 1 1 96 32 – (33,33) or (33, 35) 0,0 97, 37 APA150 1 1 128 48 – (49,49) or (49, 51) 0,0 129, 53 APA300 1 5 128 68 (1,1) or (1,3) (69,69) or (69, 71) 0,0 129, 73 APA450 1 5 192 68 (1,1) or (1,3) (69,69) or (69, 71) 0,0 193, 73 APA600 1 5 224 100 (1,1) or (1,3) (101, 101) or (101, 103) 0,0 225, 105 APA750 1 5 256 132 (1,1) or (1,3) (133, 133) or (133, 135) 0,0 257, 137 APA1000 1 5 352 164 (1,1) or (1,3) (165, 165) or (165, 167) 0,0 353, 169 Figure 1-8  Core Cell Coordinates for the APA1000 (353,169) (352,167) (352,165) (352,164) (352,5) (352,3) (353,0) (352,1) (1,5) (1,1) (1,164) (1,165) (1,3) (1,167) (1,169) (0,0) Core Memory Blocks Memory Blocks

ProASICPLUS Flash Family FPGAs v5.7 1-9 Input/Output Blocks To meet complex system demands, the ProASIC PLUS family offers devices with a large number of user I/O pins, up to 712 on the APA1000. Table 1-3 shows the available supply voltage conf igurations (the PLL block uses an independent 2.5 V supply on the AVDD and AGND pins). All I/Os include ES D protection circuits. Each I/O has been tested to 2000 V to the human body model (per JESD22 (HBM)). Six or seven standard I/O pads are grouped with a GND pad and either a V DD (core power) or V DDP (I/O power) pad. Two reference bias signals circle the chip. One protects the cascaded output drivers, while the other creates a virtual VDD supply for the I/O ring. I/O pads are fully configurab le to provide the maximum flexibility and speed. Each pad can be configured as an input, an output, a tristate driver, or a bidirectional buffer (Figure 1-9 and Table 1-4). Table 1-3  ProASICPLUS I/O Power Supply Voltages VDDP 2.5 V 3.3 V Input Compatibility 2 . 5V 3 . 3V Output Drive 2 . 5V 3 . 3V Figure 1-9  I/O Block Schematic Representation 3.3V/2.5V Signal Control Pull-up Control Pad Y EN A 3.3 V/2.5 V Signal Control Drive Strength and Slew-Rate Control Table 1-4  I/O Features Function Description I/O pads configured as inputs  Selectable 2.5 V or 3.3 V threshold levels  Optional pull-up resistor  Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be configured as an input only, not a bidirectional buffer. This input type may be slower than a standard input under certain conditions and has a typical hysteresis of 0.35 V. I/O macros with an “S” in the standard I/O library have added Schmitt capabilities.  3.3 V PCI Compliant (exc ept Schmitt trigger inputs) I/O pads configured as outputs  Selectable 2.5 V or 3.3 V compliant output signals  2.5 V – JEDEC JESD 8-5  3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)  3.3 V PCI compliant  Ability to drive LVTTL and LVCMOS levels  Selectable drive strengths  Selectable slew rates  Tristate I/O pads configured as bidirectional buffers  Selectable 2.5 V or 3.3 V compliant output signals  2.5 V – JEDEC JESD 8-5  3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)  3.3 V PCI compliant  Optional pull-up resistor  Selectable drive strengths  Selectable slew rates  Tristate

ProASICPLUS Flash Family FPGAs v5.7 1-11 Boundary Scan (JTAG) ProASICPLUS devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective, board-level testing. The basic ProASICPLUS boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers, and instruction register ( Figure 1-12). This circuit supports all manda tory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS) and the optional IDCODE instruction (Table 1-6). Each test section is accessed through the TAP, which has five associated pins: TCK (t est clock input), TDI and TDO (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundar y-scan test usage. Actel recommends that a nominal 20 k Ω pull-up resistor is added to TDO and TCK pins. The TAP controller is a four-b it state machine (16 states) that operates as shown in Figure 1-13 on page 1-12. The ’1’s and ‘0’s represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. ProASIC PLUS devices have to be programmed at least once for complete boundary-scan functionality to be available. Prior to being programmed, EXTEST is not available. If boundary-scan functionality is required prior to programming, refer to online technical support on the Actel website and search for ProASIC PLUS BSDL. Figure 1-12  ProASICPLUS JTAG Boundary Scan Test Logic Circuit Device Logic TDI TCK TMS TRST TDO I/OI/OI/O I/OI/O I/OI/OI/O I/OI/O I/O I/O I/O I/O Bypass Register Instruction Register TAP Controller Test Data Registers Table 1-6  Boundary-Scan Opcodes Hex Opcode EXTEST 00 SAMPLE/PRELOAD 01 IDCODE 0F CLAMP 05 BYPASS FF Table 1-6  Boundary-Scan Opcodes Hex Opcode

ProASICPLUS Flash Family FPGAs 1-12 v5.7 The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architec ture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin may also be used to asyn chronously place the TAP controller in the Test-Logic-Reset state. ProASIC PLUS devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary- scan register chain, which st arts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output, and control ports of an I/O buffer to capt ure and load data into the register to control or observe the logic state of each I/O. Figure 1-13  TAP Controller State Diagram Test-Logic Reset Run-Test/ Idle Select-DR- Scan Capture-DR Shift-DR Exit-DR Pause-DR Exit2-DR Update-DR Select-IR- Scan Capture-IR Shift-IR Exit-IR Pause-IR Exit2-IR Update-IR 11 1 1 1 1 1 1 1 1 1 00 0 0

ProASICPLUS Flash Family FPGAs v5.7 1-13 Timing Control and Characteristics ProASICPLUS Clock Management System ProASICPLUS devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASICPLUS family contains two phase-locked loop (PLL) blocks which perform the following functions:  Clock Phase Adjustment via Programmable Delay (250 ps steps from –7 ns to +8 ns)  Clock Skew Minimization  Clock Frequency Synthesis Each PLL has the following key features:  Input Frequency Range (f IN) = 1.5 to 180 MHz  Feedback Frequency Range (f VCO) = 24 to 180 MHz  Output Frequency Range (f OUT) = 8 to 180 MHz  Output Phase Shif t = 0 ° and 180 °  Output Duty Cycle = 50%  Low Output Jitt er (max at 25°C) VCO <10 MHz. Jitter ±1% or better – 10 MHz < f VCO < 60 MHz. Jitter ±2% or better –f VCO > 60 MHz. Jitter ±1% or better Note: Jitter(ps) = Jitter(%)* period For Example:  Low Power Consumption – 6.9 mW (max – analog supply) + 7.0μW/MHz (max – digital supply) Physical Implementation Each side of the chip contains a clock conditioning circuit based on a 180 MHz PLL block ( Figure 1-14 on page 1- 14). Two global multiplexed lines extend along each side of the chip to provide bidire ctional access to the PLL on that side (neither MUX can be connected to the opposite side's PLL). Each global line has optional LVPECL input pads (described below). The global lines may be driven by either the LVPECL global input pad or the outputs from the PLL block, or both. Each global line can be driven by a different output from the PLL. Unused global pins can be configured as regular I/Os or left unconnected. They default to an input with pull-up. The two signals available to driv e the global networks are as follows (Figure 1-15 on page 1-15 , Table 1-7 on page 1- 15, and Table 1-8 on page 1-16): Global A (secondary clock)  Output from Global MUX A  Conditioned version of PLL output (f OUT) – delayed or advanced  Divided version of either of the above  Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay) Global B  Output from Global MUX B  Delayed or advanced version of f OUT  Divided version of either of the above  Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay) Functional Description Each PLL block contains four programmable dividers as shown in Figure 1-14 on page 1-14 . These allow frequency scaling of the input clock signal as follows:  The n divider divides the input clock by integer factors from 1 to 32.  The m divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64.  The two dividers together can implement any combination of multiplication and division resulting in a clock frequency between 24 and 180 MHz exiting the PLL core. This clock has a fixed 50% duty cycle.  The output frequency of the PLL core is given by the formula EQ 1-1 (f REF is the reference clock frequency): fOUT = fREF * m/n EQ 1-1  The third and fourth dividers (u and v) permit the signals applied to the global network to each be further divided by integer factors ranging from 1 to 4. The implementations shown in EQ2 and EQ3 enable the user to define a wide range of frequency multiplier and divisors. f GLB = m/(n*u) EQ 1-2 fGLA = m/(n*v) EQ 1-3 Jitter in picoseconds at 100 MHz = 0.01 * (1/100E6) = 100 ps  Maximum Acquisition Time = 80 µs for fVCO > 40 MHz = 30 µs for fVCO < 40 MHz 1. This mode is available through the delay feature of the Global MUX driver.

ProASICPLUS Flash Family FPGAs 1-14 v5.7 enable the user to define a wide range of frequency multipliers and divisors. The clock conditioning circuit can advance or delay the clock up to 8 ns (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock phases of 0° and 180°. Prior to the application of si gnals to the rib drivers, they pass through programmable delay units, one per global network. These units permit the delaying of global signals relative to other signals to assist in the control of input set-up times. Not all possible combinations of input and output modes can be used. The degrees of freedom available in the bidirectional global pad system and in the clock conditioning circui t have been restricted. This avoids unnecessary and unwieldy design kit and software work. Notes: 1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments. 2. DLYA and DLYB are programmable delay lines, each wi th selectable values 0 ps, 250 ps, 500 ps, and 4 ns. 3. OBDIV will also divide the phase-shift since it takes place after the PLL Core. Figure 1-14  PLL Block – Top-Level View and Detailed PLL Block Diagram AVDD AGND GND VDD External Feedback Signal GLA GLB Dynamic Configuration Bits Flash Configuration Bits Clock Conditioning Circuitry (Top level view) Global MUX A OUT Global MUX B OUT See Figure 1-15 on page 1-14 Input Pins to the PLL GLB GLA PLL Core 180˚ Delay Line 0.0 ns, 0.25 ns, 0.50 ns and 4.00 ns Clock from Core (GLINT mode) CLK Deskew Delay 2.95 ns Delay Line 0.25 ns to 4.00 ns, 16 steps, 0.25 ns increments 2 Delay Line 0.0 ns, 0.25 ns, 0.50 ns and 4.00 ns Clock from Core (GLINT mode) CLKA EXTFB XDLYSEL Bypass Secondary Bypass Primary FIVDIV[4:0] FBDIV[5:0] FBSEL[1:0] OAMUX[1:0] DLYA[1:0] DLYB[1:0] OBDIV[1:0] OBMUX[2:0] OADIV[1:0] FBDLY[3:0] Clock Conditioning Circuitry Detailed Block Diagram

ProASICPLUS Flash Family FPGAs v5.7 1-15 Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time. Figure 1-15  Input Connectors to ProASICPLUS Clock Conditioning Circuitry Table 1-7  Clock-Conditioning Circuitry MUX Settings MUX Datapath Comments FBSEL

1 Internal Feedback

2 Internal Feedback and Advance Clock Using FBDLY –0.25 to –4 ns in 0.25 ns increments

3 External Feedback (EXTFB)

0 Feedback Unchanged

1 Deskew feedback by advancing clock by system delay Fixed delay of -2.95 ns OBMUX GLB

0 Primary bypass, no divider

1 Primary bypass, use divider

2 Delay Clock Using FBDLY +0.25 to +4 ns in 0.25 ns increments

4 Phase Shift Clock by 0°

5 Reserved

6 Phase Shift Clock by +180°

7 Reserved

0 Secondary bypass, no divider

1 Secondary bypass, use divider

2 Delay Clock Using FBDLY +0.25 to +4 ns in 0.25 ns increments

3 Phase Shift Clock by 0°

Std. Pad Cell Std. Pad Cell Std. Pad Cell GL NPECL PPECL CORE Package Pins Physical I/O Buffers Global MUX External Feedback Global MUX B OUT Global MUX A OUT Legend Physical Pin DATA Signals to the Core DATA Signals to the PLL Block DATA Signals to the Global MUX Control Signals to the Global MUX

ProASICPLUS Flash Family FPGAs v5.7 1-17 Figure 1-16  Using the PLL 33 MHz In, 133 MHz Out Figure 1-17  Using the PLL 40 MHz In, 50 MHz Out D D D D PLL Core External Feedback Global MUX B OUT Global MUX A OUT GLB GLA 180˚

33 MHz

133 MHz

D D D D PLL Core External Feedback Global MUX B OUT Global MUX A OUT GLB GLA 180˚

40 MHz

50 MHz

ProASICPLUS Flash Family FPGAs 1-18 v5.7 Figure 1-18  Using the PLL to Delay the Input Clock Figure 1-19  Using the PLL to Advance the Input Clock D D D D PLL Core External Feedback Global MUX B OUT Global MUX A OUT GLB GLA 180˚133 MHz

133 MHz÷1

D D D D PLL Core External Feedback Global MUX B OUT Global MUX A OUT GLB GLA 180˚

ProASICPLUS Flash Family FPGAs v5.7 1-19 Figure 1-20  Using the PLL for Clock Deskewing D D D D PLL Core External Feedback Global MUX B OUT Global MUX A OUT GL B GL A D Q Q SET CLR Off chip On chip Reference clock 180˚

ProASICPLUS Flash Family FPGAs 1-20 v5.7 Logic Tile Timing Characteristics Timing characteristics for ProASIC PLUS devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are co mmon to all ProASIC PLUS family members. Internal routing de lays are device dependent. Design dependency means that actual delays are not determined until after plac ement and routing of the user’s design are complete. Delay values may then be determined by using the Timer utility or by performing simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays are expres sed only for typical nets, which are used for initial design performance evaluation. Critical net delays can th en be applied to the most timing-critical paths. Critical nets are determined by net property assignment prior to place-and-route. Refer to the Actel Designer User’s Guide or online help for details on using constraints. Timing Derating Since ProASIC PLUS devices are manufactured with a CMOS process, device performance will vary with temperature, voltage, and process. Minimum timing parameters reflect maximum operating voltage, minimum operating temperat ure, and optimal process variations. Maximum timing parameters reflect minimum operating voltage, maximu m operating temperature, and worst-case process variations (within process specifications). The derating factors shown in Table 1-9 should be applied to all timing data contained within this datasheet. All timing numbers listed in this datasheet represent sample timing characteristics of ProASIC PLUS devices. Actual timing delay values are design-specific and can be derived from the Timer tool in Actel’s Designer software after place-and-route. Table 1-9  Temperature and Voltage Derating Factors (Normalized to Worst-Case Commercial, TJ = 70°C, VDD = 2.3 V) –55°C –40°C 0°C 25°C 70°C 85°C 110°C 125°C 135°C 150°C Notes: 1. The user can set the junction temperature in Designer softwar e to be any integer value in the range of –55°C to 175°C. 2. The user can set the core voltage in Designer software to be any value between 1.4 V and 1.6 V.

ProASICPLUS Flash Family FPGAs v5.7 1-21 Parameter Value Notes Frequency Ranges Reference Frequency fIN (min.) 1.5 MHz Clock conditioning circuitry (min.) lowest input frequency Reference Frequency fIN (max.) 180 MHz Clock c onditioning circuitry (max.) highest input frequency OSC Frequency fVCO (min.) 24 MHz Lowest output frequency voltage controlled oscillator OSC Frequency fVCO (max.) 180 MHz Highest output frequency voltage controlled osc illator Clock Conditioning Circuitry fOUT (min.) 6 MHz Lowest output frequency clock conditioning circuitry Clock Conditioning Circuitry fOUT (max.) 180 MHz Highest output frequency clock conditioning circuitry Long Term Jitter Peak-to-Peak Max.* Temperature Frequency MHz fVCO<10 10<f VCO<60 f VCO>60 25°C (or higher) ±1% ±2% ±1% Jitter(ps) = Jitter(%)*period For example: Jitter in picoseconds at 100 MHz Acquisition Time from Cold Start Acquisition Time (max.) 30 μsf VCO ≤ 40 MHz Acquisition Time (max.) 80 μsf VCO > 40 MHz Power Consumption Analog Supply Power (max.*) 6.9 mW per PLL Digital Supply Current (max.) 7 μW/MHz Duty Cycle 50% ±0.5% Input Jitter Tolerance 5% input period (max. 5 ns) Maximum jitter allowable on an input clock to acquire and maintain lock. Note: *High clock frequencies (>60 MHz) under typical setup conditions

ProASICPLUS Flash Family FPGAs 1-22 v5.7 User Security ProASICPLUS devices have FlashLock protection bits that, once programmed, block the entire programmed contents from being read externally. Please refer to Table 1-10 for details on the number of bits in the key for each device. If locked, the user can only reprogram the device employing the user-d efined security key. This protects the device from being read back and duplicated. Since programmed data is stored in nonvolatile memory cells (actually very small capa citors) rather than in the wiring, physical deconstruction cannot be used to compromise data. This type of security breach is further discouraged by the placement of the memory cells beneath the four metal layers (whose removal cannot be accomplished without disturbing the charge in the capacitor). This is the highest security provided in the industry. For more information, refer to Actel’s Design Security in Nonvolatile Flash and Antifuse FPGAs white paper. Embedded Memory Floorplan The embedded memory is lo cated across the top and bottom of the device in 256x9 blocks (Figure 1-1 on page 1-2). Depending on the device, up to 88 blocks are available to support a variety of memory configurations. Each block can be programmed as an independent memory array or combined (using dedicated memory routing resources) to form larger, more complex memory configurations. A single me mory configuration could include blocks from both the top and bottom memory locations. Embedded Memory Configurations The embedded memory in the ProASIC PLUS family provides great configuration flexibility (Table 1-11). Each ProASICPLUS block is designed and optimized as a two- port memory (one read, on e write). This provides 198 kbits of two-port and/or single port memory in the APA1000 device. Each memory block can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports ( Table 1-12). Additional characteristics include programmable flags as well as parity checking and generation. Figure 1-21 on page 1-24 and Figure 1-22 on page 1-25 show the block diagrams of the basic SRAM and FIFO blocks. Table 1-13 on page 1-24 and Table 1-14 on page 1-25 describe memory block SRAM and FIFO interface signals, respectively. A single memory block is designed to operate at up to 150 MHz (s tandard speed grade typical conditions). Each block is comprised of 256 9-bit words (one read port, one write po rt). The memory blocks may be cascaded in width and/or depth to create the desired memory organization. ( Figure 1-23 on page 1-26 ). This provides optimal bit widths of 9 (one block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1,024. Refer to Actel’s SmartGen User’s Guide for more information. Figure 1-24 on page 1-26 gives an example of optimal memory usage. Ten blocks with 23,040 bits have been used to generate three arra ys of various widths and depths. Figure 1-25 on page 1-26 shows how RAM blocks can be used in parallel to create extra read ports. In this example, using only 10 of the 88 available blocks of the APA1000 yields an effective 6,912 bits of multiple port RAM. The Actel SmartGen so ftware facilitates building wider and deeper memory configurations for optimal memory usage. Table 1-10  Flashlock Key Size by Device Device Key Size APA075 79 bits APA150 79 bits APA300 79 bits APA450 119 bits APA600 167 bits APA750 191 bits APA1000 263 bits Table 1-11  ProASICPLUS Memory Configurations by Device Device Bottom Top Maximum Width Maximum Depth DWDW APA075 0 12 256 108 1,536 9 APA150 0 16 256 144 2,048 9 APA300 16 16 256 144 2,048 9 APA450 24 24 256 216 3,072 9 APA600 28 28 256 252 3,584 9 APA750 32 32 256 288 4,096 9 APA1000 44 44 256 396 5,632 9

ProASICPLUS Flash Family FPGAs v5.7 1-23 Table 1-12  Basic Memory Configurations Type Write Access Read Access Parity Library Cell Name RAM Asynchronous Asynchronous Checked RAM256x9AA RAM Asynchronous Asynchronous Generated RAM256x9AAP RAM Asynchronous Synchronous Transparent Checked RAM256x9AST RAM Asynchronous Synchronous Transparent Generated RAM256x9ASTP RAM Asynchronous Synchronous Pipelined Checked RAM256x9ASR RAM Asynchronous Synchronous Pipelined Generated RAM256x9ASRP RAM Synchronous Asynchronous Checked RAM256x9SA RAM Synchronous Asynchronous Generated RAM256xSAP RAM Synchronous Synchronous Transparent Checked RAM256x9SST RAM Synchronous Synchronous Transparent Generated RAM256x9SSTP RAM Synchronous Synchronous Pipelined Checked RAM256x9SSR RAM Synchronous Synchronous Pipelined Generated RAM256x9SSRP FIFO Asynchronous Asynchronous Checked FIFO256x9AA FIFO Asynchronous Asynchronous Generated FIFO256x9AAP FIFO Asynchronous Synchronous Transparent Checked FIFO256x9AST FIFO Asynchronous Synchronous Transparent Generated FIFO256x9ASTP FIFO Asynchronous Synchronous Pipelined Checked FIFO256x9ASR FIFO Asynchronous Synchronous Pipelined Generated FIFO256x9ASRP FIFO Synchronous Asynchronous Checked FIFO256x9SA FIFO Synchronous Asynchronous Generated FIFO256x9SAP FIFO Synchronous Synchronous Transparent Checked FIFO256x9SST FIFO Synchronous Synchronous Transparent Generated FIFO256x9SSTP FIFO Synchronous Synchronous Pipelined Checked FIFO256x9SSR FIFO Synchronous Synchronous Pipelined Generated FIFO256x9SSRP

ProASICPLUS Flash Family FPGAs 1-24 v5.7 Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when RAM blocks are cascaded and are automatically inserted by the software tools. Figure 1-21  Example SRAM Block Diagrams Table 1-13  Memory Block SRAM Interface Signals SRAM Signal Bits In/Out Description WCLKS 1 In Write clock used on synchronization on write side RCLKS 1 In Read clock used on synchronization on read side RADDR<0:7> 8 In Read address RBLKB 1 In Read block select (active Low) RDB 1 In Read pulse (active Low) WADDR<0:7> 8 In Write address WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> can be used for parity In WRB 1 In Write pulse (active Low) DO<0:8> 9 Out Output data bits <0:8>, <8> can be used for parity Out RPE 1 Out Read parity error (active High) WPE 1 Out Write parity error (active High) PARODD 1 In Selects Odd parity generation/d etect when High, Even parity when Low Note: Not all signals shown are used in all modes. SRAM (256x9) DI <0:8> DO <0:8> RADDR <0:7>WADDR <0:7> WRB RDB WBLKB RBLKB WCLKS RCLKS RPE PARODD DI <0:8> WADDR <0:7> WRB WBLKB PARODD WPE WPE SRAM (256x9) DI <0:8> DO <0:8> WADDR <0:7> WRB RDB WBLKB RBLKB WCLKS RPE PARODD WPE RADDR <0:7> PARODD DI <0:8> DO <0:8> RADDR <0:7>WADDR <0:7> WRB RDB WBLKB RBLKB RCLKS RPEWPE DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE Sync Write and Sync Read Ports Async Write and Async Read Ports Sync Write and Async Read Ports Async Write and Sync Read Ports SRAM (256x9) SRAM (256x9)

ProASICPLUS Flash Family FPGAs v5.7 1-25 Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when RAM blocks are cascaded and are automatically inserted by the software tools. Figure 1-22  Basic FIFO Block Diagrams Table 1-14  Memory Block FIFO Interface Signals FIFO Signal Bits In/Out Description WCLKS 1 In Write clock used for synchronization on write side RCLKS 1 In Read clock used for synchronization on read side LEVEL <0:7> 8 In Direct configuratio n implements static flag logic RBLKB 1 In Read block select (active Low) RDB 1 In Read pulse (active Low) RESET 1 In Reset for FIFO pointers (active Low) WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> will be generated parity if PARGEN is true WRB 1 In Write pulse (active Low) FULL, EMPTY 2 Out FIFO flags. FULL prev ents write and EMPTY prevents read EQTH, GEQTH 2 Out EQTH is true when the FIFO holds th e number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more DO<0:8> 9 Out Output data bits <0:8>. <8> will be parity output if PARGEN is true. RPE 1 Out Read parity error (active High) WPE 1 Out Write parity error (active High) LGDEP <0:2> 3 In Configures DEPTH of the FIFO to 2 (LGDEP+1) PARODD 1 In Parity generation/detect – Even when Low, Odd when High FIFO (256x9) LEVEL<0:7> DO <0:8> DI<0:8> WRB RDB WBLKB RBLKB RPE PARODD WPE LGDEP<0:2> FULL EMPTY EQTH GEQTH WCLKS RCLKS RESET RESET RPE WPE FULL EMPTY EQTH GEQTH DO <0:8> RPE WPE FULL EMPTY EQTH GEQTH DI <0:8> DO <0:8> LEVEL <0:7> WRB RDB WBLKB RBLKB RPE PARODD WPE LGDEP<0:2> DI <0:8> LEVEL <0:7> WRB RDB WBLKB RBLKB PARODD LGDEP<0:2> FULL EMPTY EQTH GEQTH RCLKS RESET RESET LEVEL<0:7> DI<0:8> WRB RDB WBLKB RBLKB PARODD LGDEP<0:2> WCLKS DO <0:8> FIFO (256x9) FIFO (256x9) FIFO (256x9) Sync Write and Sync Read Ports Sync Write and Async Read Ports Async Write and Sync Read Ports Async Write and Async Read Ports

ProASICPLUS Flash Family FPGAs v5.7 1-27 Design Environment The ProASIC PLUS family of FPGAs is fully supported by both Actel's Libero ® Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a sing le environment (see Actel’s website for more information about Libero IDE). Libero IDE includes Synplify ® AE from Synplicity®, ViewDraw ® AE from Mentor Graphics ®, Model Sim® HDL Simulator from Mentor Graphics, WaveFormer Lite™ AE from SynaptiCAD®, PALACE™ AE Physical Synthesis from Magma, and Designer software from Actel. PALACE is an effective tool when designing with ProASICPLUS. PALACE AE Physical Synthesis from Magma takes an EDIF netlist and optimizes the performance of ProASICPLUS devices through a physical placement-driven process, ensuring that timing closure is easily achieved. Actel's Designer software is a place-and-route tool that provides a comprehensive suite of back-end support tools for FPGA development. The Designer software includes the following:  Timer – a world-class integrated static timing analyzer and constraints editor that support timing-driven place-and-route  NetlistViewer – a design netlist schematic viewer  ChipPlanner – a graphical floorplanner viewer and editor  SmartPower – allows the designer to quickly estimate the power consumption of a design  PinEditor – a graphical application for editing pin assignments and I/O attributes  I/O Attribute Editor – di splays all assigned and unassigned I/O macros and their attributes in a spreadsheet format With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, Actel’s back-annotation flow is compatible with all the major simulators. Another tool included in the Designer software is the SmartGen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Ment or Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. ISP The user can generate *.bit or *.stp programming files from the Designer software and can use these files to program a device. ProASICPLUS devices can be progr ammed in-system. For more information on ISP of ProASIC PLUS devices, refer to the In-System Programming ProASIC PLUS Devices and Performing Internal In-System Programming Using Actel’s ProASIC PLUS Devices application notes. Prior to being programmed for the first time, the ProASICPLUS device I/Os are in a tristate condition with the pull-up resistor option enabled.

ProASICPLUS Flash Family FPGAs 1-28 v5.7 Related Documents Application Notes Efficient Use of ProASIC Clock Trees http://www.actel.com/documents/A500K_Clocktree_AN.pdf I/O Features in ProASICPLUS Flash FPGAs http://www.actel.com/documents/APA_LVPECL_AN.pdf Power-Up Behavior of ProASICPLUS Devices http://www.actel.com/documents/APA_PowerUp_AN.pdf ProASICPLUS PLL Dynamic Reconfiguration Using JTAG http://www.actel.com/documents/APA_PLLdynamic_AN.pdf Using ProASICPLUS Clock Conditioning Circuits http://www.actel.com/documents/APA_PLL_AN.pdf In-System Programming ProASICPLUS Devices http://www.actel.com/documents/APA_External_ISP_AN.pdf Performing Internal In-System Programming Using Actel’s ProASICPLUS Devices http://www.actel.com/documents/APA_Microprocessor_AN.pdf ProASICPLUS RAM and FIFO Blocks http://www.actel.com/documents/APA_RAM_FIFO_AN.pdf White Paper Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity_WP .pdf User’s Guide Designer User’s Guide http://www.actel.com/documents/designer_UG.pdf SmartGen Cores Reference Guide http://www.actel.com/documents/gen_refguide_ug.pdf ProASIC and ProASICPLUS Macro Library Guide http://www.actel.com/documents/pa_libguide_UG.pdf Additional Information The following link contains additional information on ProASICPLUS devices. http://www.actel.com/products/proasicplus/default.aspx

ProASICPLUS Flash Family FPGAs v5.7 1-29 Package Thermal Characteristics The ProASIC PLUS family is available in several package types with a range of pin counts. Actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. Thermal resistance defines the ability of a package to conduct heat away from the silicon, through the package to the surrounding air. Junction-to-ambient thermal resistance is measur ed in degrees Celsius/Watt and is represented as Theta ja ( Θja). The lower the thermal resistance, the more efficiently a package will dissipate heat. A package’s maximum allowed power (P) is a function of maximum junction temperature (T J), maximum ambient operating temperature (T A), and junction-to-ambient thermal resistance Θja. Maximum junction temperature is the maximum allowable temperature on the active surface of the IC and is 110° C. P is defined as: EQ 1-4 Θja is a function of the rate (in linear feet per minute (lfpm)) of airflow in contact with the package. When the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. The maximum power dissipation allowed for a Military temperature device is specified as a function of Θjc. The absolute maximum junction temperature is 150°C. The calculation of the absolute maximum power dissipation allowed for a Military temperature application is illustrated in the following example for a 456-pin PBGA package: EQ 1-5 P TJ TA– Θja Table 1-15  Package Thermal Characteristics Plastic Packages Pin Count θjc θja UnitsStill Air 1.0 m/s 200 ft./min. 2.5 m/s 500 ft./min. Thin Quad Flat Pack (TQFP) 100 14.0 33.5 27.4 25.0 °C/W Thin Quad Flat Pack (TQFP) 144 11.0 33.5 28.0 25.7 °C/W Plastic Quad Flat Pack (PQFP) 1 208 8.0 26.1 22.5 20.8 °C/W PQFP with Heat spreader2 208 3.8 16.2 13.3 11.9 °C/W Plastic Ball Grid Array (PBGA) 456 3.0 15.6 12.5 11.6 °C/W Fine Pitch Ball Grid Array (FBGA) 144 3.8 26.9 22.9 21.5 °C/W Fine Pitch Ball Grid Array (FBGA) 256 3.8 26.6 22.8 21.5 °C/W Fine Pitch Ball Grid Array (FBGA) 3 484 3.2 18.0 14.7 13.6 °C/W Fine Pitch Ball Grid Array (FBGA)4 484 3.2 20.5 17.0 15.9 °C/W Fine Pitch Ball Grid Array (FBGA) 676 3.2 16.4 13.0 12.0 °C/W Fine Pitch Ball Grid Array (FBGA) 896 2.4 13.6 10.4 9.4 °C/W Fine Pitch Ball Grid Array (FBGA) 1152 1.8 12.0 8.9 7.9 °C/W Ceramic Quad Flat Pack (CQFP) 208 2.0 22.0 19.8 18.0 °C/W Ceramic Quad Flat Pack (CQFP) 352 2.0 17.9 16.1 14.7 °C/W Ceramic Column Grid Array (CCGA/LGA) 624 6.5 8.9 8.5 8.0 °C/W Notes: 1. Valid for the following devices irrespective of temperature grade: APA075, APA150, and APA300 2. Valid for the following devices irrespective of te mperature grade: APA450, APA600, APA750, and APA1000 3. Depopulated Array 4. Full array Maximum Power Allowed Max. junction temp. (°C) Max. case temp. ( °C)–

ProASICPLUS Flash Family FPGAs 1-30 v5.7 Calculating Typical Power Dissipation ProASICPLUS device power is calculated with both a static and an active component. The active component is a function of both the number of tile s utilized and the system speed. Power dissip ation can be calculat ed using the following formula: Total Power Consumption—P total Ptotal = Pdc + Pac where: Global Clock Contribution—P clock Pclock, the clock component of power dissipation, is given by the piece-wise model: for R < 15000 the model is: (P1 + (P2*R) - (P7*R2)) * Fs (lightly-loaded clock trees) for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees) where: Storage-Tile Contribution—P storage Pstorage, the storage-tile (Register) component of AC power dissipation, is given by Pstorage = P5 * ms * Fs where: Pdc = 7 mW for the APA075 8 mW for the APA150 11 mW for the APA300 12 mW for the APA450 12 mW for the APA600 13 mW for the APA750 19 mW for the APA1000 P dc includes the static components of PVDDP + PVDD + PAVDD Pac =P clock + Pstorage + Plogic + Poutputs + Pinputs + Ppll + Pmemory P1 = 100 µW/MHz is the basic power consumption of the clock tree per MHz of the clock P2 = 1.3 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of the clock P7 = 0.00003 µW/MHz is a correction factor for partially-loaded clock trees P10 = 6850 µW/MHz is the basic power consumption of the clock tree per MHz of the clock P11 = 0.4 µW/MHz is the incremental power consumption of the clock tree pe r storage tile – also per MHz of the clock R = the number of storage tiles clocked by this clock Fs = the clock frequency P5 = 1.1 μW/MHz is the average power consumption of a storage tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2. ms = the number of storage tiles (Reg ister) switching during each Fs cycle Fs = the clock frequency

ProASICPLUS Flash Family FPGAs v5.7 1-31 Logic-Tile Contribution—P logic Plogic, the logic-tile component of AC power dissipation, is given by Plogic = P3 * mc * Fs where: I/O Output Buffer Contribution—P outputs Poutputs, the I/O component of AC power dissipation, is given by Poutputs = (P4 + (Cload * VDDP 2)) * p * Fp where: I/O Input Buffer's Buffer Contribution—P inputs The input’s component of AC power dissipation is given by Pinputs = P8 * q * Fq where: PLL Contribution—P pll Ppll = P9 * Npll where: RAM Contribution—P memory Finally, Pmemory, the memory component of AC power consumption, is given by Pmemory = P6 * Nmemory * Fmemory * Ememory where: P3 = 1.4 μW/MHz is the average power consumption of a logi c tile per MHz of its ou tput toggling rate. The maximum output toggling rate is Fs/2. mc = the number of logic tiles switching during each Fs cycle Fs = the clock frequency P4 = 326 μW/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output frequency. This is the total I/O current V DDP. Cload = the output load p = the number of outputs Fp = the average output frequency P8 = 29 μW/MHz is the intrinsic power consumption of an input pad normalized per MHz of the input frequency. q = the number of inputs Fq = the average input frequency P9 = 7.5 mW. This value has been estimated at maximum PLL clock frequency. N Pll = number of PLLs used P6 = 175 μW/MHz is the average power consumption of a memory block per MHz of the clock Nmemory = the number of RAM/FIFO blocks (1 block = 256 words * 9 bits) Fmemory = the clock frequency of the memory Ememory = the average number of active blocks divided by the total number of blocks (N) of the memory.  Typical values for E memory would be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8, 9, 16, and 32 memory configuration  In addition, an application-dependent component to E memory can be considered. For example, for a 1kx8 memory configuration using only 1 cycle out of 2, Ememory = 1/4*1/2 = 1/8

ProASICPLUS Flash Family FPGAs 1-32 v5.7 The following is an APA750 exam ple using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as follows: Pclock => P clock = (P1 + (P2*R) - (P7*R2)) * Fs = 121.5 mW Pstorage => P storage = P5 * ms * Fs = 147.8 mW Plogic => P logic = 0 mW Poutputs => P outputs = (P4 + (Cload * VDDP Pinputs => P inputs = P8 * q * Fq = 0.3 mW Pmemory => P memory = 0 mW Pac => 361 mW Ptotal Pdc + Pac = 374 mW (typical) Fs = 10 MHz R = 13,440 ms = 13,440 (in a shift register 100% of storage tile s are toggling at each clock cycle and Fs = 10 MHz) mc = 0 (no logic tiles in this shift register) Cload = 40 pF VDDP = 3.3 V p= 2 4 Fp = 5 MHz q= 1 Fq = 10 MHz Nmemory = 0 (no RAM/FIFO blocks in this shift register)

ProASICPLUS Flash Family FPGAs v5.7 1-33 Operating Conditions Standard and –F parts are the same unless otherwise noted. All –F parts are only available as commercial. Performance Retention For devices operated and stored at 110°C or less, the performance retention period is 20 years after programming. For devices operated and stored at temperatures greater than 110°C, refer to Table 1-18 on page 1-34 to determine the performance retention period. Actel does not guar antee performance if the performance retention period is exceeded. Designers can determine the performance retention period from the following table. Evaluate the percentage of time spent at the highest temperature, then dete rmine the next highest temperature to which the device will be exposed. In Table 1-18 on page 1-34 , find the temperature profile that most closely matches the application. Example – the ambient temperature of a system cycles between 100°C (25% of the time) and 50°C (75% of the time). No forced ventilation cooling system is in use. An APA600-PQ208M FPGA operates in the system, dissipating 1 W. The package thermal resistance (junction-to-ambient) in still air Θja is 20°C/W, indicating that the junction temperature of the FPGA will be 120°C (25% of the time) and 70°C ( 75% of the time). The entry in Table 1-18 on page 1-34 , which most closely matches the application, is 25% at 125°C with 75% at 110°C. Performance retention in this example is at least 16.0 years. Note that exceeding the st ated retention period may result in a performance degradation in the FPGA below the worst-case performance indicated in the Actel Timer. To ensure that performance does not degrade below the worst-case values in the Actel Timer, the FPGA must be reprogrammed within the performance retention period. In addition, note that performance retention is independent of whether or not the FPGA is operating. The retention period of a device in storage at a given temperature will be the same as the retention period of a device operating at that junction temperature. Table 1-16  Absolute Maximum Ratings* Parameter Condition Minimum Maximum Units Supply Voltage Core (VDD)– 0 . 3 3 . 0 V Supply Voltage I/O Ring (VDDP)– 0 . 3 4 . 0 V DC Input Voltage –0.3 V DDP + 0.3 V PCI DC Input Voltage –1.0 V DDP + 1.0 V PCI DC Input Clamp Current (absolute) V IN < –1 or VIN = VDDP + 1 V 10 mA LVPECL Input Voltage –0.3 V DDP + 0.5 V GND 00 V Note: *Stresses beyond those listed u nder “Absolute Maximum Ratings” may cause pe rmanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 1-17  Programming, Storage, and Operating Limits Product Grade Programming Cycles (min.) Program Retention (min.) Storage Temperature Operating Min. Max. TJ Max. Junction Temperature Commercial 500 20 years –55°C 110°C 110°C Industrial 500 20 years –55°C 110°C 110°C Military 100 Refer to Table 1-18 on page 1-34 –65°C 150°C 150°C MIL-STD-883 100 Refer to Table 1-18 on page 1-34 –65°C 150°C 150°C

ProASICPLUS Flash Family FPGAs 1-34 v5.7 Table 1-18  Military Temperature Grade Product Performance Retention Minimum Time at TJ 110°C or below Minimum Time at TJ 125°C or below Minimum Time at TJ 135°C or below Minimum Time at TJ 150°C or below Minimum Performance Retention (Years) 100% 20.0 90% 10% 18.2 75% 25% 16 90% 10% 15.4 50% 50% 13.3 90% 10% 11.8 75% 25% 11.4 100% 10 90% 10% 9.1 50% 50% 8 75% 25% 8 90% 10% 7.7 75% 25% 7.3 50% 50% 6.7 75% 25% 5.7 100% 5 90% 10% 4.5 50% 50% 4.4 50% 50% 4 75% 25% 4 50% 50% 3.3 100% 2.5

ProASICPLUS Flash Family FPGAs v5.7 1-35 Table 1-19  Recommended Maximum Operating Conditions Programming and PLL Supplies Parameter Condition Commercial/Industrial/Military/MIL-STD-883 UnitsMinimum Maximum VPP During Programming 15.8 16.5 V Normal Operation1 01 6 . 5 V VPN During Programming –13.8 –13.2 V Normal Operation 2 –13.8 0.5 V IPP During Programming 25 mA IPN During Programming 10 mA AVDD V DD VDD V AGND GND GND V Notes: 1. Please refer to the "VPP Programming Supply Pin" section on page 1-74 for more information. 2. Please refer to the "VPN Programming Supply Pin" section on page 1-74 for more information. Table 1-20  Recommended Operating Conditions Parameter Symbol Limits Commercial Industrial Military/MIL-STD-883 DC Supply Voltage (3.3 V I/Os) V DDP VDD 3.3 V ± 0.3 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2.5 V ± 0.2 V Operating Ambient Temperature Range T A, TC 0°C to 70°C –40°C to 85°C –55°C (T A) to 125°C (TC) Maximum Operating Junction Temperature T J 110°C 110°C 150°C Note: For I/O long-term reliability, external pull-up resistors cannot be used to increase output voltage above VDDP.

ProASICPLUS Flash Family FPGAs 1-36 v5.7 Table 1-21  DC Electrical Specifications (VDDP = 2.5 V ±0.2V) Symbol Parameter Conditions Commercial/Industrial/ Military/MIL-STD-8831, 2 Min. Typ. Max. Units VOH Output High Voltage High Drive (OB25LPH) Low Drive (OB25LPL) IOH = –6 mA IOH = –12 mA IOH = –24 mA IOH = –3 mA IOH = –6 mA IOH = –8 mA 2.1 2.0 1.7 2.1 1.9 1.7 V VOL Output Low Voltage High Drive (OB25LPH) Low Drive (OB25LPL) IOL = 8 mA IOL = 15 mA IOL = 24 mA IOL = 4 mA IOL = 8 mA IOL = 15 mA 0.2 0.4 0.7 0.2 0.4 0.7 V VIH 6 Input High Voltage 1.7 V DDP + 0.3 V VIL 7 Input Low Voltage –0.3 0.7 V RWEAKPULLUP Weak Pull-up Resistance (OTB25LPU) VIN ≥ 1.25 V 6 56 k Ω HYST Input Hysteresis Schmitt See Table 1-4 on page 1-9 0.3 0.35 0.45 V IIN Input Current with pull up (V IN = GND) –240 – 20 µA without pull up (VIN = GND or VDD) –10 10 µA IDDQ Quiescent Supply Current (standby) Commercial VIN = GND4 or VDD Std. 5.0 15 mA –F3 5.0 25 mA IDDQ Quiescent Supply Current (standby) Industrial VIN = GND4 or VDD Std. 5.0 20 mA IDDQ Quiescent Supply Current (standby) Military/MIL-STD-883 V IN = GND4 or VDD Std. 5.0 25 mA IOZ Tristate Output Leakage Current VOH = GND or VDD Std. –10 10 µA –F3, 5 –10 100 µA Notes: 1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C. 2. All process conditions. Military: Junction Temperature: –55 to +150°C. 3. All –F parts are available only as commercial. 4. No pull-up resistor. 5. This will not exceed 2 mA total per device. 6. During transitions, the input signal may overshoot to V DDP +1.0V for a limited time of no larger than 10% of the duty cycle. 7. During transitions, the input signal may undershoot to -1.0 V for a limited time of no larger than 10% of the duty cycle.

ProASICPLUS Flash Family FPGAs v5.7 1-37 IOSH Output Short Circuit Current High High Drive (OB25LPH) Low Drive (OB25LPL) VIN = VSS VIN = VSS –120 –100 mA IOSL Output Short Circuit Current Low High Drive (OB25LPH) Low Drive (OB25LPL) VIN = VDDP VIN = VDDP 100 mA CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF Table 1-21  DC Electrical Specifications (VDDP = 2.5 V ±0.2V) (Continued) Symbol Parameter Conditions Commercial/Industrial/ Military/MIL-STD-8831, 2 Min. Typ. Max. Units Notes: 1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C. 2. All process conditions. Military: Junction Temperature: –55 to +150°C. 3. All –F parts are available only as commercial. 4. No pull-up resistor. 5. This will not exceed 2 mA total per device. 6. During transitions, the input signal may overshoot to V DDP +1.0V for a limited time of no larger than 10% of the duty cycle. 7. During transitions, the input signal may undershoot to -1.0 V for a limited time of no larger than 10% of the duty cycle.

ProASICPLUS Flash Family FPGAs 1-38 v5.7 Table 1-22  DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V) Symbol Parameter Conditions Commercial/Industrial/ Military/MIL-STD-8831, 2 UnitsMin. Typ. Max. VOH Output High Voltage

3.3 V I/O, High Drive (OB33P)

3.3 V I/O, Low Drive (OB33L)

IOH = –14 mA IOH = –24 mA IOH = –6 mA IOH = –12 mA 0.9∗VDDP 2.4 0.9∗VDDP 2.4 V VOL Output Low Voltage IOL = 15 mA IOL = 20 mA IOL = 28 mA IOL = 7 mA IOL = 10 mA IOL = 15 mA 0.1VDDP 0.4 0.7 0.1VDDP 0.4 0.7 V VIH

6 Input High Voltage

3.3 V Schmitt Trigger Inputs

3.3 V LVTTL/LVCMOS

2.5 V Mode

1.6 1.7 V DDP + 0.3 VDDP + 0.3 VDDP + 0.3 V VIL

7 Input Low Voltage

–0.3 –0.3 –0.3 0.8 0.8 0.7 V RWEAKPULLUP Weak Pull-up Resistance (IOB33U) VIN ≥ 1.5 V 7 43 k Ω RWEAKPULLUP Weak Pull-up Resistance (IOB25U) VIN ≥ 1.5 V 7 43 k Ω IIN Input Current with pull up (V IN = GND) –300 –40 µA without pull up (VIN = GND or VDD) –10 10 µA IDDQ Quiescent Supply Current (standby) Commercial VIN = GND4 or VDD S t d . 5 . 01 5m A –F3 5.0 25 mA IDDQ Quiescent Supply Current (standby) Industrial VIN = GND4 or VDD Std. 5.0 20 mA IDDQ Quiescent Supply Current (standby) Military VIN = GND4 or VDD Std. 5.0 25 mA Notes: 1. All process conditions. Commercial/Industri al: Junction Temperature: –40 to +110°C. 2. All process conditions. Military: Junc tion Temperature: –55 to +150°C. 3. All –F parts are only available as commercial. 4. No pull-up resistor required. 5. This will not exceed 2 mA total per device. 6. During transitions, the inpu t signal may overshoot to V DDP +1.0 V for a limited time of no larger than 10% of the duty cycle. 7. During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle.

ProASICPLUS Flash Family FPGAs v5.7 1-39 IOZ Tristate Output Leakage Current VOH = GND or VDD Std. –10 10 µA –F3, 5 –10 100 µA IOSH Output Short Circuit Current High

3.3 V High Drive (OB33P)

3.3 V Low Drive (OB33L)

V IN = GND VIN = GND –200 –100 IOSL Output Short Circuit Current Low

3.3 V High Drive

3.3 V Low Drive

VIN = VDD VIN = VDD 200 100 CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF Table 1-22  DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V) (Continued) Symbol Parameter Conditions Commercial/Industrial/ Military/MIL-STD-8831, 2 UnitsMin. Typ. Max. Notes: 1. All process conditions. Commercial/Industri al: Junction Temperature: –40 to +110°C. 2. All process conditions. Military: Junc tion Temperature: –55 to +150°C. 3. All –F parts are only available as commercial. 4. No pull-up resistor required. 5. This will not exceed 2 mA total per device. 6. During transitions, the inpu t signal may overshoot to V DDP +1.0 V for a limited time of no larger than 10% of the duty cycle. 7. During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle.

ProASICPLUS Flash Family FPGAs 1-40 v5.7 Table 1-23  DC Specifications (3.3 V PCI Operation)1 Symbol Parameter Condition Commercial/ Industrial2,3 Military/MIL-STD- 8832,3 UnitsMin. Max. Min. Max. VDD Supply Voltage for Core 2.3 2.7 2.3 2.7 V VDDP Supply Voltage for I/O Ring 3.0 3.6 3.0 3.6 V VIH Input High Voltage 0.5V DDP VDDP + 0.5 0.5V DDP VDDP + 0.5 V VIL Input Low Voltage –0.5 0.3V DDP –0.5 0.3V DDP V IIPU Input Pull-up Voltage4 0.7VDDP 0.7VDDP V IIL Input Leakage Current5 0 < VIN < VDDP Std. –10 10 –50 50 μA –F3, 6 –10 100 μA VOH Output High Voltage I OUT = –500 µA 0.9V DDP 0.9VDDP V VOL Output Low Voltage I OUT = 1500 µA 0.1V DDP 0.1VDDP V CIN Input Pin Capacitance (except CLK) 10 10 pF CCLK CLK Pin Capacitance 5 12 5 12 pF Notes: 1. For PCI operation, use GL33, OTB33PH, OB33PH, IOB 33PH, IB33, or IB33S macro library cell only. 2. All process conditions. Junction Temperature: –40 to +110°C fo r Commercial and Industrial devices and –55 to +125°C for Military. 3. All –F parts are available as commercial only. 4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistor s are calculated to pull a flo ated network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum current at this input voltage. 5. Input leakage currents include hi-Z output leakage fo r all bidirectional buffers with tristate outputs. 6. The sum of the leakage currents for all inputs shall not exceed 2mA per device.

ProASICPLUS Flash Family FPGAs v5.7 1-41 Table 1-24  AC Specifications (3.3 V PCI Revision 2.2 Operation) Symbol Parameter Condition Commercial/Industrial/Military/MIL-STD- 883 UnitsMin. Max. IOH(AC) Switching Current High 0 < V OUT ≤ 0.3VDDP * –12VDDP mA 0.3VDDP ≤ VOUT < 0.9VDDP * (–17.1 + (VDDP – VOUT)) mA 0.7VDDP < VOUT < VDDP * See equation C – page 124 of the PCI Specification document rev. 2.2 (Test Point) V OUT = 0.7VDDP * –32VDDP mA IOL(AC) Switching Current Low V DDP > VOUT ≥ 0.6VDDP * 16VDDP mA 0.6VDDP > VOUT > 0.1VDDP 1 (26.7VOUT)m A 0.18VDDP > VOUT > 0* See equation D – page 124 of the PCI Specification document rev. 2.2 (Test Point) V OUT = 0.18VDDP 38VDDP mA ICL Low Clamp Current –3 < V IN ≤ –1 –25 + (V IN + 1)/0.015 mA ICH High Clamp Current V DDP + 4 > VIN ≥ VDDP + 1 25 + (VIN – VDDP – 1)/0.015 mA slewR Output Rise Slew Rate 0.2V DDP to 0.6VDDP load* 14 V / n s slewF Output Fall Slew Rate 0.6V DDP to 0.2VDDP load* 14 V / n s Note: * Refer to the PCI Specification document rev. 2.2. pin output buffer 1/2 in. max 10 pF 1kΩ pin output buffer 10 pF 1kΩ Pad Loading Applicable to the Rising Edge PCI Pad Loading Applicable to the Falling Edge PCI

ProASICPLUS Flash Family FPGAs 1-42 v5.7 Tristate Buffer Delays Figure 1-26  Tristate Buffer Delays Table 1-25  Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 70°C Macro Type Description Max tDLH Max tDHL Max tENZH Max tENZL UnitsStd. –F Std. –F Std. –F Std. –F Notes: 1. t DLH=Data-to-Pad High 2. t DHL=Data-to-Pad Low 3. t ENZH=Enable-to-Pad, Z to High 4. t ENZL = Enable-to-Pad, Z to Low 5. All –F parts are only available as commercial. Table 1-26  Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 70°C Macro Type Description Max tDLH Max tDHL Max tENZH Max tENZL UnitsStd. –F Std. –F Std. –F Std. –F Notes: 1. t DLH=Data-to-Pad High 2. t DHL=Data-to-Pad Low 3. t ENZH=Enable-to-Pad, Z to High 4. t ENZL = Enable-to-Pad, Z to Low 6. All –F parts are only available as commercial. PADA OTBx A 50% PAD VOL VOH 50% tDLH 50% 50% tDHL EN 50% PAD VOL 50% tENZL 50% 10% EN 50% PAD GND VOH 50% tENZH 50% 90% VDDP 35pF EN

ProASICPLUS Flash Family FPGAs v5.7 1-43 Table 1-27  Worst-Case Military Conditions VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 125°C for Military/MIL-STD-883 Macro Type Description Max tDLH Max tDHL Max tENZH Max tENZL UnitsStd. Std. Std. Std. Notes: 1. t DLH=Data-to-Pad High 2. t DHL=Data-to-Pad Low 3. t ENZH=Enable-to-Pad, Z to High 4. t ENZL = Enable-to-Pad, Z to Low Table 1-28  Worst-Case Military Conditions VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 125°C for Military/MIL-STD-883 Macro Type Description Max tDLH Max tDHL Max tENZH Max tENZL UnitsStd. Std. Std. Std. OTB25LPHN 2.5 V, Low Power, High Output Current, Nominal Slew Rate5 2.7 3.2 2.8 2.1 ns Notes: 1. t DLH=Data-to-Pad High 2. t DHL=Data-to-Pad Low 3. t ENZH=Enable-to-Pad, Z to High 4. t ENZL = Enable-to-Pad, Z to Low

ProASICPLUS Flash Family FPGAs 1-44 v5.7 Output Buffer Delays Figure 1-27  Output Buffer Delays Table 1-29  Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 70°C Macro Type Description Max tDLH

1 Max tDHL

UnitsStd. –F Std. –F Notes: 1. t DLH = Data-to-Pad High 2. t DHL = Data-to-Pad Low 3. All –F parts are only available as commercial. Table 1-30  Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 70°C Macro Type Description Max tDLH UnitsStd. –F Std. –F Notes: 1. t DLH = Data-to-Pad High 2. t DHL = Data-to-Pad Low 4. All –F parts are only available as commercial. PAD A 50% PAD VOL VOH 50% tDLH 50% 50% tDHL 35pF A OBx

ProASICPLUS Flash Family FPGAs v5.7 1-45 Table 1-31  Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 125°C for Military/MIL-STD-883 Macro Type Description Max. tDLH Max. tDHL UnitsStd. Std. OB33PH 3.3V , PCI Output Current, High Slew Rate 2.1 2.3 ns OB33PN 3.3V, High Output Current, Nominal Slew Rate 2.5 3.2 ns OB33PL 3.3V, High Output Current, Low Slew Rate 2.7 3.5 ns OB33LH 3.3V, Low Output Current, High Slew Rate 2.7 4.3 ns OB33LN 3.3V , Low Output Current, Nominal Slew Rate 3.3 4.7 ns OB33LL 3.3V , Low Output Current, Low Slew Rate 3.3 6.1 ns Notes: 1. t DLH = Data-to-Pad High 2. t DHL = Data-to-Pad Low Table 1-32  Worst-Case Military Conditions VDDP = 2.3 V, VDD = 2.3V, 35 pF load, TJ = 125°C for Military/MIL-STD-883 Macro Type Description Max. tDLH Max. tDHL UnitsStd. Std. OB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate 3 2.3 2.4 ns OB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate 3 2.7 3.3 ns OB25LPHL 2.5V , Low Power, High Output Current, Low Slew Rate3 3.2 3.5 ns OB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate 3 3.0 5.0 ns OB25LPLN 2.5V , Low Power, Low Output Current, Nominal Slew Rate 3 3.9 4.6 ns OB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate 3 4.3 5.7 ns Notes: 1. t DLH = Data-to-Pad High 2. t DHL = Data-to-Pad Low

ProASICPLUS Flash Family FPGAs 1-46 v5.7 Input Buffer Delays Figure 1-28  Input Buffer Delays Table 1-33  Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C Macro Type Description Max. tINYH Max. tINYL UnitsStd. –F Std. –F Notes: 1. t INYH = Input Pad-to-Y High 2. t INYL = Input Pad-to-Y Low 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, V DDP=2.3 V for delays. 5. All –F parts are only available as commercial. Table 1-34  Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, TJ = 70°C Macro Type Description Max. tINYH Max. tINYL UnitsStd. –F Std. –F Notes: 1. t INYH = Input Pad-to-Y High 2. t INYL = Input Pad-to-Y Low 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, V DDP=2.3 V for delays. 5. All –F parts are only available as commercial. PAD Y PAD VDDP

0 V50%

Y GND VDD 50% tINYH 50% 50% INYL IBx t

ProASICPLUS Flash Family FPGAs v5.7 1-47 Table 1-35  Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883 Macro Type Description Max. tINYH Max. tINYL UnitsStd. Std. IB33 3.3V , CMOS Input Levels 3, No Pull-up Resistor 0.5 0.6 ns IB33S 3.3V, CMOS Input Levels 3, No Pull-up Resistor, Schmitt Trigger 0.6 0.8 ns Notes: 1. t INYH = Input Pad-to-Y High 2. t INYL = Input Pad-to-Y Low 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, V DDP=2.3V for delays. Table 1-36  Worst-Case Military Conditions VDDP = 2.3V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883 Macro Type Description Max. tINYH Max. tINYL UnitsStd. Std. IB25LP 2.5V , CMOS Input Levels 3, Low Power 0.9 0.7 ns IB25LPS 2.5V, CMOS Input Levels 3, Low Power, Schmitt Trigger 0.8 1.0 ns Notes: 1. t INYH = Input Pad-to-Y High 2. t INYL = Input Pad-to-Y Low 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, V DDP=2.3V for delays.

ProASICPLUS Flash Family FPGAs 1-48 v5.7 Global Input Buffer Delays Table 1-37  Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C Macro Type Description Max. tINYH Max. tINYL

2 Units

Std.3 –F Std. 3 –F PECL PPECL Input Levels 1.0 1.2 1.1 1.3 ns Notes: 1. t INYH = Input Pad-to-Y High 2. t INYL = Input Pad-to-Y Low 3. Applies to Military ProASIC PLUS devices. 4. LVTTL delays are the same as CMOS delays. 5. For LP Macros, V DDP=2.3 V for delays. 6. All –F parts are only available as commercial. Table 1-38  Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, TJ = 70°C Macro Type Description Max. tINYH Max. tINYL Std.3 –F Std. 3 –F Notes: 1. t INYH = Input Pad-to-Y High 2. t INYL = Input Pad-to-Y Low 3. Applies to Military ProASIC PLUS devices. 4. LVTTL delays are the same as CMOS delays. 5. For LP Macros, V DDP=2.3 V for delays. 6. All –F parts are only available as commercial.

ProASICPLUS Flash Family FPGAs v5.7 1-49 Table 1-39  Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883 Macro Type Description Max. tINYH Max. tINYL Std. Std. GL33 3.3V , CMOS Input Levels 3, No Pull-up Resistor 1.1 1.1 GL33S 3.3V, CMOS Input Levels 3, No Pull-up Resistor, Schmitt Trigger 1.1 1.1 PECL PPECL Input Levels 1.1 1.1 Notes: 1. t INYH = Input Pad-to-Y High 2. t INYL = Input Pad-to-Y Low 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, V DDP=2.3V for delays. Table 1-40  Worst-Case Military Conditions VDDP = 2.3V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883 Macro Type Description Max. tINYH Max. tINYL Std. Std. GL25LP 2.5V , CMOS Input Levels 3, Low Power 1.0 1.1 GL25LPS 2.5V, CMOS Input Levels 3, Low Power, Schmitt Trigger 1.4 1.0 Notes: 1. t INYH = Input Pad-to-Y High 2. t INYL = Input Pad-to-Y Low 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, V DDP=2.3V for delays.

ProASICPLUS Flash Family FPGAs 1-50 v5.7 Predicted Global Routing Delay Global Routing Skew Table 1-41  Worst-Case Commercial Conditions1 VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C Parameter Description Max. UnitsStd. –F 2 tRCKH Input Low to High3 1.1 1.3 ns tRCKL Input High to Low3 1.0 1.2 ns tRCKH Input Low to High4 0.8 1.0 ns tRCKL Input High to Low4 0.8 1.0 ns Notes: 1. The timing delay difference between tile locations is less than 15ps. 2. All –F parts are only available as commercial. 3. Highly loaded row 50%. 4. Minimally loaded row. Table 1-42  Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883 Parameter Description Max. Units tRCKH Input Low to High (high loaded row of 50%) 1.1 ns tRCKL Input High to Low (high loaded row of 50%) 1.0 ns tRCKH Input Low to High (minimally loaded row) 0.8 ns tRCKL Input High to Low (minimally loaded row) 0.8 ns Note: * The timing delay difference between tile locations is less than 15 ps. Table 1-43  Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C Parameter Description Max. UnitsStd. –F* tRCKSWH Maximum Skew Low to High 270 320 ps tRCKSHH Maximum Skew High to Low 270 320 ps Note: *All –F parts are only available as commercial. Table 1-44  Worst-Case Commercial Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883 Parameter Description Max. Units tRCKSWH Maximum Skew Low to High 270 ps tRCKSHH Maximum Skew High to Low 270 ps

ProASICPLUS Flash Family FPGAs v5.7 1-51 Module Delays Sample Macrocell Library Listing Figure 1-29  Module Delays Table 1-45  Worst-Case Military Conditions1 VDD = 2.3 V, TJ = 70º C, TJ = 70°C, TJ = 125°C for Military/MIL-STD-883 Cell Name Description Std. –F 2 Max Min Max Min Units NAND2 2-Input NAND 0.5 0.6 ns AND2 2-Input AND 0.7 0.8 ns NOR3 3-Input NOR 0.8 1.0 ns MUX2L 2-1 MUX with Active Low Select 0.5 0.6 ns OA21 2-Input OR into a 2-Input AND 0.8 1.0 ns XOR2 2-Input Exclusive OR 0.6 0.8 ns LDL Active Low Latch (LH/HL) LH 3 0.9 1.1 ns CLK-Q HL 3 0.8 0.9 ns tsetup 0.7 0.8 ns thold 0.1 0.2 ns DFFL Negative Edge-Triggered D-type Flip-Flop (LH/HL) CLK-Q LH3 0.9 1.1 ns HL3 0.8 1.0 ns tsetup 0.6 0.7 ns thold 0.0 0.0 ns Notes: 1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of local interconnect. 2. All –F parts are only available as commercial. 3. LH and HL refer to the Q transitions from Low to High and High to Low, respectively. A B 50% Y 50% 50%50% 50% 50% DALH C 50%50% 50%50%50% DBLH DAHL DBHL DCHLDCLH 50% t t t t tt A B C Y

ProASICPLUS Flash Family FPGAs 1-52 v5.7 Table 1-46  Recommended Operating Conditions Parameter Symbol Limits Commercial/Industrial Military/MIL-STD-883 Maximum Clock Frequency* f CLOCK 180 MHz 180 MHz Maximum RAM Frequency* f RAM 150 MHz 150 MHz Maximum Rise/Fall Time on Inputs*  Schmitt Trigger Mode (10% to 90%)  Non-Schmitt Trigger Mode (10% to 90%) tR/tF tR/tF N/A 100 ns 100 ns 10 ns Maximum LVPECL Frequency* 180 MHz 180 MHz Maximum TCK Frequency (JTAG) f TCK 10 MHz 10 MHz Note: *All –F parts will be 20% slower than standard commercial devices. Table 1-47  Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25°C Type Trig. Level Rising Edge (ns) Slew Rate (V/n s) Falling Edge (ns) Slew Rate (V/ns) PCI Mode OB33PH 10%-90% 1.60 1.65 1.65 1.60 Yes OB33PN 10%-90% 1.57 1.68 3.32 0.80 No OB33PL 10%-90% 1.57 1.68 1.99 1.32 No OB33LH 10%-90% 3.80 0.70 4.84 0.55 No OB33LN 10%-90% 4.19 0.63 3.37 0.78 No OB33LL 10%-90% 5.49 0.48 2.98 0.89 No OB25LPHH 10%-90% 1.55 1.29 1.56 1.28 No OB25LPHN 10%-90% 1.70 1.18 2.08 0.96 No OB25LPHL 10%-90% 1.97 1.02 2.09 0.96 No OB25LPLH 10%-90% 3.57 0.56 3.93 0.51 No OB25LPLN 10%-90% 4.65 0.43 3.28 0.61 No OB25LPLL 10%-90% 5.52 0.36 3.44 0.58 No Notes: 1. Standard and –F parts. 2. All –F only available as commercial.

ProASICPLUS Flash Family FPGAs v5.7 1-53 Table 1-48  JTAG Switching Characteristics Description Symbol Min Max Unit Output delay from TCK falling to TDI, TMS t TCKTDI –4 4 ns TDO Setup time before TCK rising t TDOTCK 10 ns TDO Hold time after TCK rising t TCKTDO 0 ns TCK period t TCK 100 2 1,000 ns RCK period t RCK 100 1,000 ns Notes: 1. For DC electrical specificati ons of the JTAG pins (TCK, TDI, TMS, TDO, TRST), refer to Table 1-21 on page 1-36 when VDDP = 2.5 V and Table 1-22 on page 1-38 when VDDP = 3.3 V. 2. If RCK is being used, there is no minimum on the TCK period. Figure 1-30  JTAG Operation Timing TCK TMS, TDI TDO tTCK tTCKTDI tTCKTDO tTDOTCK

ProASICPLUS Flash Family FPGAs 1-54 v5.7 Embedded Memory Specifications This section discusses ProASIC PLUS SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks ( Table 1-49). Table 1-12 on page 1-23 shows basic SRAM and FIFO configurations. Simultaneous read and write to the same location must be done with care. On such accesses the DI bus is output to the DO bus. Refer to the ProASIC PLUS RAM and FIFO Blocks application note for more information. Enclosed Timing Diagrams—SRAM Mode:  "Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Tr ansparent)" section on page 1-55  "Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)" section on page 1-56  "Asynchronous SRAM Write" section on page 1-57  "Asynchronous SRAM Read, Address Controlled, RDB=0" section on page 1-58  "Asynchronous SRAM Read, RDB Controlled" section on page 1-59  "Synchronous SRAM Write"  Embedded Memory Specifications The difference between sy nchronous transparent and pipeline modes is the timing of all the output signals from the memory. In transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. If clock cycles are short (h igh clock speed), the data requires most of the clock cycle to change to valid values (stable signals). Processing of this data in the same clock cycle is nearly impossible. Most designers add registers at all outputs of the memory to push the data processing into the next clock cycle. An entire clock cycle can then be used to process the data. To simplify use of this memory setup, suitable registers have been implemented as part of th e memory primitive and are available to the user in the synchronous pipeline mode. In this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access. Table 1-49  Memory Block SRAM Interface Signals SRAM Signal Bits In/Out Description WCLKS 1 In Write clock used on synchronization on write side RCLKS 1 In Read clock used on synchronization on read side RADDR<0:7> 8 In Read address RBLKB 1 In True read block select (active Low) RDB 1 In True read pulse (active Low) WADDR<0:7> 8 In Write address WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> can be used for parity In WRB 1 In Negative true write pulse DO<0:8> 9 Out Output data bits <0:8>, <8> can be used for parity Out RPE 1 Out Read parity error (active High) WPE 1 Out Write parity error (active High) PARODD 1 In Selects Odd parity generation/detect when high, Even when low Note: Not all signals shown are used in all modes.

ProASICPLUS Flash Family FPGAs v5.7 1-55 Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) Note: The plot shows the normal operation status. Figure 1-31  Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) Table 1-50  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New DO access from RCLKS ↑ 7.5 ns OCH Old DO valid from RCLKS ↑ 3.0 ns RACH RADDR hold from RCLKS ↑ 0.5 ns RACS RADDR setup to RCLKS ↑ 1.0 ns RDCH RDB hold from RCLKS ↑ 0.5 ns RDCS RDB setup to RCLKS ↑ 1.0 ns RPCA New RPE access from RCLKS ↑ 9.5 ns RPCH Old RPE valid from RCLKS ↑ 3.0 ns Note: All –F speed grade devices are 20% slower than the standard numbers. RADDR RPE DO RCLKS RBD, RBLKB New Valid Data Out Cycle Start Old Data Out New Valid Address tRACS tRDCS tRDCH tRACH tOCH tRPCH tCMH tOCA tRPCA tCCYC tCML

ProASICPLUS Flash Family FPGAs 1-56 v5.7 Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) Note: The plot shows the normal operation status. Figure 1-32  Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) Table 1-51  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = 0°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New DO access from RCLKS ↑ 2.0 ns OCH Old DO valid from RCLKS ↑ 0.75 ns RACH RADDR hold from RCLKS ↑ 0.5 ns RACS RADDR setup to RCLKS ↑ 1.0 ns RDCH RDB hold from RCLKS ↑ 0.5 ns RDCS RDB setup to RCLKS ↑ 1.0 ns RPCA New RPE access from RCLKS ↑ 4.0 ns RPCH Old RPE valid from RCLKS ↑ 1.0 ns Note: All –F speed grade devices are 20% slower than the standard numbers. RCLKS RPE DO New Valid Data Out Cycle Start New RPE Out RADDR New Valid Address RDB, RBLKB tRACS tOCA tRPCH tOCH tRPCA tCMLtCMH tCCYC tRACH tRDCH tRDCS Old Data Out Old RPE Out

ProASICPLUS Flash Family FPGAs v5.7 1-57 Asynchronous SRAM Write Note: The plot shows the normal operation status. Figure 1-33  Asynchronous SRAM Write Table 1-52  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B Symbol txxx Description Min. Max. Units Notes AWRH WADDR hold from WB ↑ 1.0 ns AWRS WADDR setup to WB ↓ 0.5 ns DWRH DI hold from WB ↑ 1.5 ns DWRS DI setup to WB ↑ 0.5 ns PARGEN is inactive. DWRS DI setup to WB ↑ 2.5 ns PARGEN is active. WPDA WPE access from DI 3.0 ns W PE is invalid, while PARGEN is active.WPDH WPE hold from DI 1.0 ns WRCYC Cycle time 7.5 ns WRMH WB high phase 3.0 ns Inactive WRML WB low phase 3.0 ns Active Note: All –F speed grade devices are 20% slower than the standard numbers. WRB, WBLKB WADDR WPE DI tAWRS tWPDA tAWRH tDWRS tWRML tWRMH tWRCYC tWPDH tDWRH

ProASICPLUS Flash Family FPGAs 1-58 v5.7 Asynchronous SRAM Read, Address Controlled, RDB=0 Note: The plot shows the normal operation status. Figure 1-34  Asynchronous SRAM Read, Address Controlled, RDB=0 Table 1-53  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B Symbol txxx Description Min. Max. Units Notes ACYC Read cycle time 7.5 ns OAA New DO access from RADDR stable 7.5 ns OAH Old DO hold from RADDR stable 3.0 ns RPAA New RPE access from RADDR stable 10.0 ns RPAH Old RPE hold from RADDR stable 3.0 ns Note: All –F speed grade devices are 20% slower than the standard numbers. RPE DO RADDR tOAH tRPAH tOAA tRPAA tACYC

ProASICPLUS Flash Family FPGAs v5.7 1-59 Asynchronous SRAM Read, RDB Controlled Note: The plot shows the normal operation status. Figure 1-35  Asynchronous SRAM Read, RDB Controlled Table 1-54  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes ORDA New DO access from RB ↓ 7.5 ns ORDH Old DO valid from RB ↓ 3.0 ns RDCYC Read cycle time 7.5 ns RDMH RB high phase 3.0 ns Inactive setup to new cycle RDML RB low phase 3.0 ns Active RPRDA New RPE access from RB ↓ 9.5 ns RPRDH Old RPE valid from RB ↓ 3.0 ns Note: All –F speed grade devices are 20% slower than the standard numbers. RB=(RDB+RBLKB) RPE DO tORDH tORDA tRPRDA tRDML tRDCYC tRDMH tRPRDH

ProASICPLUS Flash Family FPGAs 1-60 v5.7 Synchronous SRAM Write Note: The plot shows the normal operation status. Figure 1-36  Synchronous SRAM Write Table 1-55  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns DCH DI hold from WCLKS ↑ 0.5 ns DCS DI setup to WCLKS ↑ 1.0 ns WACH WADDR hold from WCLKS ↑ 0.5 ns WDCS WADDR setup to WCLKS ↑ 1.0 ns WPCA New WPE access from WCLKS ↑ 3.0 ns WPE is invalid while PARGEN is activeWPCH Old WPE valid from WCLKS ↑ 0.5 ns WRCH, WBCH WRB & WBLKB hold from WCLKS ↑ 0.5 ns WRCS, WBCS WRB & WBLKB setup to WCLKS ↑ 1.0 ns Notes: 1. On simultaneous read and write accesses to the same location, DI is output to DO. 2. All –F speed grade devices are 20% slower than the standard numbers. WCLKS WPE WADDR, DI WRB, WBLKB Cycle Start tWRCH, tWBCH tWRCS, tWBCS tDCS, tWDCS tWPCH tDCH, tWACH tWPCA tCMH tCML tCCYC

ProASICPLUS Flash Family FPGAs v5.7 1-61 Synchronous Write and Read to the Same Location Note: The plot shows the normal operation status. Figure 1-37  Synchronous Write and Read to the Same Location Table 1-56  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WCLKRCLKS WCLKS ↑ to RCLKS ↑ setup time – 0.1 ns WCLKRCLKH WCLKS ↑ to RCLKS ↑ hold time 7.0 ns OCH Old DO valid from RCLKS ↑ 3.0 ns OCA/OCH displayed for Access Timed OutputOCA New DO valid from RCLKS ↑ 7.5 ns Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS and RCLKS driven by the same design signal. 3. If WCLKS changes after the hold time, the data will be read. 4. A setup or hold time violation will result in unknown output data. 5. All –F speed grade devices are 20% slower than the standard numbers. * New data is read if WCLKS ↑ occurs before setup time. The data stored is read if WCLKS ↑ occurs after hold time. RCLKS DO WCLKS tWCLKRCLKH New Data*Last Cycle Data tWCLKRCLKS tOCH tCCYC tCMH tCML tOCA

ProASICPLUS Flash Family FPGAs 1-62 v5.7 Asynchronous Write and Synchronous Read to the Same Location Note: The plot shows the normal operation status. Figure 1-38  Asynchronous Write and Synchronous Read to the Same Location Table 1-57  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WBRCLKS WB ↓ to RCLKS ↑ setup time –0.1 ns WBRCLKH WB ↓ to RCLKS ↑ hold time 7.0 ns OCH Old DO valid from RCLKS ↑ 3.0 ns OCA/OCH displayed for Access Timed OutputOCA New DO valid from RCLKS ↑ 7.5 ns DWRRCLKS DI to RCLKS ↑ setup time 0 ns DWRH DI to WB ↑ hold time 1.5 ns Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. In asynchronous write and synchronous read access to the same lo cation, the new write data will be read out if the active wri te signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be read. 3. A setup or hold time violation will result in unknown output data. 4. All –F speed grade devices are 20% slower than the standard numbers. * New data is read if WB ↓ occurs before setup time. The stored data is read if WB ↓ occurs after hold time. WB = {WRB + WBLKB} RCLKS DO tBRCLKH New Data*Last Cycle Data tWRCKS tOCH tOCA DI tDWRRCLKS tDWRH tCCYC t CMH tCML

ProASICPLUS Flash Family FPGAs v5.7 1-63 Asynchronous Write and Read to the Same Location Note: The plot shows the normal operation status. Figure 1-39  Asynchronous Write and Read to the Same Location Table 1-58  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes ORDA New DO access from RB ↓ 7.5 ns ORDH Old DO valid from RB ↓ 3.0 ns OWRA New DO access from WB ↑ 3.0 ns OWRH Old DO valid from WB ↑ 0.5 ns RAWRS RB ↓ or RADDR from WB ↓ 5.0 ns RAWRH RB ↑ or RADDR from WB ↑ 5.0 ns Notes: 1. During an asynchronous read cycle, each write operation (synch ronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. Refer to the ProASICPLUS RAM and FIFO Blocks application note for more information. 2. Violation or RAWRS will disturb access to the OLD data. 3. Violation of RAWRH will disturb access to the NEWER data. 4. All –F speed grade devices are 20% slower than the standard numbers. RB, RADDR OLD NEWERNEW tORDA tORDH tOWRH tRAWRH WB = {WRB+WBLKB} DO tOWRAtRAWRS

ProASICPLUS Flash Family FPGAs 1-64 v5.7 Synchronous Write and Asynchronous Read to the Same Location Note: The plot shows the normal operation status. Figure 1-40  Synchronous Write and Asynchronous Read to the Same Location Table 1-59  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes ORDA New DO access from RB ↓ 7.5 ns ORDH Old DO valid from RB ↓ 3.0 ns OWRA New DO access from WCLKS ↓ 3.0 ns OWRH Old DO valid from WCLKS ↓ 0.5 ns RAWCLKS RB ↓ or RADDR from WCLKS ↑ 5.0 ns RAWCLKH RB ↑ or RADDR from WCLKS ↓ 5.0 ns Notes: 1. During an asynchronous read cycle, each write operation (synch ronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation of RAWCLKS will disturb access to OLD data. 3. Violation of RAWCLKH will disturb access to NEWER data. 4. All –F speed grade devices are 20% slower than the standard numbers. RB, RADDR OLD NEW NEWER tORDA tORDH tRAWCLKS tRAWCLKH WCLKS DO tOWRH tOWRA

ProASICPLUS Flash Family FPGAs v5.7 1-65 Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO acce pts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when th e FIFO is empty, all reads are inhibited. A problem is cr eated if the FIFO is written to during the transition fr om full to not full, or read during the transition from empty to not empty. The exact time at which the writ e or read operation changes from inhibited to accepted after the read (write) signal which causes the transition from full or empty to not full or not empty is indeterminate. For slow cycles, this indeterminate period starts 1 ns after the RB (WB) transition, which deactivates full or not empty and ends 3 ns after the RB (WB) transition. For fast cycles, the indeterminate period ends 3 ns (7.5 ns – RDL (WRL)) after the RB (WB) transition, whichever is later ( Table 1-1 on page 1-7). The timing diagram for write is shown in Figure 1-38 on page 1-62 . The timing diagram for read is shown in Figure 1-39 on page 1-63. For basic SRAM configurations, see Table 1-13 on page 1-24. When reset is asserted, the empty flag will be asserted, the counters will reset, the outputs go to zero, but the internal RAM is not erased. Enclosed Timing Diagrams – FIFO Mode: The following timing diagrams apply only to single cell; they are not applicable to cascaded cells. For more information, refer to the ProASICPLUS RAM/FIFO Blocks application note.  "Asynchronous FIFO Read" section on page 1-67  "Asynchronous FIFO Write" section on page 1-68  "Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Tr ansparent)" section on page 1-69  "Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)" section on page 1-70  "Synchronous FIFO Write" section on page 1-71  "FIFO Reset" section on page 1-72 Table 1-60  Memory Block FIFO Interface Signals FIFO Signal Bits In/Out Description WCLKS 1 In Write clock used for synchronization on write side RCLKS 1 In Read clock used for synchronization on read side LEVEL <0:7>* 8 In Direct configuratio n implements static flag logic RBLKB 1 In Read block select (active Low) RDB 1 In Read pulse (active Low) RESET 1 In Reset for FIFO pointers (active Low) WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> will be generated if PARGEN is true WRB 1 In Write pulse (active Low) FULL, EMPTY 2 Out FIFO flags. FULL prev ents write and EMPTY prevents read EQTH, GEQTH* 2 Out EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more DO<0:8> 9 Out Output data bits <0:8> RPE 1 Out Read parity error (active High) WPE 1 Out Write parity error (active High) LGDEP <0:2> 3 In Configures DEPTH of the FIFO to 2 (LGDEP+1) PARODD 1 In Selects Odd parity generation/detect when high, Even when low Note: *LEVEL is always eight bits (0000.0000, 0000.0001). That means fo r values of DEPTH greater than 256, not all values will be indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL. Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs.

ProASICPLUS Flash Family FPGAs v5.7 1-67 Asynchronous FIFO Read Note: The plot shows the normal operation status. Figure 1-43  Asynchronous FIFO Read Table 1-61  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes ERDH, FRDH, THRDH Old EMPTY, FULL, EQTH, & GETH valid hold time from RB ↑ 0.5 ns Empty/full/thresh are invalid from the end of hold until the new access is complete ERDA New EMPTY access from RB ↑ 3.01 ns FRDA FULL ↓ access from RB ↑ 3.01 ns ORDA New DO access from RB ↓ 7.5 ns ORDH Old DO valid from RB ↓ 3.0 ns RDCYC Read cycle time 7.5 ns RDWRS WB ↑, clearing EMPTY, setup to RB ↓ 3.02 ns Enabling the read operation 1.0 ns Inhibiting the read operation RDH RB high phase 3.0 ns Inactive RDL RB low phase 3.0 ns Active RPRDA New RPE access from RB ↓ 9.5 ns RPRDH Old RPE valid from RB ↓ 4.0 ns THRDA EQTH or GETH access from RB ↑ 4.5 ns Notes: 1. At fast cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns. 2. At fast cycles, RDWRS (for enabli ng read) = MAX (7.5 ns – WRL), 3.0 ns. 3. All –F speed grade devices are 20% slower than the standard numbers. RB = (RDB+RBLKB) RPE RDATA EMPTY EQTH, GETH FULL (Empty inhibits read) Cycle Start WB tRDWRS tERDH, tFRDH tERDA, tFRDA tTHRDH tORDH tRPRDH tORDA tRPRDA tRDL tRDH tRPRDA tRDL tRDCYC tRDH tTHRDA

ProASICPLUS Flash Family FPGAs 1-68 v5.7 Asynchronous FIFO Write Note: The plot shows the normal operation status. Figure 1-44  Asynchronous FIFO Write Table 1-62  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes DWRH DI hold from WB ↑ 1.5 ns DWRS DI setup to WB ↑ 0.5 ns PARGEN is inactive DWRS DI setup to WB ↑ 2.5 ns PARGEN is active EWRH, FWRH, THWRH Old EMPTY, FULL, EQTH, & GETH valid hold time after WB ↑ 0.5 ns Empty/full/thresh are invalid from the end of hold until the new access is complete EWRA EMPTY ↓ access from WB ↑ 3.0 1 ns FWRA New FULL access from WB ↑ 3.01 ns THWRA EQTH or GETH access from WB ↑ 4.5 ns WPDA WPE access from DI 3.0 ns WPE is invalid while PARGEN is active WPDH WPE hold from DI 1.0 ns WRCYC Cycle time 7.5 ns WRRDS RB ↑, clearing FULL, setup to WB ↓ 3.02 ns Enabling the write operation

1.0 Inhibiting the write operation

WRH WB high phase 3.0 ns Inactive WRL WB low phase 3.0 ns Active Notes: 1. At fast cycles, EWRA, FWRA = MAX (7.5 ns – WRL), 3.0 ns. 2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns – RDL), 3.0 ns. 3. All –F speed grade devices are 20% slower than the standard numbers. 4. After FIFO reset, WRB needs an initial falling edge prior to any write actions. WPE WDATA (Full inhibits write) WB = (WRB+WBLKB) EMPTY EQTH, GETH FULL Cycle Start RB tWRRDS tDWRH tWPDHtWPDA tDWRS tEWRH, tFWRH tEWRA, tFWRA tTHWRH tTHWRA tWRHtWRL tWRCYC

ProASICPLUS Flash Family FPGAs v5.7 1-69 Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) Note: The plot shows the normal operation status. Figure 1-45  Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) Table 1-63  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns ECBA New EMPTY access from RCLKS ↓ 3.0 1 ns FCBA FULL ↓ access from RCLKS ↓ 3.0 1 ns ECBH, FCBH, THCBH Old EMPTY, FULL, EQTH, & GETH valid hold time from RCLKS ↓ 1.0 ns Empty/full/thresh are invalid from the end of hold until the new access is complete OCA New DO access from RCLKS ↑ 7.5 ns OCH Old DO valid from RCLKS ↑ 3.0 ns RDCH RDB hold from RCLKS ↑ 0.5 ns RDCS RDB setup to RCLKS ↑ 1.0 ns RPCA New RPE access from RCLKS ↑ 9.5 ns RPCH Old RPE valid from RCLKS ↑ 3.0 ns HCBA EQTH or GETH access from RCLKS ↓ 4.5 ns Notes: 1. At fast cycles, ECBA and FC BA = MAX (7.5 ns – CMH), 3.0 ns. 2. All –F speed grade devices are 20% slower than the standard numbers. RCLK RPE RDATA EMPTY EQTH, GETH FULL RDB tRDCH tOCH tRPCH tRDCS Old Data Out New Valid Data Out (Empty Inhibits Read) Cycle Start tECBH, tFCBH tECBA, tFCBA tOCA tRPCA tCMH tCML tCCYC tTHCBH tHCBA

ProASICPLUS Flash Family FPGAs 1-70 v5.7 Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) Note: The plot shows the normal operation status. Figure 1-46  Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) Table 1-64  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns ECBA New EMPTY access from RCLKS ↓ 3.0 1 ns FCBA FULL ↓ access from RCLKS ↓ 3.0 1 ns ECBH, FCBH, THCBH Old EMPTY, FULL, EQTH, & GETH valid hold time from RCLKS ↓ 1.0 ns Empty/full/thresh are invalid from the end of hold until the new access is complete OCA New DO access from RCLKS ↑ 2.0 ns OCH Old DO valid from RCLKS ↑ 0.75 ns RDCH RDB hold from RCLKS ↑ 0.5 ns RDCS RDB setup to RCLKS ↑ 1.0 ns RPCA New RPE access from RCLKS ↑ 4.0 ns RPCH Old RPE valid from RCLKS ↑ 1.0 ns HCBA EQTH or GETH access from RCLKS ↓ 4.5 ns Notes: 1. At fast cycles, ECBA and FC BA = MAX (7.5 ns – CMS), 3.0 ns. 2. All –F speed grade devices are 20% slower than the standard numbers. RCLK RPE RDATA EMPTY EQTH, GETH FULL Old Data Out New Valid Data Out RDB Cycle Start Old RPE Out New RPE Out tECBH, tFCBH tRDCH tRDCS tOCA tECBA, tFCBA tTHCBH tHCBA tCMH tCML tCCYC tRPCH tOCH tRPCA

ProASICPLUS Flash Family FPGAs v5.7 1-71 Synchronous FIFO Write Note: The plot shows the normal operation status. Figure 1-47  Synchronous FIFO Write Table 1-65  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns DCH DI hold from WCLKS ↑ 0.5 ns DCS DI setup to WCLKS ↑ 1.0 ns FCBA New FULL access from WCLKS ↓ 3.0 1 ns ECBA EMPTY ↓ access from WCLKS ↓ 3.0 1 ns ECBH, FCBH, HCBH Old EMPTY, FULL, EQTH, & GETH valid hold time from WCLKS ↓ 1.0 ns Empty/full/thresh are invalid from the end of hold until the new access is complete HCBA EQTH or GETH access from WCLKS ↓ 4.5 ns WPCA New WPE access from WCLKS ↑ 3.0 ns WPE is invalid, while PARGEN is active WPCH Old WPE valid from WCLKS ↑ 0.5 ns WRCH, WBCH WRB & WBLKB hold from WCLKS ↑ 0.5 ns WRCS, WBCS WRB & WBLKB setup to WCLKS ↑ 1.0 ns Notes: 1. At fast cycles, ECBA and FC BA = MAX (7.5 ns – CMH), 3.0 ns. 2. All –F speed grade devices are 20% slower than the standard numbers. WCLKS WPE DI EMPTY EQTH, GETH FULL (Full Inhibits Write) WRB, WBLKB Cycle Start tWRCH, tWBCH tECBH, tFCBH tECBA, tFCBA tHCBA tWRCS, tWBCS tDCS tWPCA tCMH tCML tCCYC tWPCH tDCH tHCBH

ProASICPLUS Flash Family FPGAs 1-72 v5.7 FIFO Reset Notes: 1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be low. 2. The plot shows the normal operation status. Figure 1-48  FIFO Reset Table 1-66  TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CBRSH1 WCLKS or RCLKS ↑ hold from RESETB ↑ 1.5 ns Synchronous mode only CBRSS1 WCLKS or RCLKS ↓ setup to RESETB ↑ 1.5 ns Synchronous mode only ERSA New EMPTY ↑ access from RESETB ↓ 3.0 ns FRSA FULL ↓ access from RESETB ↓ 3.0 ns RSL RESETB low phase 7.5 ns THRSA EQTH or GETH access from RESETB ↓ 4.5 ns WBRSH1 WB ↓ hold from RESETB ↑ 1.5 ns Asynchronous mode only WBRSS1 WB ↑ setup to RESETB ↑ 1.5 ns Asynchronous mode only Notes: 1. During rest, the enables (WRB and RBD) must be hi gh OR the clocks (WCLKS and RCKLS) must be low. 2. All –F speed grade devices are 20% slower than the standard numbers. RESETB EMPTY EQTH, GETH FULL WRB/RBD1 Cycle Start Cycle StartWCLKS, RCLKS1 tERSA, tFRSA tTHRSA tCBRSS tWBRSS tCBRSH tWBRSH tRSL

ProASICPLUS Flash Family FPGAs v5.7 1-73 Pin Description User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL and LVCMOS specifications. Unused I/O pins are configured as inputs with pull-up resistors. NC No Connect To maintain compatibility with other Actel ProASIC PLUS products, it is recommended that this pin not be connected to the circuitry on the board. GL Global Pin Low skew input pin for clock or other global signals. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as a normal I/O. GLMX Global Multiplexing Pin Low skew input pin for clock or other global signals. This pin can be used in one of two special ways (refer to Actel’s Using ProASICPLUS Clock Conditioning Circuits). When the external feedback option is selected for the PLL block, this pin is rout ed as the external feedback source to the clock conditioning circuit. In applications where two di fferent signals access the same global net at different times through the use of GLMXx and GLMXLx macros, this pin will be fixed as one of the source pins. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as any normal I/O. If not used, the GLMXx pin will be configured as an input with pull-up. Dedicated Pins GND Ground Common ground supply voltage. VDD Logic Array Power Supply Pin 2.5 V supply voltage. VDDP I/O Pad Power Supply Pin 2.5 V or 3.3 V supply voltage. TMS Test Mode Select The TMS pin controls the use of boundary-scan circuitry. This pin has an internal pull-up resistor. TCK Test Clock Clock input pin for boundary scan (maximum 10 MHz). Actel recommends adding a nominal 20 kΩ pull-up resistor to this pin. TDI Test Data In Serial input for boundary scan. A dedicated pull-up resistor is included to pull this pin high when not being driven. TDO Test Data Out Serial output for boundary scan. Actel recommends adding a nominal 20kΩ pull-up resistor to this pin. TRST Test Reset Input Asynchronous, active-low input pin for resetting boundary-scan circuitry. This pin has an internal pull-up resistor. For more information, please refer to Power-up Behavior of ProASICPLUS Devices application note. Special Function Pins RCK Running Clock A free running clock is needed during programming if the programmer cannot guarantee that TCK will be uninterrupted. If not used, th is pin has an internal pull- up and can be left floating. NPECL User Negative Input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. PPECL User Positive Input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. AVDD PLL Power Supply Analog VDD should be VDD (core voltage) 2.5 V (nominal) and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel’s Using ProASIC PLUS Clock Conditioning Circuits application note. If the clock conditioning circuitry is not used in a design, AVDD can either be left floating or tied to 2.5 V. AGND PLL Power Ground The analog ground can be connected to the system ground. For more information, refer to Actel’s Using ProASICPLUS Clock Conditioning Circuits application note. If the PLLs or clock conditioning circuitry are not used in a design, AGND should be tied to GND.

ProASICPLUS Flash Family FPGAs 1-74 v5.7 VPP Programming Supply Pin This pin may be connected to any voltage between GND and 16.5 V during normal operation, or it can be left unconnected.2 For information on using this pin during programming, see the In-System Programming ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to VDDP. VPN Programming Supply Pin This pin may be connected to any voltage between 0.5V and –13.8 V during normal operation, or it can be left unconnected.3 For information on using this pin during programming, see the In-System Programming ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to GND. Recommended Design Practice for VPN/VPP ProASICPLUS Devices – APA450, APA600, APA750, APA1000 Bypass capacitors are required from V PP to GND and V PN to GND for all ProASIC PLUS devices during programming. During the erase cycle, ProASIC PLUS devices may have current surges on the V PP and V PN power supplies. The only way to maintain the integrity of the power distribution to the ProASIC PLUS device during these current surges is to counteract the inductance of the finite length conductors that distribute the power to the device. This can be accomplished by providing sufficient bypass capacitance between the V PP and V PN pins and GND (using the shortest paths possible). Without sufficient bypass capacitance to counteract the inductance, the V PP and V PN pins may incur a voltage spike beyond the voltage that the device can withstand. This issue applies to all programming configurations. The solution prevents spikes from damaging the ProASICPLUS devices. Bypass capacitors are required for the V PP and V PN pads. Use a 0.01 µF to 0.1 µF ceramic capacitor with a 25 V or greater rating. To filter low- frequency noise (decoupling), use a 4.7 µF (low ESR, <1 <Ω, tantalum, 25 V or greater rating) capacitor. The capacitors should be located as close to the device pins as possible (within 2.5 cm is desirable). The smaller, high- frequency capacitor should be placed closer to the device pins than the larger low-fr equency capacitor. The same dual-capacitor circuit should be used on both the V PP and VPN pins (Figure 1-49). ProASICPLUS Devices – APA075, APA150, APA300 These devices do not require bypass capacitors on the VPP and VPN pins as long as the total combined distance of the programming cable and the trace length on the board is less than or equal to 30 inches. Note: For trace lengths greater than 30 inches, use the bypass capacitor recommendations in the previous section. 2. There is a nominal 40 k Ω pull-up resistor on VPP. 3. There is a nominal 40 k Ω pull-down resistor on VPN. Figure 1-49  ProASICPLUS VPP and VPN Capacitor Requirements 2.5cm 0.1μF to 0.01μF Programming Header or Supplies 4.7μFActel ProASIC Device _VPP VPN 0.1μF to 0.01μF 4.7μF PLUS

ProASICPLUS Flash Family FPGAs v5.7 2-1 Package Pin Assignments 100-Pin TQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. 100-Pin TQFP 100

ProASICPLUS Flash Family FPGAs 2-2 v5.7 100-Pin TQFP Pin Number APA075 Function APA150 Function 1G N D G N D 2I / OI / O 3I / OI / O 4I / OI / O 5I / OI / O 6I / OI / O 7I / OI / O 8I / OI / O 9G N D G N D

10 I/O / GLMX1 I/O / GLMX1

11 I/O / GL1 I/O / GL1

12 AGND AGND

13 NPECL1 NPECL1

14 AVDD AVDD

15 PPECL1 / Input PPECL1 / Input

16 I/O / GL2 I/O / GL2

18 I/O I/O

19 I/O I/O

20 I/O I/O

21 I/O I/O

22 I/O I/O

23 I/O I/O

24 I/O I/O

25 GND GND

27 I/O I/O

28 I/O I/O

29 I/O I/O

30 I/O I/O

31 I/O I/O

32 I/O I/O

33 I/O I/O

34 I/O I/O

35 I/O I/O

36 I/O I/O

37 V DD VDD

38 GND GND

40 GND GND

41 I/O I/O

42 I/O I/O

43 I/O I/O

44 I/O I/O

45 I/O I/O

46 I/O I/O

47 TCK TCK

48 TDI TDI

49 TMS TMS

51 GND GND

52 V PP VPP

53 V PN VPN

54 TDO TDO

55 TRST TRST

56 RCK RCK

57 I/O I/O

58 I/O I/O

59 I/O I/O

60 I/O / GL3 I/O / GL3

61 PPECL2 / Input PPECL2 / Input

62 AVDD AVDD

63 NPECL2 NPECL2

64 AGND AGND

65 I/O / GL4 I/O / GL4

66 I/O / GLMX2 I/O / GLMX2

67 GND GND

69 I/O I/O

70 I/O I/O

71 I/O I/O

72 I/O I/O

73 I/O I/O

74 I/O I/O

75 GND GND

77 I/O I/O

78 I/O I/O

79 I/O I/O

80 I/O I/O

81 I/O I/O

82 I/O I/O

83 I/O I/O

84 I/O I/O

85 I/O I/O

86 GND GND

88 GND GND

90 I/O I/O

91 I/O I/O

92 I/O I/O

93 I/O I/O

94 I/O I/O

95 I/O I/O

96 I/O I/O

97 I/O I/O

98 I/O I/O

99 I/O I/O

ProASICPLUS Flash Family FPGAs v5.7 2-3 144-Pin TQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. 144-Pin TQFP 144

ProASICPLUS Flash Family FPGAs 2-4 v5.7 144-Pin TQFP Pin Number APA075 Function 1I / O 2I / O 3I / O 4I / O 5I / O 6I / O 7I / O 8I / O DD

10 GND

11 V DDP

12 I/O

13 I/O

14 I/O

15 I/O / GLMX1

16 I/O / GL1

17 AGND

18 NPECL1

19 AVDD

20 PPECL1 /

21 I/O / GL2

22 I/O

23 I/O

24 I/O

25 I/O

26 I/O

27 GND

29 I/O

30 I/O

31 I/O

32 I/O

33 I/O

34 I/O

35 I/O

36 I/O

37 I/O

38 I/O

39 I/O

40 I/O

41 I/O

42 I/O

43 I/O

44 I/O

46 GND

47 V DDP

48 I/O

49 I/O

50 I/O

51 I/O

52 I/O

53 I/O

54 I/O

55 I/O

56 I/O

57 I/O

58 I/O

59 I/O

60 I/O

61 I/O

63 GND

65 I/O

66 I/O

67 I/O

68 I/O

69 TCK

70 TDI

71 TMS

73 V PP

74 V PN

75 TDO

76 TRST

77 RCK

78 I/O

79 I/O

80 I/O

82 GND

83 I/O

84 I/O

85 I/O

86 I/O

87 I/O

88 I/O / GL3

89 PPECL2 /

90 AVDD

91 NPECL2

92 AGND

93 I/O / GL4

94 I/O / GLMX2

95 I/O

96 I/O

97 I/O

99 GND

100 V DD

101 I/O

102 I/O

103 I/O

104 I/O

105 I/O

106 I/O

107 I/O

108 I/O

109 I/O

110 I/O

111 I/O

112 I/O

113 I/O

114 I/O

115 I/O

116 I/O

118 GND

119 V DD

120 I/O

121 I/O

122 I/O

123 I/O

124 I/O

125 I/O

126 I/O

127 I/O

128 I/O

129 I/O

130 I/O

131 I/O

132 I/O

133 I/O

135 GND

137 I/O

138 I/O

139 I/O

140 I/O

141 I/O

142 I/O

143 I/O

144 I/O

ProASICPLUS Flash Family FPGAs v5.7 2-5 208-Pin PQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. 208-Pin PQFP 1 208

ProASICPLUS Flash Family FPGAs 2-6 v5.7 208-Pin PQFP Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

1 GND GND GND GND GND GND GND

2 I / OI / OI / OI / OI / OI / OI / O

3 I / OI / OI / OI / OI / OI / OI / O

4 I / OI / OI / OI / OI / OI / OI / O

5 I / OI / OI / OI / OI / OI / OI / O

6 I / OI / OI / OI / OI / OI / OI / O

7 I / OI / OI / OI / OI / OI / OI / O

8 I / OI / OI / OI / OI / OI / OI / O

9 I / OI / OI / OI / OI / OI / OI / O

10 I/O I/O I/O I/O I/O I/O I/O

11 I/O I/O I/O I/O I/O I/O I/O

12 I/O I/O I/O I/O I/O I/O I/O

13 I/O I/O I/O I/O I/O I/O I/O

14 I/O I/O I/O I/O I/O I/O I/O

15 I/O I/O I/O I/O I/O I/O I/O

DD VDD VDD VDD VDD VDD VDD

17 GND GND GND GND GND GND GND

18 I/O I/O I/O I/O I/O I/O I/O

19 I/O I/O I/O I/O I/O I/O I/O

20 I/O I/O I/O I/O I/O I/O I/O

21 I/O I/O I/O I/O I/O I/O I/O

DDP VDDP VDDP VDDP VDDP VDDP VDDP

23 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1

24 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2

25 AGND AGND AGND AGND AGND AGND AGND

26 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1

27 AVDD AVDD AVDD AVDD AVDD AVDD AVDD

28 PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input

29 GND GND GND GND GND GND GND

30 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1

31 I/O I/O I/O I/O I/O I/O I/O

32 I/O I/O I/O I/O I/O I/O I/O

33 I/O I/O I/O I/O I/O I/O I/O

34 I/O I/O I/O I/O I/O I/O I/O

35 I/O I/O I/O I/O I/O I/O I/O

ProASICPLUS Flash Family FPGAs v5.7 2-7

36 V DD VDD VDD VDD VDD VDD VDD

37 I/O I/O I/O I/O I/O I/O I/O

38 I/O I/O I/O I/O I/O I/O I/O

39 I/O I/O I/O I/O I/O I/O I/O

DDP VDDP VDDP VDDP VDDP VDDP VDDP

41 GND GND GND GND GND GND GND

42 I/O I/O I/O I/O I/O I/O I/O

43 I/O I/O I/O I/O I/O I/O I/O

44 I/O I/O I/O I/O I/O I/O I/O

45 I/O I/O I/O I/O I/O I/O I/O

46 I/O I/O I/O I/O I/O I/O I/O

47 I/O I/O I/O I/O I/O I/O I/O

48 I/O I/O I/O I/O I/O I/O I/O

49 I/O I/O I/O I/O I/O I/O I/O

50 I/O I/O I/O I/O I/O I/O I/O

51 I/O I/O I/O I/O I/O I/O I/O

52 GND GND GND GND GND GND GND

DDP VDDP VDDP VDDP VDDP VDDP VDDP

54 I/O I/O I/O I/O I/O I/O I/O

55 I/O I/O I/O I/O I/O I/O I/O

56 I/O I/O I/O I/O I/O I/O I/O

57 I/O I/O I/O I/O I/O I/O I/O

58 I/O I/O I/O I/O I/O I/O I/O

59 I/O I/O I/O I/O I/O I/O I/O

60 I/O I/O I/O I/O I/O I/O I/O

61 I/O I/O I/O I/O I/O I/O I/O

62 I/O I/O I/O I/O I/O I/O I/O

63 I/O I/O I/O I/O I/O I/O I/O

64 I/O I/O I/O I/O I/O I/O I/O

65 GND GND GND GND GND GND GND

66 I/O I/O I/O I/O I/O I/O I/O

67 I/O I/O I/O I/O I/O I/O I/O

68 I/O I/O I/O I/O I/O I/O I/O

69 I/O I/O I/O I/O I/O I/O I/O

70 I/O I/O I/O I/O I/O I/O I/O

ProASICPLUS Flash Family FPGAs 2-8 v5.7

71 V DD VDD VDD VDD VDD VDD VDD

72 V DDP VDDP VDDP VDDP VDDP VDDP VDDP

73 I/O I/O I/O I/O I/O I/O I/O

74 I/O I/O I/O I/O I/O I/O I/O

75 I/O I/O I/O I/O I/O I/O I/O

76 I/O I/O I/O I/O I/O I/O I/O

77 I/O I/O I/O I/O I/O I/O I/O

78 I/O I/O I/O I/O I/O I/O I/O

79 I/O I/O I/O I/O I/O I/O I/O

80 I/O I/O I/O I/O I/O I/O I/O

81 GND GND GND GND GND GND GND

82 I/O I/O I/O I/O I/O I/O I/O

83 I/O I/O I/O I/O I/O I/O I/O

84 I/O I/O I/O I/O I/O I/O I/O

85 I/O I/O I/O I/O I/O I/O I/O

86 I/O I/O I/O I/O I/O I/O I/O

87 I/O I/O I/O I/O I/O I/O I/O

DD VDD VDD VDD VDD VDD VDD

89 V DDP VDDP VDDP VDDP VDDP VDDP VDDP

90 I/O I/O I/O I/O I/O I/O I/O

91 I/O I/O I/O I/O I/O I/O I/O

92 I/O I/O I/O I/O I/O I/O I/O

93 I/O I/O I/O I/O I/O I/O I/O

94 I/O I/O I/O I/O I/O I/O I/O

95 I/O I/O I/O I/O I/O I/O I/O

96 I/O I/O I/O I/O I/O I/O I/O

97 GND GND GND GND GND GND GND

98 I/O I/O I/O I/O I/O I/O I/O

99 I/O I/O I/O I/O I/O I/O I/O

100 I/O I/O I/O I/O I/O I/O I/O

101 TCK TCK TCK TCK TCK TCK TCK

102 TDI TDI TDI TDI TDI TDI TDI

103 TMS TMS TMS TMS TMS TMS TMS

DDP VDDP VDDP VDDP VDDP VDDP VDDP

105 GND GND GND GND GND GND GND

ProASICPLUS Flash Family FPGAs v5.7 2-9

106 V PP VPP VPP VPP VPP VPP VPP

107 V PN VPN VPN VPN VPN VPN VPN

108 TDO TDO TDO TDO TDO TDO TDO

109 TRST TRST TRST TRST TRST TRST TRST

110 RCK RCK RCK RCK RCK RCK RCK

111 I/O I/O I/O I/O I/O I/O I/O

112 I/O I/O I/O I/O I/O I/O I/O

113 I/O I/O I/O I/O I/O I/O I/O

114 I/O I/O I/O I/O I/O I/O I/O

115 I/O I/O I/O I/O I/O I/O I/O

116 I/O I/O I/O I/O I/O I/O I/O

117 I/O I/O I/O I/O I/O I/O I/O

118 I/O I/O I/O I/O I/O I/O I/O

119 I/O I/O I/O I/O I/O I/O I/O

120 I/O I/O I/O I/O I/O I/O I/O

121 I/O I/O I/O I/O I/O I/O I/O

122 GND GND GND GND GND GND GND

DDP VDDP VDDP VDDP VDDP VDDP VDDP

124 I/O I/O I/O I/O I/O I/O I/O

125 I/O I/O I/O I/O I/O I/O I/O

DD VDD VDD VDD VDD VDD VDD

127 I/O I/O I/O I/O I/O I/O I/O

128 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3

129 PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input

130 GND GND GND GND GND GND GND

131 AVDD AVDD AVDD AVDD AVDD AVDD AVDD

132 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2

133 AGND AGND AGND AGND AGND AGND AGND

134 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4

135 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2

136 I/O I/O I/O I/O I/O I/O I/O

137 I/O I/O I/O I/O I/O I/O I/O

DDP VDDP VDDP VDDP VDDP VDDP VDDP

139 I/O I/O I/O I/O I/O I/O I/O

140 I/O I/O I/O I/O I/O I/O I/O

ProASICPLUS Flash Family FPGAs 2-10 v5.7

141 GND GND GND GND GND GND GND

142 V DD VDD VDD VDD VDD VDD VDD

143 I/O I/O I/O I/O I/O I/O I/O

144 I/O I/O I/O I/O I/O I/O I/O

145 I/O I/O I/O I/O I/O I/O I/O

146 I/O I/O I/O I/O I/O I/O I/O

147 I/O I/O I/O I/O I/O I/O I/O

148 I/O I/O I/O I/O I/O I/O I/O

149 I/O I/O I/O I/O I/O I/O I/O

150 I/O I/O I/O I/O I/O I/O I/O

151 I/O I/O I/O I/O I/O I/O I/O

152 I/O I/O I/O I/O I/O I/O I/O

153 I/O I/O I/O I/O I/O I/O I/O

154 I/O I/O I/O I/O I/O I/O I/O

155 I/O I/O I/O I/O I/O I/O I/O

156 GND GND GND GND GND GND GND

DDP VDDP VDDP VDDP VDDP VDDP VDDP

158 I/O I/O I/O I/O I/O I/O I/O

159 I/O I/O I/O I/O I/O I/O I/O

160 I/O I/O I/O I/O I/O I/O I/O

161 I/O I/O I/O I/O I/O I/O I/O

162 GND GND GND GND GND GND GND

163 I/O I/O I/O I/O I/O I/O I/O

164 I/O I/O I/O I/O I/O I/O I/O

165 I/O I/O I/O I/O I/O I/O I/O

166 I/O I/O I/O I/O I/O I/O I/O

167 I/O I/O I/O I/O I/O I/O I/O

168 I/O I/O I/O I/O I/O I/O I/O

169 I/O I/O I/O I/O I/O I/O I/O

DDP VDDP VDDP VDDP VDDP VDDP VDDP

171 V DD VDD VDD VDD VDD VDD VDD

172 I/O I/O I/O I/O I/O I/O I/O

173 I/O I/O I/O I/O I/O I/O I/O

174 I/O I/O I/O I/O I/O I/O I/O

175 I/O I/O I/O I/O I/O I/O I/O

ProASICPLUS Flash Family FPGAs v5.7 2-11

176 I/O I/O I/O I/O I/O I/O I/O

177 I/O I/O I/O I/O I/O I/O I/O

178 GND GND GND GND GND GND GND

179 I/O I/O I/O I/O I/O I/O I/O

180 I/O I/O I/O I/O I/O I/O I/O

181 I/O I/O I/O I/O I/O I/O I/O

182 I/O I/O I/O I/O I/O I/O I/O

183 I/O I/O I/O I/O I/O I/O I/O

184 I/O I/O I/O I/O I/O I/O I/O

185 I/O I/O I/O I/O I/O I/O I/O

DDP VDDP VDDP VDDP VDDP VDDP VDDP

187 V DD VDD VDD VDD VDD VDD VDD

188 I/O I/O I/O I/O I/O I/O I/O

189 I/O I/O I/O I/O I/O I/O I/O

190 I/O I/O I/O I/O I/O I/O I/O

191 I/O I/O I/O I/O I/O I/O I/O

192 I/O I/O I/O I/O I/O I/O I/O

193 I/O I/O I/O I/O I/O I/O I/O

194 I/O I/O I/O I/O I/O I/O I/O

195 GND GND GND GND GND GND GND

196 I/O I/O I/O I/O I/O I/O I/O

197 I/O I/O I/O I/O I/O I/O I/O

198 I/O I/O I/O I/O I/O I/O I/O

199 I/O I/O I/O I/O I/O I/O I/O

200 I/O I/O I/O I/O I/O I/O I/O

201 I/O I/O I/O I/O I/O I/O I/O

202 I/O I/O I/O I/O I/O I/O I/O

203 I/O I/O I/O I/O I/O I/O I/O

204 I/O I/O I/O I/O I/O I/O I/O

205 I/O I/O I/O I/O I/O I/O I/O

206 I/O I/O I/O I/O I/O I/O I/O

207 I/O I/O I/O I/O I/O I/O I/O

DDP VDDP VDDP VDDP VDDP VDDP VDDP 208-Pin PQFP Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-12 v5.7 208-Pin CQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. Ceramic Tie Bar No. 1 208-Pin CQFP 156 155 154 153 142 141 140 139 138 137 136 135 134 108 107 106 105 101 102 103 104 208 207 206 205 194 193 192 191 190 189 188 187 186 160 159 158 157

ProASICPLUS Flash Family FPGAs v5.7 2-13 208-Pin CQFP Pin Number APA300 Function APA600 Function APA1000 Function 1G N D G N D G N D

2 I/O I/O I/O

3 I/O I/O I/O

4 I/O I/O I/O

5 I/O I/O I/O

6 I/O I/O I/O

7 I/O I/O I/O

8 I/O I/O I/O

9 I/O I/O I/O

10 I/O I/O I/O

11 I/O I/O I/O

12 I/O I/O I/O

13 I/O I/O I/O

14 I/O I/O I/O

15 I/O I/O I/O

17 GND GND GND

18 I/O I/O I/O

19 I/O I/O I/O

20 I/O I/O I/O

21 I/O I/O I/O

23 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1

24 I/O / GL2 I/O / GL2 I/O / GL2

25 AGND AGND AGND

26 NPECL1 NPECL1 NPECL1

27 AVDD AVDD AVDD

28 PPECL1 / Input PPECL1 / Input PPECL1 / Input

29 GND GND GND

30 I/O / GL1 I/O / GL1 I/O / GL1

31 I/O I/O I/O

32 I/O I/O I/O

33 I/O I/O I/O

34 I/O I/O I/O

35 I/O I/O I/O

36 V DD VDD VDD

37 I/O I/O I/O

38 I/O I/O I/O

39 I/O I/O I/O

41 GND GND GND

42 I/O I/O I/O

43 I/O I/O I/O

44 I/O I/O I/O

45 I/O I/O I/O

46 I/O I/O I/O

47 I/O I/O I/O

48 I/O I/O I/O

49 I/O I/O I/O

50 I/O I/O I/O

51 I/O I/O I/O

52 GND GND GND

54 I/O I/O I/O

55 I/O I/O I/O

56 I/O I/O I/O

57 I/O I/O I/O

58 I/O I/O I/O

59 I/O I/O I/O

60 I/O I/O I/O

61 I/O I/O I/O

62 I/O I/O I/O

63 I/O I/O I/O

64 I/O I/O I/O

65 GND GND GND

66 I/O I/O I/O

67 I/O I/O I/O

68 I/O I/O I/O

69 I/O I/O I/O

70 I/O I/O I/O

ProASICPLUS Flash Family FPGAs 2-14 v5.7

71 V DD VDD VDD

72 V DDP VDDP VDDP

73 I/O I/O I/O

74 I/O I/O I/O

75 I/O I/O I/O

76 I/O I/O I/O

77 I/O I/O I/O

78 I/O I/O I/O

79 I/O I/O I/O

80 I/O I/O I/O

81 GND GND GND

82 I/O I/O I/O

83 I/O I/O I/O

84 I/O I/O I/O

85 I/O I/O I/O

86 I/O I/O I/O

87 I/O I/O I/O

89 V DDP VDDP VDDP

90 I/O I/O I/O

91 I/O I/O I/O

92 I/O I/O I/O

93 I/O I/O I/O

94 I/O I/O I/O

95 I/O I/O I/O

96 I/O I/O I/O

97 GND GND GND

98 I/O I/O I/O

99 I/O I/O I/O

100 I/O I/O I/O

101 TCK TCK TCK

102 TDI TDI TDI

103 TMS TMS TMS

105 GND GND GND

106 V PP VPP VPP

107 V PN VPN VPN

108 TDO TDO TDO

109 TRST TRST TRST

110 RCK RCK RCK

111 I/O I/O I/O

112 I/O I/O I/O

113 I/O I/O I/O

114 I/O I/O I/O

115 I/O I/O I/O

116 I/O I/O I/O

117 I/O I/O I/O

118 I/O I/O I/O

119 I/O I/O I/O

120 I/O I/O I/O

121 I/O I/O I/O

122 GND GND GND

124 I/O I/O I/O

125 I/O I/O I/O

126 V DD VDD VDD

127 I/O I/O I/O

128 I/O / GL3 I/O / GL3 I/O / GL3

129 PPECL2 / Input PPECL2 / Input PPECL2 / Input

130 GND GND GND

131 AVDD AVDD AVDD

132 NPECL2 NPECL2 NPECL2

133 AGND AGND AGND

134 I/O / GL4 I/O / GL4 I/O / GL4

135 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2

136 I/O I/O I/O

137 I/O I/O I/O

139 I/O I/O I/O

140 I/O I/O I/O

ProASICPLUS Flash Family FPGAs v5.7 2-15

141 GND GND GND

142 V DD VDD VDD

143 I/O I/O I/O

144 I/O I/O I/O

145 I/O I/O I/O

146 I/O I/O I/O

147 I/O I/O I/O

148 I/O I/O I/O

149 I/O I/O I/O

150 I/O I/O I/O

151 I/O I/O I/O

152 I/O I/O I/O

153 I/O I/O I/O

154 I/O I/O I/O

155 I/O I/O I/O

156 GND ]GND GND

158 I/O I/O I/O

159 I/O I/O I/O

160 I/O I/O I/O

161 I/O I/O I/O

162 GND GND GND

163 I/O I/O I/O

164 I/O I/O I/O

165 I/O I/O I/O

166 I/O I/O I/O

167 I/O I/O I/O

168 I/O I/O I/O

169 I/O I/O I/O

171 V DD VDD VDD

172 I/O I/O I/O

173 I/O I/O I/O

174 I/O I/O I/O

175 I/O I/O I/O

176 I/O I/O I/O

177 I/O I/O I/O

178 GND GND GND

179 I/O I/O I/O

180 I/O I/O I/O

181 I/O I/O I/O

182 I/O I/O I/O

183 I/O I/O I/O

184 I/O I/O I/O

185 I/O I/O I/O

187 V DD VDD VDD

188 I/O I/O I/O

189 I/O I/O I/O

190 I/O I/O I/O

191 I/O I/O I/O

192 I/O I/O I/O

193 I/O I/O I/O

194 I/O I/O I/O

195 GND GND GND

196 I/O I/O I/O

197 I/O I/O I/O

198 I/O I/O I/O

199 I/O I/O I/O

200 I/O I/O I/O

201 I/O I/O I/O

202 I/O I/O I/O

203 I/O I/O I/O

204 I/O I/O I/O

205 I/O I/O I/O

206 I/O I/O I/O

207 I/O I/O I/O

ProASICPLUS Flash Family FPGAs 2-16 v5.7 352-Pin CQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. Ceramic Tie Bar 352-Pin CQFP 127 128 129 130 131 132 133 134 135 173 174175 176 264 263 262 261 180 179 178 177 223 222 221 220 219 218 217 216 215 352 351 350 349 339 338 337 336 335 334 333 332 331 268 267266 265 Pin 1

ProASICPLUS Flash Family FPGAs v5.7 2-17 352-Pin CQFP Pin Number APA300 Function APA600 Function APA1000 Function 1I / O I / O I / O 2I / O I / O I / O 3I / O I / O I / O 4I / O I / O I / O 5I / O I / O I / O 6I / O I / O I / O DD VDD VDD

8 GND GND GND

16 I/O I/O I/O

17 I/O I/O I/O

19 GND GND GND

22 I/O I/O I/O

23 I/O I/O I/O

24 I/O I/O I/O

25 I/O I/O I/O

26 I/O I/O I/O

27 I/O I/O I/O

28 I/O I/O I/O

30 GND GND GND

31 V DDP VDDP VDDP

36 I/O I/O I/O

38 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1

39 I/O / GL2 I/O / GL2 I/O / GL2

40 AGND AGND AGND

41 AVDD AVDD AVDD

42 NPECL1 NPECL1 NPECL1

43 PPECL1 / Input PPECL1 / Input PPECL1 / Input

44 I/O / GL1 I/O / GL1 I/O / GL1

48 GND GND GND

49 V DDP VDDP VDDP

52 I/O I/O I/O

53 I/O I/O I/O

59 GND GND GND

65 I/O I/O I/O

70 GND GND GND

72 I/O I/O I/O

ProASICPLUS Flash Family FPGAs 2-18 v5.7

88 I/O I/O I/O

90 GND GND GND

97 I/O I/O I/O

101 GND GND GND

102 V DD VDD VDD

103 I/O I/O I/O

104 I/O I/O I/O

105 I/O I/O I/O

106 I/O I/O I/O

107 I/O I/O I/O

108 I/O I/O I/O

109 I/O I/O I/O

110 I/O I/O I/O

112 GND GND GND

113 V DD VDD VDD

123 GND GND GND

124 V DD VDD VDD

126 I/O I/O I/O

128 I/O I/O I/O

129 I/O I/O I/O

130 I/O I/O I/O

131 I/O I/O I/O

132 I/O I/O I/O

134 GND GND GND

135 V DD VDD VDD

138 I/O I/O I/O

141 I/O I/O I/O

142 I/O I/O I/O

145 GND GND GND

146 V DD VDD VDD

ProASICPLUS Flash Family FPGAs v5.7 2-19

156 GND GND GND

157 V DD VDD VDD

162 I/O I/O I/O

167 GND GND GND

170 I/O I/O I/O

171 I/O I/O I/O

173 TCK TCK TCK

174 TDI TDI TDI

175 TMS TMS TMS

177 VPP VPP VPP

178 VPN VPN VPN

179 TDO TDO TDO

180 TRST TRST TRST

181 RCK RCK RCK

184 GND GND GND

185 V DD VDD VDD

186 I/O I/O I/O

187 I/O I/O I/O

206 GND GND GND

207 V DD VDD VDD

208 I/O I/O I/O

209 I/O I/O I/O

210 I/O I/O I/O

211 I/O I/O I/O

212 I/O I/O I/O

213 I/O I/O I/O

214 I/O I/O I/O

215 I/O I/O I/O

217 GND GND GND

218 V DD VDD VDD

219 I/O I/O I/O

220 I/O I/O I/O

221 I/O / GL3 I/O / GL3 I/O / GL3

222 PPECL2 / Input PPECL2 / Input PPECL2 / Input

ProASICPLUS Flash Family FPGAs 2-20 v5.7

223 NPECL2 NPECL2 NPECL2

224 AVDD AVDD AVDD

225 AGND AGND AGND

226 I/O / GL4 I/O / GL4 I/O / GL4

227 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2

228 I/O I/O I/O

229 I/O I/O I/O

230 I/O I/O I/O

231 I/O I/O I/O

232 I/O I/O I/O

233 I/O I/O I/O

235 GND GND GND

237 I/O I/O I/O

238 I/O I/O I/O

239 I/O I/O I/O

240 I/O I/O I/O

241 I/O I/O I/O

242 I/O I/O I/O

243 I/O I/O I/O

244 I/O I/O I/O

246 GND GND GND

247 V DD VDD VDD

248 I/O I/O I/O

249 I/O I/O I/O

250 I/O I/O I/O

251 I/O I/O I/O

252 I/O I/O I/O

253 I/O I/O I/O

254 I/O I/O I/O

255 I/O I/O I/O

257 GND GND GND

259 I/O I/O I/O

260 I/O I/O I/O

261 I/O I/O I/O

262 I/O I/O I/O

263 I/O I/O I/O

264 I/O I/O I/O

265 I/O I/O I/O

266 I/O I/O I/O

267 I/O I/O I/O

268 I/O I/O I/O

269 I/O I/O I/O

270 I/O I/O I/O

271 I/O I/O I/O

272 I/O I/O I/O

274 GND GND GND

275 V DDP VDDP VDDP

276 I/O I/O I/O

277 I/O I/O I/O

278 I/O I/O I/O

279 I/O I/O I/O

280 I/O I/O I/O

281 I/O I/O I/O

282 I/O I/O I/O

283 I/O I/O I/O

285 GND GND GND

286 V DDP VDDP VDDP

287 I/O I/O I/O

288 I/O I/O I/O

289 I/O I/O I/O

290 I/O I/O I/O

291 I/O I/O I/O

292 I/O I/O I/O

293 I/O I/O I/O

294 I/O I/O I/O

296 GND GND GND

ProASICPLUS Flash Family FPGAs v5.7 2-21

297 V DDP VDDP VDDP

298 I/O I/O I/O

299 I/O I/O I/O

300 I/O I/O I/O

301 I/O I/O I/O

302 I/O I/O I/O

303 I/O I/O I/O

304 I/O I/O I/O

305 I/O I/O I/O

307 GND GND GND

308 V DDP VDDP VDDP

309 I/O I/O I/O

310 I/O I/O I/O

311 I/O I/O I/O

312 I/O I/O I/O

313 I/O I/O I/O

314 I/O I/O I/O

315 I/O I/O I/O

316 I/O I/O I/O

318 GND GND GND

320 I/O I/O I/O

321 I/O I/O I/O

322 I/O I/O I/O

323 I/O I/O I/O

324 I/O I/O I/O

325 I/O I/O I/O

326 I/O I/O I/O

327 I/O I/O I/O

329 GND GND GND

331 I/O I/O I/O

332 I/O I/O I/O

333 I/O I/O I/O

334 I/O I/O I/O

335 I/O I/O I/O

336 I/O I/O I/O

337 I/O I/O I/O

338 I/O I/O I/O

340 GND GND GND

342 I/O I/O I/O

343 I/O I/O I/O

344 I/O I/O I/O

345 I/O I/O I/O

346 I/O I/O I/O

347 I/O I/O I/O

348 I/O I/O I/O

349 I/O I/O I/O

351 GND GND GND

352 V DDP VDDP VDDP

ProASICPLUS Flash Family FPGAs 2-22 v5.7 456-Pin PBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. 12356789101115 14 13 121617181920212223 4242526 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF A1 Ball Pad Corner

ProASICPLUS Flash Family FPGAs v5.7 2-23 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function A1 V DDP VDDP VDDP VDDP VDDP VDDP A2 V DDP VDDP VDDP VDDP VDDP VDDP A3 NC NC I/O I/O I/O I/O A4 NC NC I/O I/O I/O I/O A5 NC NC I/O I/O I/O I/O A6 NC NC I/O I/O I/O I/O A7 NC NC I/O I/O I/O I/O A 8 I / OI / OI / OI / OI / OI / O A 9 I / OI / OI / OI / OI / OI / O A10 I/O I/O I/O I/O I/O I/O A11 I/O I/O I/O I/O I/O I/O A12 I/O I/O I/O I/O I/O I/O A13 I/O I/O I/O I/O I/O I/O A14 I/O I/O I/O I/O I/O I/O A15 I/O I/O I/O I/O I/O I/O A16 I/O I/O I/O I/O I/O I/O A17 I/O I/O I/O I/O I/O I/O A18 I/O I/O I/O I/O I/O I/O A19 I/O I/O I/O I/O I/O I/O A20 NC NC I/O I/O I/O I/O A21 NC NC I/O I/O I/O I/O A22 NC NC I/O I/O I/O I/O A23 NC NC I/O I/O I/O I/O A24 NC NC I/O I/O I/O I/O A25 V DDP VDDP VDDP VDDP VDDP VDDP A26 V DDP VDDP VDDP VDDP VDDP VDDP B1 V DDP VDDP VDDP VDDP VDDP VDDP B2 V DDP VDDP VDDP VDDP VDDP VDDP B3 NC NC NC I/O I/O I/O B4 NC NC I/O I/O I/O I/O B5 NC NC I/O I/O I/O I/O B6 NC NC I/O I/O I/O I/O B7 NC NC I/O I/O I/O I/O B 8I / OI / OI / OI / OI / OI / O

ProASICPLUS Flash Family FPGAs 2-24 v5.7 B 9I / OI / OI / OI / OI / OI / O B10 I/O I/O I/O I/O I/O I/O B11 I/O I/O I/O I/O I/O I/O B12 I/O I/O I/O I/O I/O I/O B13 I/O I/O I/O I/O I/O I/O B14 I/O I/O I/O I/O I/O I/O B15 I/O I/O I/O I/O I/O I/O B16 I/O I/O I/O I/O I/O I/O B17 I/O I/O I/O I/O I/O I/O B18 I/O I/O I/O I/O I/O I/O B19 I/O I/O I/O I/O I/O I/O B20 NC NC I/O I/O I/O I/O B21 NC NC I/O I/O I/O I/O B22 NC NC I/O I/O I/O I/O B23 NC NC I/O I/O I/O I/O B24 NC NC I/O I/O I/O I/O B25 V DDP VDDP VDDP VDDP VDDP VDDP B26 V DDP VDDP VDDP VDDP VDDP VDDP C1 V DDP VDDP VDDP VDDP VDDP VDDP C2 NC I/O I/O I/O I/O I/O C3 V DDP VDDP VDDP VDDP VDDP VDDP C4 NC NC NC I/O I/O I/O C5 NC NC I/O I/O I/O I/O C6 NC NC I/O I/O I/O I/O C 7I / OI / OI / OI / OI / OI / O C 8I / OI / OI / OI / OI / OI / O C 9I / OI / OI / OI / OI / OI / O C 1 0 I / OI / OI / OI / OI / OI / O C11 I/O I/O I/O I/O I/O I/O C 1 2 I / OI / OI / OI / OI / OI / O C 1 3 I / OI / OI / OI / OI / OI / O C 1 4 I / OI / OI / OI / OI / OI / O C 1 5 I / OI / OI / OI / OI / OI / O C 1 6 I / OI / OI / OI / OI / OI / O 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-25 C 1 7 I / OI / OI / OI / OI / OI / O C 1 8 I / OI / OI / OI / OI / OI / O C 1 9 I / OI / OI / OI / OI / OI / O C 2 0 I / OI / OI / OI / OI / OI / O C21 NC NC I/O I/O I/O I/O C22 NC NC I/O I/O I/O I/O C23 NC NC I/O I/O I/O I/O C24 V DDP VDDP VDDP VDDP VDDP VDDP C 2 5 N CN CN CI / OI / OI / O C 2 6 N CN CN CI / OI / OI / O D1 NC NC NC I/O I/O I/O D2 NC NC NC I/O I/O I/O D3 NC I/O I/O I/O I/O I/O D4 V DDP VDDP VDDP VDDP VDDP VDDP D5 NC NC I/O I/O I/O I/O D6 NC NC I/O I/O I/O I/O D 7 I / OI / OI / OI / OI / OI / O D 8 I / OI / OI / OI / OI / OI / O D 9 I / OI / OI / OI / OI / OI / O D10 I/O I/O I/O I/O I/O I/O D11 I/O I/O I/O I/O I/O I/O D12 I/O I/O I/O I/O I/O I/O D13 I/O I/O I/O I/O I/O I/O D14 I/O I/O I/O I/O I/O I/O D15 I/O I/O I/O I/O I/O I/O D16 I/O I/O I/O I/O I/O I/O D17 I/O I/O I/O I/O I/O I/O D18 I/O I/O I/O I/O I/O I/O D19 I/O I/O I/O I/O I/O I/O D20 I/O I/O I/O I/O I/O I/O D21 I/O I/O I/O I/O I/O I/O D22 NC NC I/O I/O I/O I/O D23 V DDP VDDP VDDP VDDP VDDP VDDP D24 NC I/O I/O I/O I/O I/O 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-26 v5.7 D 2 5 N CN CN CI / OI / OI / O D 2 6 N CN CN CI / OI / OI / O E 1N CI / OI / OI / OI / OI / O E 2N CI / OI / OI / OI / OI / O E 3N CI / OI / OI / OI / OI / O E 4N CI / OI / OI / OI / OI / O E5 V DD VDD VDD VDD VDD VDD E6 V DD VDD VDD VDD VDD VDD E7 V DD VDD VDD VDD VDD VDD E8 V DD VDD VDD VDD VDD VDD E 9I / OI / OI / OI / OI / OI / O E 1 0 I / OI / OI / OI / OI / OI / O E 1 1 I / OI / OI / OI / OI / OI / O E 1 2 I / OI / OI / OI / OI / OI / O E 1 3 I / OI / OI / OI / OI / OI / O E 1 4 I / OI / OI / OI / OI / OI / O E 1 5 I / OI / OI / OI / OI / OI / O E 1 6 I / OI / OI / OI / OI / OI / O E 1 7 I / OI / OI / OI / OI / OI / O E 1 8 I / OI / OI / OI / OI / OI / O E 1 9 I / OI / OI / OI / OI / OI / O E20 V DD VDD VDD VDD VDD VDD E21 V DD VDD VDD VDD VDD VDD E22 V DD VDD VDD VDD VDD VDD E23 NC I/O I/O I/O I/O I/O E24 NC I/O I/O I/O I/O I/O E25 NC I/O I/O I/O I/O I/O E26 NC I/O I/O I/O I/O I/O F 1N CI / OI / OI / OI / OI / O F 2N CI / OI / OI / OI / OI / O F 3N CI / OI / OI / OI / OI / O F 4N CI / OI / OI / OI / OI / O F5 V DD VDD VDD VDD VDD VDD F22 V DD VDD VDD VDD VDD VDD 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-27 F23 NC I/O I/O I/O I/O I/O F24 NC I/O I/O I/O I/O I/O F25 NC I/O I/O I/O I/O I/O F26 NC I/O I/O I/O I/O I/O G1 I/O I/O I/O I/O I/O I/O G2 I/O I/O I/O I/O I/O I/O G3 NC I/O I/O I/O I/O I/O G4 NC I/O I/O I/O I/O I/O G5 V DD VDD VDD VDD VDD VDD G22 V DD VDD VDD VDD VDD VDD G23 NC I/O I/O I/O I/O I/O G24 NC I/O I/O I/O I/O I/O G25 NC I/O I/O I/O I/O I/O G26 I/O I/O I/O I/O I/O I/O H 1I / OI / OI / OI / OI / OI / O H 2 I / OI / OI / OI / OI / OI / O H 3I / OI / OI / OI / OI / OI / O H 4I / OI / OI / OI / OI / OI / O H5 V DD VDD VDD VDD VDD VDD H22 V DD VDD VDD VDD VDD VDD H23 I/O I/O I/O I/O I/O I/O H24 I/O I/O I/O I/O I/O I/O H25 I/O I/O I/O I/O I/O I/O H26 I/O I/O I/O I/O I/O I/O J 1 I / OI / OI / OI / OI / OI / O J 2 I / OI / OI / OI / OI / OI / O J 3 I / OI / OI / OI / OI / OI / O J 4 I / OI / OI / OI / OI / OI / O J 5 I / OI / OI / OI / OI / OI / O J22 I/O I/O I/O I/O I/O I/O J23 I/O I/O I/O I/O I/O I/O J24 I/O I/O I/O I/O I/O I/O J25 I/O I/O I/O I/O I/O I/O J26 I/O I/O I/O I/O I/O I/O 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-28 v5.7 K 1I / OI / OI / OI / OI / OI / O K 2I / OI / OI / OI / OI / OI / O K 3I / OI / OI / OI / OI / OI / O K 4I / OI / OI / OI / OI / OI / O K 5I / OI / OI / OI / OI / OI / O K22 I/O I/O I/O I/O I/O I/O K23 I/O I/O I/O I/O I/O I/O K24 I/O I/O I/O I/O I/O I/O K25 I/O I/O I/O I/O I/O I/O K26 I/O I/O I/O I/O I/O I/O L 1I / OI / OI / OI / OI / OI / O L 2I / OI / OI / OI / OI / OI / O L 3I / OI / OI / OI / OI / OI / O L 4I / OI / OI / OI / OI / OI / O L 5I / OI / OI / OI / OI / OI / O L11 GND GND GND GND GND GND L12 GND GND GND GND GND GND L13 GND GND GND GND GND GND L14 GND GND GND GND GND GND L15 GND GND GND GND GND GND L16 GND GND GND GND GND GND L 2 2 I / OI / OI / OI / OI / OI / O L23 I/O I/O I/O I/O I/O I/O L24 I/O I/O I/O I/O I/O I/O L25 I/O I/O I/O I/O I/O I/O L26 I/O I/O I/O I/O I/O I/O M1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 M2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 M 3I / OI / OI / OI / OI / OI / O M 4I / OI / OI / OI / OI / OI / O M 5I / OI / OI / OI / OI / OI / O M11 GND GND GND GND GND GND M12 GND GND GND GND GND GND M13 GND GND GND GND GND GND 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-29 M14 GND GND GND GND GND GND M15 GND GND GND GND GND GND M16 GND GND GND GND GND GND M22 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 M 2 3 I / OI / OI / OI / OI / OI / O M 2 4 I / OI / OI / OI / OI / OI / O M 2 5 I / OI / OI / OI / OI / OI / O M 2 6 I / OI / OI / OI / OI / OI / O N 1I / OI / OI / OI / OI / OI / O N2 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 N3 AGND AGND AGND AGND AGND AGND N4 PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input N5 AVDD AVDD AVDD AVDD AVDD AVDD N11 GND GND GND GND GND GND N12 GND GND GND GND GND GND N13 GND GND GND GND GND GND N14 GND GND GND GND GND GND N15 GND GND GND GND GND GND N16 GND GND GND GND GND GND N22 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 N23 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 N 2 4 A V D DA V D DA V D DA V D DA V D DA V D D N25 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 N26 AGND AGND AGND AGND AGND AGND P 1I / OI / OI / OI / OI / OI / O P 2I / OI / OI / OI / OI / OI / O P 3I / OI / OI / OI / OI / OI / O P 4I / OI / OI / OI / OI / OI / O P5 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 P11 GND GND GND GND GND GND P12 GND GND GND GND GND GND P13 GND GND GND GND GND GND P14 GND GND GND GND GND GND P15 GND GND GND GND GND GND 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-30 v5.7 P16 GND GND GND GND GND GND P 2 2 I / OI / OI / OI / OI / OI / O P 2 3 I / OI / OI / OI / OI / OI / O P 2 4 I / OI / OI / OI / OI / OI / O P 2 5 I / OI / OI / OI / OI / OI / O P26 PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input R 1I / OI / OI / OI / OI / OI / O R 2I / OI / OI / OI / OI / OI / O R 3I / OI / OI / OI / OI / OI / O R 4I / OI / OI / OI / OI / OI / O R 5I / OI / OI / OI / OI / OI / O R11 GND GND GND GND GND GND R12 GND GND GND GND GND GND R13 GND GND GND GND GND GND R14 GND GND GND GND GND GND R15 GND GND GND GND GND GND R16 GND GND GND GND GND GND R 2 2 I / OI / OI / OI / OI / OI / O R23 I/O I/O I/O I/O I/O I/O R24 I/O I/O I/O I/O I/O I/O R25 I/O I/O I/O I/O I/O I/O R26 I/O I/O I/O I/O I/O I/O T 1I / OI / OI / OI / OI / OI / O T 2I / OI / OI / OI / OI / OI / O T 3I / OI / OI / OI / OI / OI / O T 4I / OI / OI / OI / OI / OI / O T 5I / OI / OI / OI / OI / OI / O T11 GND GND GND GND GND GND T12 GND GND GND GND GND GND T13 GND GND GND GND GND GND T14 GND GND GND GND GND GND T15 GND GND GND GND GND GND T16 GND GND GND GND GND GND T 2 2 I / OI / OI / OI / OI / OI / O 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-31 T 2 3 I / OI / OI / OI / OI / OI / O T 2 4 I / OI / OI / OI / OI / OI / O T 2 5 I / OI / OI / OI / OI / OI / O T 2 6 I / OI / OI / OI / OI / OI / O U 1 I / OI / OI / OI / OI / OI / O U 2 I / OI / OI / OI / OI / OI / O U 3I / OI / OI / OI / OI / OI / O U 4 I / OI / OI / OI / OI / OI / O U 5 I / OI / OI / OI / OI / OI / O U22 I/O I/O I/O I/O I/O I/O U23 I/O I/O I/O I/O I/O I/O U24 I/O I/O I/O I/O I/O I/O U25 I/O I/O I/O I/O I/O I/O U26 I/O I/O I/O I/O I/O I/O V 1I / OI / OI / OI / OI / OI / O V 2I / OI / OI / OI / OI / OI / O V 3I / OI / OI / OI / OI / OI / O V 4I / OI / OI / OI / OI / OI / O V 5I / OI / OI / OI / OI / OI / O V22 I/O I/O I/O I/O I/O I/O V23 I/O I/O I/O I/O I/O I/O V24 I/O I/O I/O I/O I/O I/O V25 I/O I/O I/O I/O I/O I/O V26 I/O I/O I/O I/O I/O I/O W 1 I / OI / OI / OI / OI / OI / O W 2 I / OI / OI / OI / OI / OI / O W 3 I / OI / OI / OI / OI / OI / O W 4 I / OI / OI / OI / OI / OI / O W5 V DD VDD VDD VDD VDD VDD W22 V DD VDD VDD VDD VDD VDD W23 I/O I/O I/O I/O I/O I/O W24 I/O I/O I/O I/O I/O I/O W25 I/O I/O I/O I/O I/O I/O W26 I/O I/O I/O I/O I/O I/O 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-32 v5.7 Y 1I / OI / OI / OI / OI / OI / O Y 2I / OI / OI / OI / OI / OI / O Y 3I / OI / OI / OI / OI / OI / O Y 4 N CI / OI / OI / OI / OI / O Y5 V DD VDD VDD VDD VDD VDD Y22 V DD VDD VDD VDD VDD VDD Y23 NC I/O I/O I/O I/O I/O Y24 NC I/O I/O I/O I/O I/O Y25 NC I/O I/O I/O I/O I/O Y26 NC I/O I/O I/O I/O I/O A A 1 I / OI / OI / OI / OI / OI / O AA2 NC I/O I/O I/O I/O I/O AA3 NC I/O I/O I/O I/O I/O AA4 NC I/O I/O I/O I/O I/O AA5 V DD VDD VDD VDD VDD VDD AA22 V DD VDD VDD VDD VDD VDD AA23 NC I/O I/O I/O I/O I/O AA24 NC I/O I/O I/O I/O I/O AA25 NC I/O I/O I/O I/O I/O AA26 NC I/O I/O I/O I/O I/O AB1 NC I/O I/O I/O I/O I/O AB2 NC I/O I/O I/O I/O I/O AB3 NC I/O I/O I/O I/O I/O AB4 NC I/O I/O I/O I/O I/O AB5 V DD VDD VDD VDD VDD VDD AB6 V DD VDD VDD VDD VDD VDD AB7 V DD VDD VDD VDD VDD VDD A B 8 I / OI / OI / OI / OI / OI / O A B 9 I / OI / OI / OI / OI / OI / O A B 1 0 I / OI / OI / OI / OI / OI / O A B 1 1 I / OI / OI / OI / OI / OI / O A B 1 2 I / OI / OI / OI / OI / OI / O A B 1 3 I / OI / OI / OI / OI / OI / O A B 1 4 I / OI / OI / OI / OI / OI / O 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-33 A B 1 5 I / OI / OI / OI / OI / OI / O A B 1 6 I / OI / OI / OI / OI / OI / O A B 1 7 I / OI / OI / OI / OI / OI / O A B 1 8 I / OI / OI / OI / OI / OI / O A B 1 9 I / OI / OI / OI / OI / OI / O AB20 V DD VDD VDD VDD VDD VDD AB21 V DD VDD VDD VDD VDD VDD AB22 V DD VDD VDD VDD VDD VDD AB23 NC I/O I/O I/O I/O I/O AB24 NC I/O I/O I/O I/O I/O AB25 NC I/O I/O I/O I/O I/O AB26 NC NC NC I/O I/O I/O AC1 NC I/O I/O I/O I/O I/O AC2 NC I/O I/O I/O I/O I/O AC3 NC I/O I/O I/O I/O I/O AC4 V DDP VDDP VDDP VDDP VDDP VDDP AC5 NC NC I/O I/O I/O I/O A C 6 I / OI / OI / OI / OI / OI / O A C 7 I / OI / OI / OI / OI / OI / O A C 8 I / OI / OI / OI / OI / OI / O A C 9 I / OI / OI / OI / OI / OI / O AC10 I/O I/O I/O I/O I/O I/O AC11 I/O I/O I/O I/O I/O I/O AC12 I/O I/O I/O I/O I/O I/O AC13 I/O I/O I/O I/O I/O I/O AC14 I/O I/O I/O I/O I/O I/O AC15 I/O I/O I/O I/O I/O I/O AC16 I/O I/O I/O I/O I/O I/O AC17 I/O I/O I/O I/O I/O I/O AC18 I/O I/O I/O I/O I/O I/O AC19 I/O I/O I/O I/O I/O I/O AC20 I/O I/O I/O I/O I/O I/O AC21 TMS TMS TMS TMS TMS TMS AC22 TDO TDO TDO TDO TDO TDO 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-34 v5.7 AC23 V DDP VDDP VDDP VDDP VDDP VDDP AC24 RCK RCK RCK RCK RCK RCK AC25 NC NC I/O I/O I/O I/O AC26 NC I/O I/O I/O I/O I/O AD1 NC NC NC I/O I/O I/O AD2 NC I/O I/O I/O I/O I/O AD3 V DDP VDDP VDDP VDDP VDDP VDDP AD4 NC NC I/O I/O I/O I/O AD5 NC NC I/O I/O I/O I/O AD6 NC NC I/O I/O I/O I/O A D 7 I / OI / OI / OI / OI / OI / O A D 8 I / OI / OI / OI / OI / OI / O A D 9 I / OI / OI / OI / OI / OI / O AD10 I/O I/O I/O I/O I/O I/O AD11 I/O I/O I/O I/O I/O I/O AD12 I/O I/O I/O I/O I/O I/O AD13 I/O I/O I/O I/O I/O I/O AD14 I/O I/O I/O I/O I/O I/O AD15 I/O I/O I/O I/O I/O I/O AD16 I/O I/O I/O I/O I/O I/O AD17 I/O I/O I/O I/O I/O I/O AD18 I/O I/O I/O I/O I/O I/O AD19 I/O I/O I/O I/O I/O I/O AD20 NC NC I/O I/O I/O I/O AD21 TCK TCK TCK TCK TCK TCK AD22 V PP VPP VPP VPP VPP VPP A D 2 3 N CN CN CI / OI / OI / O AD24 V DDP VDDP VDDP VDDP VDDP VDDP AD25 NC NC I/O I/O I/O I/O AD26 NC NC I/O I/O I/O I/O AE1 V DDP VDDP VDDP VDDP VDDP VDDP AE2 V DDP VDDP VDDP VDDP VDDP VDDP AE3 NC NC I/O I/O I/O I/O AE4 NC NC I/O I/O I/O I/O 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-35 AE5 NC NC I/O I/O I/O I/O AE6 NC NC I/O I/O I/O I/O AE7 NC NC I/O I/O I/O I/O AE8 I/O I/O I/O I/O I/O I/O AE9 I/O I/O I/O I/O I/O I/O A E 1 0 I / OI / OI / OI / OI / OI / O A E 1 1 I / OI / OI / OI / OI / OI / O A E 1 2 I / OI / OI / OI / OI / OI / O A E 1 3 I / OI / OI / OI / OI / OI / O A E 1 4 I / OI / OI / OI / OI / OI / O A E 1 5 I / OI / OI / OI / OI / OI / O A E 1 6 I / OI / OI / OI / OI / OI / O A E 1 7 I / OI / OI / OI / OI / OI / O A E 1 8 I / OI / OI / OI / OI / OI / O A E 1 9 I / OI / OI / OI / OI / OI / O AE20 NC NC I/O I/O I/O I/O AE21 NC NC I/O I/O I/O I/O AE22 NC NC I/O I/O I/O I/O AE23 V PN VPN VPN VPN VPN VPN AE24 TRST TRST TRST TRST TRST TRST AE25 V DDP VDDP VDDP VDDP VDDP VDDP AE26 V DDP VDDP VDDP VDDP VDDP VDDP AF1 V DDP VDDP VDDP VDDP VDDP VDDP AF2 V DDP VDDP VDDP VDDP VDDP VDDP AF3 NC NC I/O I/O I/O I/O AF4 NC NC I/O I/O I/O I/O AF5 NC NC I/O I/O I/O I/O AF6 NC NC I/O I/O I/O I/O AF7 NC NC I/O I/O I/O I/O A F 8 N CN CN CI / OI / OI / O A F 9 I / OI / OI / OI / OI / OI / O A F 1 0 I / OI / OI / OI / OI / OI / O A F 1 1 I / OI / OI / OI / OI / OI / O A F 1 2 I / OI / OI / OI / OI / OI / O 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-36 v5.7 A F 1 3 I / OI / OI / OI / OI / OI / O A F 1 4 I / OI / OI / OI / OI / OI / O A F 1 5 I / OI / OI / OI / OI / OI / O A F 1 6 I / OI / OI / OI / OI / OI / O A F 1 7 I / OI / OI / OI / OI / OI / O AF18 NC NC I/O I/O I/O I/O AF19 NC NC I/O I/O I/O I/O AF20 NC NC I/O I/O I/O I/O AF21 NC NC I/O I/O I/O I/O AF22 NC NC I/O I/O I/O I/O AF23 TDI TDI TDI TDI TDI TDI AF24 NC NC I/O I/O I/O I/O AF25 V DDP VDDP VDDP VDDP VDDP VDDP AF26 V DDP VDDP VDDP VDDP VDDP VDDP 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-37 144-Pin FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. 123456789101112 A B C D E F G H J K L M A1 Ball Pad Corner

ProASICPLUS Flash Family FPGAs 2-38 v5.7 144-FBGA Pin Pin Number APA075 Function APA150 Function APA300 Function APA450 Function A1 I/O I/O I/O I/O A2 I/O I/O I/O I/O A3 I/O I/O I/O I/O A4 I/O I/O I/O I/O A5 I/O I/O I/O I/O A6 GND GND GND GND A7 I/O I/O I/O I/O A8 V DD VDD VDD VDD A9 I/O I/O I/O I/O A10 I/O I/O I/O I/O A11 I/O I/O I/O I/O A12 I/O I/O I/O I/O B1 I/O I/O I/O I/O B 2 G N DG N DG N DG N D B3 I/O I/O I/O I/O B4 I/O I/O I/O I/O B5 I/O I/O I/O I/O B6 I/O I/O I/O I/O B7 I/O I/O I/O I/O B8 I/O I/O I/O I/O B9 I/O I/O I/O I/O B10 I/O I/O I/O I/O B 1 1 G N DG N DG N DG N D B12 I/O I/O I/O I/O C1 I/O I/O I/O I/O C2 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 C3 I/O I/O I/O I/O C4 V DD VDD VDD VDD C5 I/O I/O I/O I/O C6 I/O I/O I/O I/O C7 I/O I/O I/O I/O C8 I/O I/O I/O I/O C9 I/O I/O I/O I/O C10 I/O I/O I/O I/O C11 I/O I/O I/O I/O C12 I/O I/O I/O I/O D1 I/O I/O I/O I/O D2 I/O I/O I/O I/O D3 I/O I/O I/O I/O D4 I/O I/O I/O I/O D5 I/O I/O I/O I/O D6 I/O I/O I/O I/O D7 I/O I/O I/O I/O D8 I/O I/O I/O I/O D9 I/O I/O I/O I/O D10 I/O I/O I/O I/O D11 I/O I/O I/O I/O D12 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 E1 V DD VDD VDD VDD E2 I/O I/O I/O I/O E3 I/O I/O I/O I/O E4 V DDP VDDP VDDP VDDP E5 I/O I/O I/O I/O E6 V DDP VDDP VDDP VDDP E7 V DDP VDDP VDDP VDDP E8 AVDD AVDD AVDD AVDD E9 V DDP VDDP VDDP VDDP E10 V DD VDD VDD VDD E11 NPECL2 NPECL2 NPECL2 NPECL2 E12 AGND AGND AGND AGND F1 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 F2 AGND AGND AGND AGND F3 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 F4 I/O I/O I/O I/O F5 GND GND GND GND F6 GND GND GND GND F7 GND GND GND GND F8 I/O I/O I/O I/O F9 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 F10 GND GND GND GND F11 PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input F12 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 144-FBGA Pin Pin Number APA075 Function APA150 Function APA300 Function APA450 Function

ProASICPLUS Flash Family FPGAs v5.7 2-39 G1 PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input G2 GND GND GND GND G3 AVDD AVDD AVDD AVDD G4 NPECL1 NPECL1 NPECL1 NPECL1 G5 GND GND GND GND G6 GND GND GND GND G7 GND GND GND GND G8 I/O I/O I/O I/O G9 I/O I/O I/O I/O G10 I/O I/O I/O I/O G11 I/O I/O I/O I/O G12 I/O I/O I/O I/O H1 V DD VDD VDD VDD H2 I/O I/O I/O I/O H3 I/O I/O I/O I/O H4 I/O I/O I/O I/O H5 V DD VDD VDD VDD H6 I/O I/O I/O I/O H7 I/O I/O I/O I/O H8 I/O I/O I/O I/O H9 I/O I/O I/O I/O H10 V DDP VDDP VDDP VDDP H11 I/O I/O I/O I/O H12 V DD VDD VDD VDD J1 I/O I/O I/O I/O J2 I/O I/O I/O I/O J3 V DDP VDDP VDDP VDDP J4 I/O I/O I/O I/O J5 I/O I/O I/O I/O J6 I/O I/O I/O I/O J7 V DD VDD VDD VDD J8 TCK TCK TCK TCK J9 I/O I/O I/O I/O J10 TDO TDO TDO TDO J11 I/O I/O I/O I/O J12 I/O I/O I/O I/O 144-FBGA Pin Pin Number APA075 Function APA150 Function APA300 Function APA450 Function K1 I/O I/O I/O I/O K2 I/O I/O I/O I/O K3 I/O I/O I/O I/O K4 I/O I/O I/O I/O K5 I/O I/O I/O I/O K6 I/O I/O I/O I/O K7 GND GND GND GND K8 I/O I/O I/O I/O K9 I/O I/O I/O I/O K10 GND GND GND GND K11 I/O I/O I/O I/O K12 I/O I/O I/O I/O L1 GND GND GND GND L2 I/O I/O I/O I/O L3 I/O I/O I/O I/O L4 I/O I/O I/O I/O L5 V DDP VDDP VDDP VDDP L6 I/O I/O I/O I/O L7 I/O I/O I/O I/O L8 I/O I/O I/O I/O L 9 T M ST M ST M ST M S L10 RCK RCK RCK RCK L11 I/O I/O I/O I/O L12 TRST TRST TRST TRST M1 I/O I/O I/O I/O M2 I/O I/O I/O I/O M3 I/O I/O I/O I/O M4 I/O I/O I/O I/O M5 I/O I/O I/O I/O M6 I/O I/O I/O I/O M7 I/O I/O I/O I/O M8 I/O I/O I/O I/O M9 TDI TDI TDI TDI M10 V DDP VDDP VDDP VDDP M11 V PP VPP VPP VPP M12 V PN VPN VPN VPN 144-FBGA Pin Pin Number APA075 Function APA150 Function APA300 Function APA450 Function

ProASICPLUS Flash Family FPGAs 2-40 v5.7 256-Pin FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner 13579111315 246810121416 C E G J L N R D F H K M P T B A

ProASICPLUS Flash Family FPGAs v5.7 2-41 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function A1 GND GND GND GND A2 I/O I/O I/O I/O A3 I/O I/O I/O I/O A4 I/O I/O I/O I/O A5 I/O I/O I/O I/O A6 I/O I/O I/O I/O A7 I/O I/O I/O I/O A8 I/O I/O I/O I/O A9 I/O I/O I/O I/O A10 I/O I/O I/O I/O A11 I/O I/O I/O I/O A12 I/O I/O I/O I/O A13 I/O I/O I/O I/O A14 I/O I/O I/O I/O A15 I/O I/O I/O I/O A16 GND GND GND GND B1 I/O I/O I/O I/O B2 I/O I/O I/O I/O B3 I/O I/O I/O I/O B4 I/O I/O I/O I/O B5 I/O I/O I/O I/O B6 I/O I/O I/O I/O B7 I/O I/O I/O I/O B8 I/O I/O I/O I/O B9 I/O I/O I/O I/O B10 I/O I/O I/O I/O B11 I/O I/O I/O I/O B12 I/O I/O I/O I/O B13 I/O I/O I/O I/O B14 I/O I/O I/O I/O B15 I/O I/O I/O I/O B16 I/O I/O I/O I/O C1 I/O I/O I/O I/O C2 I/O I/O I/O I/O C3 I/O I/O I/O I/O C4 I/O I/O I/O I/O C5 I/O I/O I/O I/O C6 I/O I/O I/O I/O C7 I/O I/O I/O I/O C8 I/O I/O I/O I/O C9 I/O I/O I/O I/O C10 I/O I/O I/O I/O C11 I/O I/O I/O I/O C12 I/O I/O I/O I/O C13 I/O I/O I/O I/O C14 I/O I/O I/O I/O C15 I/O I/O I/O I/O C16 I/O I/O I/O I/O D1 I/O I/O I/O I/O D2 I/O I/O I/O I/O D3 I/O I/O I/O I/O D4 I/O I/O I/O I/O D5 I/O I/O I/O I/O D6 I/O I/O I/O I/O D7 I/O I/O I/O I/O D8 I/O I/O I/O I/O D9 I/O I/O I/O I/O D10 I/O I/O I/O I/O D11 I/O I/O I/O I/O D12 I/O I/O I/O I/O D13 I/O I/O I/O I/O D14 I/O I/O I/O I/O D15 I/O I/O I/O I/O D16 I/O I/O I/O I/O E1 I/O I/O I/O I/O E2 I/O I/O I/O I/O E3 I/O I/O I/O I/O E4 I/O I/O I/O I/O E5 I/O I/O I/O I/O E6 V DDP VDDP VDDP VDDP 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function

ProASICPLUS Flash Family FPGAs 2-42 v5.7 E7 V DDP VDDP VDDP VDDP E8 I/O I/O I/O I/O E9 I/O I/O I/O I/O E10 V DDP VDDP VDDP VDDP E11 V DDP VDDP VDDP VDDP E12 I/O I/O I/O I/O E13 I/O I/O I/O I/O E14 I/O I/O I/O I/O E15 I/O I/O I/O I/O E16 I/O I/O I/O I/O F1 I/O I/O I/O I/O F2 I/O I/O I/O I/O F3 I/O I/O I/O I/O F4 I/O I/O I/O I/O F5 V DDP VDDP VDDP VDDP F6 GND GND GND GND F7 V DD VDD VDD VDD F8 V DD VDD VDD VDD F9 V DD VDD VDD VDD F10 V DD VDD VDD VDD F11 GND GND GND GND F12 V DDP VDDP VDDP VDDP F13 I/O I/O I/O I/O F14 I/O I/O I/O I/O F15 I/O I/O I/O I/O F16 I/O I/O I/O I/O G1 I/O I/O I/O I/O G2 I/O I/O I/O I/O G3 I/O I/O I/O I/O G4 I/O I/O I/O I/O G5 V DDP VDDP VDDP VDDP G6 V DD VDD VDD VDD G7 GND GND GND GND G8 GND GND GND GND G9 GND GND GND GND 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function G10 GND GND GND GND G11 V DD VDD VDD VDD G12 V DDP VDDP VDDP VDDP G13 I/O I/O I/O I/O G14 I/O I/O I/O I/O G15 I/O I/O I/O I/O G16 I/O I/O I/O I/O H1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 H2 NPECL1 NPECL1 NPECL1 NPECL1 H3 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 H4 AGND AGND AGND AGND H5 I/O I/O I/O I/O H6 V DD VDD VDD VDD H7 GND GND GND GND H8 GND GND GND GND H9 GND GND GND GND H10 GND GND GND GND H11 V DD VDD VDD VDD H12 I/O I/O I/O I/O H13 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 H14 NPECL2 NPECL2 NPECL2 NPECL2 H15 AGND AGND AGND AGND H16 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 J1 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 J2 PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input J3 AVDD AVDD AVDD AVDD J4 I/O I/O I/O I/O J5 I/O I/O I/O I/O J6 V DD VDD VDD VDD J7 GND GND GND GND J8 GND GND GND GND J9 GND GND GND GND J10 GND GND GND GND J11 V DD VDD VDD VDD 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function

ProASICPLUS Flash Family FPGAs v5.7 2-43 J12 I/O I/O I/O I/O J13 PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input J14 I/O I/O I/O I/O J15 AVDD AVDD AVDD AVDD J16 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 K1 I/O I/O I/O I/O K2 I/O I/O I/O I/O K3 I/O I/O I/O I/O K4 I/O I/O I/O I/O K5 V DDP VDDP VDDP VDDP K6 V DD VDD VDD VDD K7 GND GND GND GND K8 GND GND GND GND K9 GND GND GND GND K10 GND GND GND GND K11 V DD VDD VDD VDD K12 V DDP VDDP VDDP VDDP K13 I/O I/O I/O I/O K14 I/O I/O I/O I/O K15 I/O I/O I/O I/O K16 I/O I/O I/O I/O L1 I/O I/O I/O I/O L2 I/O I/O I/O I/O L3 I/O I/O I/O I/O L4 I/O I/O I/O I/O L5 V DDP VDDP VDDP VDDP L6 GND GND GND GND L7 V DD VDD VDD VDD L8 V DD VDD VDD VDD L9 V DD VDD VDD VDD L10 V DD VDD VDD VDD L11 GND GND GND GND L12 V DDP VDDP VDDP VDDP L13 I/O I/O I/O I/O 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function L14 I/O I/O I/O I/O L15 I/O I/O I/O I/O L16 I/O I/O I/O I/O M1 I/O I/O I/O I/O M2 I/O I/O I/O I/O M3 I/O I/O I/O I/O M4 I/O I/O I/O I/O M5 I/O I/O I/O I/O M6 V DDP VDDP VDDP VDDP M7 V DDP VDDP VDDP VDDP M8 I/O I/O I/O I/O M9 I/O I/O I/O I/O M10 V DDP VDDP VDDP VDDP M11 V DDP VDDP VDDP VDDP M12 I/O I/O I/O I/O M13 I/O I/O I/O I/O M14 I/O I/O I/O I/O M15 I/O I/O I/O I/O M16 I/O I/O I/O I/O N1 I/O I/O I/O I/O N2 I/O I/O I/O I/O N3 I/O I/O I/O I/O N4 I/O I/O I/O I/O N5 I/O I/O I/O I/O N6 I/O I/O I/O I/O N7 I/O I/O I/O I/O N8 I/O I/O I/O I/O N9 I/O I/O I/O I/O N10 I/O I/O I/O I/O N11 I/O I/O I/O I/O N12 I/O I/O I/O I/O N13 I/O I/O I/O I/O N14 RCK RCK RCK RCK N15 I/O I/O I/O I/O N16 I/O I/O I/O I/O 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function

ProASICPLUS Flash Family FPGAs 2-44 v5.7 P1 I/O I/O I/O I/O P2 I/O I/O I/O I/O P3 I/O I/O I/O I/O P4 I/O I/O I/O I/O P5 I/O I/O I/O I/O P6 I/O I/O I/O I/O P7 I/O I/O I/O I/O P8 I/O I/O I/O I/O P9 I/O I/O I/O I/O P10 I/O I/O I/O I/O P11 I/O I/O I/O I/O P12 I/O I/O I/O I/O P13 TCK TCK TCK TCK P14 V PP VPP VPP VPP P15 TRST TRST TRST TRST P16 I/O I/O I/O I/O R1 I/O I/O I/O I/O R2 I/O I/O I/O I/O R3 I/O I/O I/O I/O R4 I/O I/O I/O I/O R5 I/O I/O I/O I/O R6 I/O I/O I/O I/O R7 I/O I/O I/O I/O R8 I/O I/O I/O I/O R9 I/O I/O I/O I/O R10 I/O I/O I/O I/O R11 I/O I/O I/O I/O R12 I/O I/O I/O I/O R13 I/O I/O I/O I/O R14 TDI TDI TDI TDI R15 V PN VPN VPN VPN R16 TDO TDO TDO TDO T1 GND GND GND GND T2 I/O I/O I/O I/O T3 I/O I/O I/O I/O 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function T4 I/O I/O I/O I/O T5 I/O I/O I/O I/O T6 I/O I/O I/O I/O T7 I/O I/O I/O I/O T8 I/O I/O I/O I/O T9 I/O I/O I/O I/O T10 I/O I/O I/O I/O T11 I/O I/O I/O I/O T12 I/O I/O I/O I/O T13 I/O I/O I/O I/O T14 I/O I/O I/O I/O T15 TMS TMS TMS TMS T16 GND GND GND GND 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function

ProASICPLUS Flash Family FPGAs v5.7 2-45 484-Pin FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. 13579111315 246810121422 19 18 17 16 C E G J L N R D F H K M P AB AA Y W V U T B A 21 20 A1 Ball Pad Corner

ProASICPLUS Flash Family FPGAs 2-46 v5.7 484-Pin FBGA Pin Number APA450 Function APA600 Function A1 GND GND A2 GND GND A3 V DDP VDDP A4 I/O I/O A5 I/O I/O A6 I/O I/O A7 I/O I/O A8 I/O I/O A9 I/O I/O A10 I/O I/O A11 I/O I/O A12 I/O I/O A13 I/O I/O A14 I/O I/O A15 I/O I/O A16 I/O I/O A17 I/O I/O A18 I/O I/O A19 I/O I/O A20 V DDP VDDP A21 GND GND A22 GND GND B1 GND GND B2 V DDP VDDP B3 I/O I/O B4 I/O I/O B5 I/O I/O B6 I/O I/O B7 I/O I/O B8 I/O I/O B9 I/O I/O B10 I/O I/O B11 I/O I/O B12 I/O I/O B13 I/O I/O B14 I/O I/O B15 I/O I/O B16 I/O I/O B17 I/O I/O B18 I/O I/O B19 I/O I/O B20 I/O I/O B21 V DDP VDDP B22 GND GND C1 V DDP VDDP C2 NC I/O C3 I/O I/O C4 I/O I/O C5 GND GND C6 I/O I/O C7 I/O I/O C8 V DD VDD C9 V DD VDD C10 I/O I/O C11 I/O I/O C12 NC I/O C13 NC I/O C14 V DD VDD C15 V DD VDD C16 NC I/O C17 I/O I/O C18 GND GND C19 I/O I/O C20 I/O I/O C21 I/O I/O C22 V DDP VDDP D1 I/O I/O D2 I/O I/O D3 NC I/O D4 GND GND D5 I/O I/O D6 I/O I/O 484-Pin FBGA Pin Number APA450 Function APA600 Function D7 I/O I/O D8 I/O I/O D9 I/O I/O D10 I/O I/O D11 I/O I/O D12 I/O I/O D13 I/O I/O D14 I/O I/O D15 I/O I/O D16 I/O I/O D17 I/O I/O D18 I/O I/O D19 GND GND D20 I/O I/O D21 I/O I/O D22 I/O I/O E1 I/O I/O E2 NC I/O E3 GND GND E4 I/O I/O E5 I/O I/O E6 I/O I/O E7 I/O I/O E8 I/O I/O E9 I/O I/O E10 I/O I/O E11 I/O I/O E12 I/O I/O E13 I/O I/O E14 I/O I/O E15 I/O I/O E16 I/O I/O E17 I/O I/O E18 I/O I/O E19 I/O I/O E20 GND GND 484-Pin FBGA Pin Number APA450 Function APA600 Function

ProASICPLUS Flash Family FPGAs v5.7 2-47 E21 I/O I/O E22 I/O I/O F1 I/O I/O F2 I/O I/O F3 I/O I/O F4 I/O I/O F5 I/O I/O F6 I/O I/O F7 I/O I/O F8 I/O I/O F9 I/O I/O F10 I/O I/O F11 I/O I/O F12 I/O I/O F13 I/O I/O F14 I/O I/O F15 I/O I/O F16 I/O I/O F17 I/O I/O F18 I/O I/O F19 I/O I/O F20 I/O I/O F21 I/O I/O F22 NC I/O G1 I/O I/O G2 I/O I/O G3 NC I/O G4 I/O I/O G5 I/O I/O G6 I/O I/O G7 I/O I/O G8 I/O I/O G9 I/O I/O G10 I/O I/O G11 I/O I/O G12 I/O I/O 484-Pin FBGA Pin Number APA450 Function APA600 Function G13 I/O I/O G14 I/O I/O G15 I/O I/O G16 I/O I/O G17 I/O I/O G18 I/O I/O G19 I/O I/O G20 I/O I/O G21 I/O I/O G22 I/O I/O H1 I/O I/O H2 I/O I/O H3 V DD VDD H4 I/O I/O H5 I/O I/O H6 I/O I/O H7 I/O I/O H8 I/O I/O H9 V DDP VDDP H10 V DDP VDDP H11 I/O I/O H12 I/O I/O H13 V DDP VDDP H14 V DDP VDDP H15 I/O I/O H16 I/O I/O H17 I/O I/O H18 I/O I/O H19 I/O I/O H20 V DD VDD H21 I/O I/O H22 I/O I/O J1 I/O I/O J2 I/O I/O J3 NC I/O J4 I/O I/O 484-Pin FBGA Pin Number APA450 Function APA600 Function J5 I/O I/O J6 I/O I/O J7 I/O I/O J8 V DDP VDDP J9 GND GND J10 V DD VDD J11 V DD VDD J12 V DD VDD J13 V DD VDD J14 GND GND J15 V DDP VDDP J16 I/O I/O J17 I/O I/O J18 I/O I/O J19 I/O I/O J20 NC I/O J21 I/O I/O J22 I/O I/O K1 I/O I/O K2 I/O I/O K3 NC I/O K4 I/O I/O K5 I/O I/O K6 I/O I/O K7 I/O I/O K8 V DDP VDDP K9 V DD VDD K10 GND GND K11 GND GND K12 GND GND K13 GND GND K14 V DD VDD K15 V DDP VDDP K16 I/O I/O K17 I/O I/O K18 I/O I/O 484-Pin FBGA Pin Number APA450 Function APA600 Function

ProASICPLUS Flash Family FPGAs 2-48 v5.7 K19 I/O I/O K20 I/O I/O K21 I/O I/O K22 I/O I/O L1 NC I/O L2 I/O I/O L3 I/O I/O L4 I/O / GL1 I/O / GL1 L5 NPECL1 NPECL1 L6 I/O / GLMX1 I/O / GLMX1 L7 AGND AGND L8 I/O I/O L9 V DD VDD L10 GND GND L11 GND GND L12 GND GND L13 GND GND L14 V DD VDD L15 I/O I/O L16 I/O / GLMX2 I/O / GLMX2 L17 NPECL2 NPECL2 L18 AGND AGND L19 I/O / GL4 I/O / GL4 L20 I/O I/O L21 I/O I/O L22 I/O I/O M1 I/O I/O M2 I/O I/O M3 I/O I/O M4 I/O / GL2 I/O / GL2 M5 PPECL1 / Input PPECL1 / Input M6 AVDD AVDD M7 I/O I/O M8 I/O I/O M9 V DD VDD 484-Pin FBGA Pin Number APA450 Function APA600 Function M10 GND GND M11 GND GND M12 GND GND M13 GND GND M14 V DD VDD M15 I/O I/O M16 PPECL2 / Input PPECL2 / Input M17 I/O I/O M18 AVDD AVDD M19 I/O / GL3 I/O / GL3 M20 I/O I/O M21 I/O I/O M22 I/O I/O N1 I/O I/O N2 I/O I/O N3 NC I/O N4 I/O I/O N5 I/O I/O N6 I/O I/O N7 I/O I/O N8 V DDP VDDP N9 V DD VDD N10 GND GND N11 GND GND N12 GND GND N13 GND GND N14 V DD VDD N15 V DDP VDDP N16 I/O I/O N17 I/O I/O N18 I/O I/O N19 I/O I/O N20 NC I/O N21 I/O I/O N22 I/O I/O 484-Pin FBGA Pin Number APA450 Function APA600 Function P1 I/O I/O P2 I/O I/O P3 I/O I/O P4 I/O I/O P5 I/O I/O P6 I/O I/O P7 I/O I/O P8 V DDP VDDP P9 GND GND P10 V DD VDD P11 V DD VDD P12 V DD VDD P13 V DD VDD P14 GND GND P15 V DDP VDDP P16 I/O I/O P17 I/O I/O P18 I/O I/O P19 I/O I/O P20 NC I/O P21 I/O I/O P22 I/O I/O R1 I/O I/O R2 I/O I/O R3 V DD VDD R4 I/O I/O R5 I/O I/O R6 I/O I/O R7 I/O I/O R8 I/O I/O R9 V DDP VDDP R10 V DDP VDDP R11 I/O I/O R12 I/O I/O R13 V DDP VDDP R14 V DDP VDDP 484-Pin FBGA Pin Number APA450 Function APA600 Function

ProASICPLUS Flash Family FPGAs v5.7 2-49 R15 I/O I/O R16 I/O I/O R17 I/O I/O R18 I/O I/O R19 I/O I/O R20 V DD VDD R21 I/O I/O R22 I/O I/O T1 I/O I/O T2 I/O I/O T3 NC I/O T4 I/O I/O T5 I/O I/O T6 I/O I/O T7 I/O I/O T8 I/O I/O T9 I/O I/O T10 I/O I/O T11 I/O I/O T12 I/O I/O T13 I/O I/O T14 I/O I/O T15 I/O I/O T16 I/O I/O T17 RCK RCK T18 I/O I/O T19 I/O I/O T20 NC I/O T21 I/O I/O T22 I/O I/O U1 I/O I/O U2 I/O I/O U3 I/O I/O U4 I/O I/O U5 I/O I/O U6 I/O I/O 484-Pin FBGA Pin Number APA450 Function APA600 Function U7 I/O I/O U8 I/O I/O U9 I/O I/O U10 I/O I/O U11 I/O I/O U12 I/O I/O U13 I/O I/O U14 I/O I/O U15 I/O I/O U16 TCK TCK U17 V PP VPP U18 TRST TRST U19 I/O I/O U20 NC I/O U21 I/O I/O U22 I/O I/O V1 I/O I/O V2 I/O I/O V3 GND GND V4 I/O I/O V5 I/O I/O V6 I/O I/O V7 I/O I/O V8 I/O I/O V9 I/O I/O V10 I/O I/O V11 I/O I/O V12 I/O I/O V13 I/O I/O V14 I/O I/O V15 I/O I/O V16 I/O I/O V17 TDI TDI V18 V PN VPN V19 TDO TDO V20 GND GND 484-Pin FBGA Pin Number APA450 Function APA600 Function V21 NC I/O V22 I/O I/O W1 NC I/O W2 I/O I/O W3 I/O I/O W4 GND GND W5 I/O I/O W6 I/O I/O W7 I/O I/O W8 I/O I/O W9 I/O I/O W10 I/O I/O W11 I/O I/O W12 I/O I/O W13 I/O I/O W14 I/O I/O W15 I/O I/O W16 I/O I/O W17 I/O I/O W18 TMS TMS W19 GND GND W20 NC I/O W21 NC I/O W22 I/O I/O Y1 V DDP VDDP Y2 I/O I/O Y3 I/O I/O Y4 I/O I/O Y5 GND GND Y6 I/O I/O Y7 I/O I/O Y8 V DD VDD Y9 V DD VDD Y10 I/O I/O Y11 I/O I/O Y12 I/O I/O 484-Pin FBGA Pin Number APA450 Function APA600 Function

ProASICPLUS Flash Family FPGAs 2-50 v5.7 Y13 I/O I/O Y14 V DD VDD Y15 V DD VDD Y16 I/O I/O Y17 I/O I/O Y18 GND GND Y19 I/O I/O Y20 I/O I/O Y21 NC I/O Y22 V DDP VDDP AA1 GND GND AA2 V DDP VDDP AA3 I/O I/O AA4 I/O I/O AA5 I/O I/O AA6 I/O I/O AA7 I/O I/O AA8 I/O I/O AA9 I/O I/O AA10 I/O I/O AA11 I/O I/O AA12 I/O I/O AA13 I/O I/O AA14 I/O I/O AA15 I/O I/O AA16 I/O I/O AA17 I/O I/O AA18 NC I/O AA19 NC I/O AA20 I/O I/O AA21 V DDP VDDP AA22 GND GND AB1 GND GND AB2 GND GND AB3 V DDP VDDP AB4 I/O I/O 484-Pin FBGA Pin Number APA450 Function APA600 Function AB5 I/O I/O AB6 I/O I/O AB7 I/O I/O AB8 I/O I/O AB9 I/O I/O AB10 I/O I/O AB11 I/O I/O AB12 I/O I/O AB13 I/O I/O AB14 I/O I/O AB15 I/O I/O AB16 I/O I/O AB17 I/O I/O AB18 NC I/O AB19 I/O I/O AB20 V DDP VDDP AB21 GND GND AB22 GND GND 484-Pin FBGA Pin Number APA450 Function APA600 Function

ProASICPLUS Flash Family FPGAs v5.7 2-51 676-Pin FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. 12356789101115 14 13 121617181920212223 4242526 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF A1 Ball Pad Corner

ProASICPLUS Flash Family FPGAs 2-52 v5.7 676-Pin FBGA Pin Number APA600 Function APA750 Function A1 GND GND A2 GND GND A3 I/O I/O A4 I/O I/O A5 I/O I/O A6 I/O I/O A7 I/O I/O A8 I/O I/O A9 I/O I/O A10 I/O I/O A11 I/O I/O A12 I/O I/O A13 I/O I/O A14 I/O I/O A15 I/O I/O A16 I/O I/O A17 I/O I/O A18 I/O I/O A19 I/O I/O A20 I/O I/O A21 I/O I/O A22 I/O I/O A23 I/O I/O A24 I/O I/O A25 GND GND A26 GND GND B1 GND GND B2 GND GND B3 GND GND B4 GND GND B5 I/O I/O B6 I/O I/O B7 I/O I/O B8 I/O I/O B9 I/O I/O B10 I/O I/O B11 I/O I/O B12 I/O I/O B13 I/O I/O B14 I/O I/O B15 I/O I/O B16 I/O I/O B17 I/O I/O B18 I/O I/O B19 I/O I/O B20 I/O I/O B21 I/O I/O B22 I/O I/O B23 I/O I/O B24 I/O I/O B25 GND GND B26 GND GND C1 GND GND C2 GND GND C3 GND GND C4 GND GND C5 I/O I/O C6 I/O I/O C7 I/O I/O C8 I/O I/O C9 I/O I/O C10 I/O I/O C11 I/O I/O C12 I/O I/O C13 I/O I/O C14 I/O I/O C15 I/O I/O C16 I/O I/O C17 I/O I/O C18 I/O I/O 676-Pin FBGA Pin Number APA600 Function APA750 Function C19 I/O I/O C20 I/O I/O C21 I/O I/O C22 I/O I/O C23 I/O I/O C24 I/O I/O C25 I/O I/O C26 I/O I/O D1 I/O I/O D2 I/O I/O D3 GND GND D4 I/O I/O D5 I/O I/O D6 I/O I/O D7 I/O I/O D8 I/O I/O D9 I/O I/O D10 I/O I/O D11 I/O I/O D12 I/O I/O D13 I/O I/O D14 I/O I/O D15 I/O I/O D16 I/O I/O D17 I/O I/O D18 I/O I/O D19 I/O I/O D20 I/O I/O D21 I/O I/O D22 I/O I/O D23 I/O I/O D24 I/O I/O D25 I/O I/O D26 I/O I/O E1 I/O I/O 676-Pin FBGA Pin Number APA600 Function APA750 Function

ProASICPLUS Flash Family FPGAs v5.7 2-53 E2 I/O I/O E3 I/O I/O E4 I/O I/O E5 I/O I/O E6 I/O I/O E7 I/O I/O E8 I/O I/O E9 I/O I/O E10 I/O I/O E11 I/O I/O E12 I/O I/O E13 I/O I/O E14 I/O I/O E15 I/O I/O E16 I/O I/O E17 I/O I/O E18 I/O I/O E19 I/O I/O E20 I/O I/O E21 I/O I/O E22 I/O I/O E23 I/O I/O E24 I/O I/O E25 I/O I/O E26 I/O I/O F1 I/O I/O F2 I/O I/O F3 I/O I/O F4 I/O I/O F5 GND GND F6 I/O I/O F7 NC NC F8 I/O I/O F9 I/O I/O F10 I/O I/O 676-Pin FBGA Pin Number APA600 Function APA750 Function F11 I/O I/O F12 I/O I/O F13 I/O I/O F14 I/O I/O F15 I/O I/O F16 I/O I/O F17 I/O I/O F18 I/O I/O F19 I/O I/O F20 I/O I/O F21 I/O I/O F22 I/O I/O F23 I/O I/O F24 I/O I/O F25 I/O I/O F26 I/O I/O G1 I/O I/O G2 I/O I/O G3 I/O I/O G4 I/O I/O G5 I/O I/O G6 I/O I/O G7 I/O I/O G8 V DD VDD G9 NC NC G10 I/O I/O G11 NC NC G12 I/O I/O G13 NC NC G14 I/O I/O G15 NC NC G16 I/O I/O G17 NC NC G18 I/O I/O G19 V DDP VDDP 676-Pin FBGA Pin Number APA600 Function APA750 Function G20 NC NC G21 I/O I/O G22 I/O I/O G23 I/O I/O G24 I/O I/O G25 I/O I/O G26 I/O I/O H1 I/O I/O H2 I/O I/O H3 I/O I/O H4 I/O I/O H5 I/O I/O H6 I/O I/O H7 V DDP VDDP H8 V DD VDD H9 V DDP VDDP H10 V DDP VDDP H11 V DDP VDDP H12 V DDP VDDP H13 V DDP VDDP H14 V DDP VDDP H15 V DDP VDDP H16 V DDP VDDP H17 V DDP VDDP H18 V DDP VDDP H19 V DD VDD H20 V DD VDD H21 I/O I/O H22 I/O I/O H23 I/O I/O H24 I/O I/O H25 I/O I/O H26 I/O I/O J1 I/O I/O J2 I/O I/O 676-Pin FBGA Pin Number APA600 Function APA750 Function

ProASICPLUS Flash Family FPGAs 2-54 v5.7 J3 I/O I/O J4 I/O I/O J5 I/O I/O J6 I/O I/O J7 NC NC J8 V DDP VDDP J9 V DD VDD J10 V DD VDD J11 V DD VDD J12 V DD VDD J13 V DD VDD J14 V DD VDD J15 V DD VDD J16 V DD VDD J17 V DD VDD J18 V DD VDD J19 V DDP VDDP J20 NC NC J21 I/O I/O J22 I/O I/O J23 I/O I/O J24 I/O I/O J25 I/O I/O J26 I/O I/O K1 I/O I/O K2 I/O I/O K3 I/O I/O K4 I/O I/O K5 I/O I/O K6 I/O I/O K7 I/O I/O K8 V DDP VDDP K9 V DD VDD K10 GND GND K11 GND GND 676-Pin FBGA Pin Number APA600 Function APA750 Function K12 GND GND K13 GND GND K14 GND GND K15 GND GND K16 GND GND K17 GND GND K18 V DD VDD K19 V DDP VDDP K20 I/O I/O K21 I/O I/O K22 I/O I/O K23 I/O I/O K24 I/O I/O K25 I/O I/O K26 I/O I/O L1 I/O I/O L2 I/O I/O L3 I/O I/O L4 I/O I/O L5 I/O I/O L6 I/O I/O L7 NC NC L8 V DDP VDDP L9 V DD VDD L10 GND GND L11 GND GND L12 GND GND L13 GND GND L14 GND GND L15 GND GND L16 GND GND L17 GND GND L18 V DD VDD L19 V DDP VDDP L20 NC NC 676-Pin FBGA Pin Number APA600 Function APA750 Function L21 I/O I/O L22 I/O I/O L23 I/O I/O L24 I/O I/O L25 I/O I/O L26 I/O I/O M1 I/O I/O M2 I/O I/O M3 I/O I/O M4 I/O I/O M5 I/O I/O M6 I/O I/O M7 I/O I/O M8 V DDP VDDP M9 V DD VDD M10 GND GND M11 GND GND M12 GND GND M13 GND GND M14 GND GND M15 GND GND M16 GND GND M17 GND GND M18 V DD VDD M19 V DDP VDDP M20 I/O I/O M21 I/O I/O M22 I/O I/O M23 I/O I/O M24 I/O I/O M25 I/O I/O M26 I/O I/O N1 I/O / GL1 I/O / GL1 N2 AGND AGND N3 I/O / GLMX1 I/O / GLMX1 676-Pin FBGA Pin Number APA600 Function APA750 Function

ProASICPLUS Flash Family FPGAs v5.7 2-55 N4 I/O I/O N5 NPECL1 NPECL1 N6 I/O I/O N7 NC NC N8 V DDP VDDP N9 V DD VDD N10 GND GND N11 GND GND N12 GND GND N13 GND GND N14 GND GND N15 GND GND N16 GND GND N17 GND GND N18 V DD VDD N19 V DDP VDDP N20 NC NC N21 I/O I/O N22 I/O / GL3 I/O / GL3 N23 I/O I/O N24 NPECL2 NPECL2 N25 I/O / GL4 I/O / GL4 N26 I/O I/O P1 I/O / GL2 I/O / GL2 P2 AVDD AVDD P3 I/O I/O P4 I/O I/O P5 PPECL1 / Input PPECL1 / Input P6 I/O I/O P7 I/O I/O P8 V DDP VDDP P9 V DD VDD P10 GND GND P11 GND GND 676-Pin FBGA Pin Number APA600 Function APA750 Function P12 GND GND P13 GND GND P14 GND GND P15 GND GND P16 GND GND P17 GND GND P18 V DD VDD P19 V DDP VDDP P20 I/O I/O P21 I/O I/O P22 I/O / GLMX2 I/O / GLMX2 P23 I/O I/O P24 PPECL2 / Input PPECL2 / Input P25 AVDD AVDD P26 AGND AGND R1 I/O I/O R2 I/O I/O R3 I/O I/O R4 I/O I/O R5 I/O I/O R6 I/O I/O R7 NC NC R8 V DDP VDDP R9 V DD VDD R10 GND GND R11 GND GND R12 GND GND R13 GND GND R14 GND GND R15 GND GND R16 GND GND R17 GND GND R18 V DD VDD R19 V DDP VDDP 676-Pin FBGA Pin Number APA600 Function APA750 Function R20 NC NC R21 I/O I/O R22 I/O I/O R23 I/O I/O R24 I/O I/O R25 I/O I/O R26 I/O I/O T1 I/O I/O T2 I/O I/O T3 I/O I/O T4 I/O I/O T5 I/O I/O T6 I/O I/O T7 I/O I/O T8 V DDP VDDP T9 V DD VDD T10 GND GND T11 GND GND T12 GND GND T13 GND GND T14 GND GND T15 GND GND T16 GND GND T17 GND GND T18 V DD VDD T19 V DDP VDDP T20 I/O I/O T21 I/O I/O T22 I/O I/O T23 I/O I/O T24 I/O I/O T25 I/O I/O T26 I/O I/O U1 I/O I/O U2 I/O I/O 676-Pin FBGA Pin Number APA600 Function APA750 Function

ProASICPLUS Flash Family FPGAs 2-56 v5.7 U3 I/O I/O U4 I/O I/O U5 I/O I/O U6 I/O I/O U7 NC NC U8 V DDP VDDP U9 V DD VDD U10 GND GND U11 GND GND U12 GND GND U13 GND GND U14 GND GND U15 GND GND U16 GND GND U17 GND GND U18 V DD VDD U19 V DDP VDDP U20 NC NC U21 I/O I/O U22 I/O I/O U23 I/O I/O U24 I/O I/O U25 I/O I/O U26 I/O I/O V1 I/O I/O V2 I/O I/O V3 I/O I/O V4 I/O I/O V5 I/O I/O V6 I/O I/O V7 I/O I/O V8 V DDP VDDP V9 V DD VDD V10 V DD VDD V11 V DD VDD 676-Pin FBGA Pin Number APA600 Function APA750 Function V12 V DD VDD V13 V DD VDD V14 V DD VDD V15 V DD VDD V16 V DD VDD V17 V DD VDD V18 V DD VDD V19 V DDP VDDP V20 I/O I/O V21 I/O I/O V22 I/O I/O V23 I/O I/O V24 I/O I/O V25 I/O I/O V26 I/O I/O W1 I/O I/O W2 I/O I/O W3 I/O I/O W4 I/O I/O W5 I/O I/O W6 I/O I/O W7 V DD VDD W8 V DD VDD W9 V DDP VDDP W10 V DDP VDDP W11 V DDP VDDP W12 V DDP VDDP W13 V DDP VDDP W14 V DDP VDDP W15 V DDP VDDP W16 V DDP VDDP W17 V DDP VDDP W18 V DDP VDDP W19 V DD VDD W20 V DDP VDDP 676-Pin FBGA Pin Number APA600 Function APA750 Function W21 I/O I/O W22 I/O I/O W23 I/O I/O W24 I/O I/O W25 I/O I/O W26 I/O I/O Y1 I/O I/O Y2 I/O I/O Y3 I/O I/O Y4 I/O I/O Y5 I/O I/O Y6 I/O I/O Y7 I/O I/O Y8 V DDP VDDP Y9 NC NC Y10 I/O I/O Y11 NC NC Y12 I/O I/O Y13 NC NC Y14 I/O I/O Y15 NC NC Y16 I/O I/O Y17 NC NC Y18 I/O I/O Y19 V DD VDD Y20 V PP VPP Y21 I/O I/O Y22 I/O I/O Y23 I/O I/O Y24 I/O I/O Y25 I/O I/O Y26 I/O I/O AA1 I/O I/O AA2 I/O I/O AA3 I/O I/O 676-Pin FBGA Pin Number APA600 Function APA750 Function

ProASICPLUS Flash Family FPGAs v5.7 2-57 AA4 I/O I/O AA5 I/O I/O AA6 GND GND AA7 I/O I/O AA8 I/O I/O AA9 I/O I/O AA10 I/O I/O AA11 I/O I/O AA12 I/O I/O AA13 I/O I/O AA14 I/O I/O AA15 I/O I/O AA16 I/O I/O AA17 I/O I/O AA18 I/O I/O AA19 I/O I/O AA20 I/O I/O AA21 TDO TDO AA22 GND GND AA23 GND GND AA24 I/O I/O AA25 I/O I/O AA26 I/O I/O AB1 I/O I/O AB2 I/O I/O AB3 I/O I/O AB4 I/O I/O AB5 I/O I/O AB6 GND GND AB7 GND GND AB8 I/O I/O AB9 I/O I/O AB10 I/O I/O AB11 I/O I/O AB12 I/O I/O 676-Pin FBGA Pin Number APA600 Function APA750 Function AB13 I/O I/O AB14 I/O I/O AB15 I/O I/O AB16 I/O I/O AB17 I/O I/O AB18 I/O I/O AB19 I/O I/O AB20 I/O I/O AB21 TCK TCK AB22 TRST TRST AB23 I/O I/O AB24 I/O I/O AB25 I/O I/O AB26 I/O I/O AC1 I/O I/O AC2 I/O I/O AC3 I/O I/O AC4 I/O I/O AC5 GND GND AC6 I/O I/O AC7 I/O I/O AC8 I/O I/O AC9 GND GND AC10 I/O I/O AC11 I/O I/O AC12 I/O I/O AC13 I/O I/O AC14 I/O I/O AC15 I/O I/O AC16 I/O I/O AC17 I/O I/O AC18 I/O I/O AC19 I/O I/O AC20 I/O I/O AC21 I/O I/O 676-Pin FBGA Pin Number APA600 Function APA750 Function AC22 TMS TMS AC23 RCK RCK AC24 I/O I/O AC25 I/O I/O AC26 I/O I/O AD1 I/O I/O AD2 I/O I/O AD3 I/O I/O AD4 I/O I/O AD5 I/O I/O AD6 I/O I/O AD7 I/O I/O AD8 I/O I/O AD9 I/O I/O AD10 I/O I/O AD11 I/O I/O AD12 I/O I/O AD13 I/O I/O AD14 I/O I/O AD15 I/O I/O AD16 I/O I/O AD17 I/O I/O AD18 I/O I/O AD19 I/O I/O AD20 I/O I/O AD21 I/O I/O AD22 I/O I/O AD23 TDI TDI AD24 V PN VPN AD25 I/O I/O AD26 I/O I/O AE1 GND GND AE2 GND GND AE3 GND GND AE4 I/O I/O 676-Pin FBGA Pin Number APA600 Function APA750 Function

ProASICPLUS Flash Family FPGAs 2-58 v5.7 AE5 I/O I/O AE6 I/O I/O AE7 I/O I/O AE8 I/O I/O AE9 I/O I/O AE10 I/O I/O AE11 I/O I/O AE12 I/O I/O AE13 I/O I/O AE14 I/O I/O AE15 I/O I/O AE16 I/O I/O AE17 I/O I/O AE18 I/O I/O AE19 I/O I/O AE20 I/O I/O AE21 I/O I/O AE22 I/O I/O AE23 I/O I/O AE24 I/O I/O AE25 GND GND AE26 GND GND AF1 GND GND AF2 GND GND AF3 GND GND AF4 GND GND AF5 I/O I/O AF6 I/O I/O AF7 I/O I/O AF8 I/O I/O AF9 I/O I/O AF10 I/O I/O AF11 I/O I/O AF12 I/O I/O AF13 I/O I/O 676-Pin FBGA Pin Number APA600 Function APA750 Function AF14 I/O I/O AF15 I/O I/O AF16 I/O I/O AF17 I/O I/O AF18 I/O I/O AF19 I/O I/O AF20 I/O I/O AF21 I/O I/O AF22 I/O I/O AF23 I/O I/O AF24 I/O I/O AF25 GND GND AF26 GND GND 676-Pin FBGA Pin Number APA600 Function APA750 Function

ProASICPLUS Flash Family FPGAs v5.7 2-59 896-Pin FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 123456789101112131415161718192021222324252627282930 A1 Ball Pad Corner

ProASICPLUS Flash Family FPGAs 2-60 v5.7 896-Pin FBGA Pin Number APA750 Function APA1000 Function A2 GND GND A3 GND GND A4 I/O I/O A5 GND GND A6 I/O I/O A7 GND GND A8 I/O I/O A9 I/O I/O A10 I/O I/O A11 I/O I/O A12 I/O I/O A13 I/O I/O A14 I/O I/O A15 I/O I/O A16 I/O I/O A17 I/O I/O A18 I/O I/O A19 I/O I/O A20 I/O I/O A21 I/O I/O A22 I/O I/O A23 I/O I/O A24 GND GND A25 I/O I/O A26 GND GND A27 I/O I/O A28 GND GND A29 GND GND B1 GND GND B2 GND GND B3 I/O I/O B4 V DD VDD B5 I/O I/O B6 V DD VDD B7 I/O I/O B8 I/O I/O B9 I/O I/O B10 I/O I/O B11 I/O I/O B12 I/O I/O B13 I/O I/O B14 I/O I/O B15 I/O I/O B16 I/O I/O B17 I/O I/O B18 I/O I/O B19 I/O I/O B20 I/O I/O B21 I/O I/O B22 I/O I/O B23 I/O I/O B24 I/O I/O B25 V DD VDD B26 I/O I/O B27 V DD VDD B28 I/O I/O B29 GND GND B30 GND GND C1 GND GND C2 I/O I/O C3 V DD VDD C4 I/O I/O C5 V DDP VDDP C6 I/O I/O C7 I/O I/O C8 I/O I/O C9 I/O I/O C10 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function C11 I/O I/O C12 I/O I/O C13 I/O I/O C14 I/O I/O C15 I/O I/O C16 I/O I/O C17 I/O I/O C18 I/O I/O C19 I/O I/O C20 I/O I/O C21 I/O I/O C22 I/O I/O C23 I/O I/O C24 I/O I/O C25 I/O I/O C26 V DDP VDDP C27 I/O I/O C28 V DD VDD C29 NC I/O C30 GND GND D1 I/O I/O D2 V DD VDD D3 I/O I/O D4 GND GND D5 I/O I/O D6 I/O I/O D7 I/O I/O D8 I/O I/O D9 I/O I/O D10 I/O I/O D11 I/O I/O D12 I/O I/O D13 I/O I/O D14 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-61 D15 I/O I/O D16 I/O I/O D17 I/O I/O D18 I/O I/O D19 I/O I/O D20 I/O I/O D21 I/O I/O D22 I/O I/O D23 I/O I/O D24 I/O I/O D25 I/O I/O D26 I/O I/O D27 GND GND D28 I/O I/O D29 V DD VDD D30 I/O I/O E1 GND GND E2 I/O I/O E3 V DDP VDDP E4 I/O I/O E5 V DD VDD E6 I/O I/O E7 V DDP VDDP E8 I/O I/O E9 I/O I/O E10 I/O I/O E11 I/O I/O E12 I/O I/O E13 I/O I/O E14 I/O I/O E15 I/O I/O E16 I/O I/O E17 I/O I/O E18 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function E19 I/O I/O E20 I/O I/O E21 I/O I/O E22 I/O I/O E23 I/O I/O E24 V DDP VDDP E25 I/O I/O E26 V DD VDD E27 I/O I/O E28 V DDP VDDP E29 I/O I/O E30 GND GND F1 I/O I/O F2 V DD VDD F3 I/O I/O F4 I/O I/O F5 I/O I/O F6 GND GND F7 I/O I/O F8 I/O I/O F9 I/O I/O F10 I/O I/O F11 I/O I/O F12 I/O I/O F13 I/O I/O F14 I/O I/O F15 I/O I/O F16 I/O I/O F17 I/O I/O F18 I/O I/O F19 I/O I/O F20 I/O I/O F21 I/O I/O F22 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function F23 I/O I/O F24 I/O I/O F25 GND GND F26 I/O I/O F27 I/O I/O F28 I/O I/O F29 V DD VDD F30 I/O I/O G1 GND GND G2 I/O I/O G3 I/O I/O G4 I/O I/O G5 V DDP VDDP G6 I/O I/O G7 V DD VDD G8 I/O I/O G9 V DDP VDDP G10 I/O I/O G11 I/O I/O G12 I/O I/O G13 I/O I/O G14 I/O I/O G15 I/O I/O G16 I/O I/O G17 I/O I/O G18 I/O I/O G19 I/O I/O G20 I/O I/O G21 I/O I/O G22 V DDP VDDP G23 I/O I/O G24 V DD VDD G25 I/O I/O G26 V DDP VDDP 896-Pin FBGA Pin Number APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-62 v5.7 G27 I/O I/O G28 I/O I/O G29 I/O I/O G30 GND GND H1 I/O I/O H2 I/O I/O H3 I/O I/O H4 I/O I/O H5 I/O I/O H6 I/O I/O H7 I/O I/O H8 GND GND H9 NC I/O H10 NC I/O H11 NC I/O H12 NC I/O H13 NC I/O H14 NC I/O H15 NC I/O H16 NC I/O H17 NC I/O H18 NC I/O H19 NC I/O H20 NC I/O H21 NC I/O H22 NC I/O H23 GND GND H24 I/O I/O H25 I/O I/O H26 I/O I/O H27 I/O I/O H28 I/O I/O H29 I/O I/O H30 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function J1 I/O I/O J2 I/O I/O J3 I/O I/O J4 I/O I/O J5 I/O I/O J6 I/O I/O J7 V DDP VDDP J8 I/O I/O J9 V DD VDD J10 NC I/O J11 NC I/O J12 NC I/O J13 NC I/O J14 NC I/O J15 NC I/O J16 NC I/O J17 NC I/O J18 NC I/O J19 NC I/O J20 NC I/O J21 NC I/O J22 V DD VDD J23 I/O I/O J24 V DDP VDDP J25 I/O I/O J26 I/O I/O J27 I/O I/O J28 I/O I/O J29 I/O I/O J30 I/O I/O K1 I/O I/O K2 I/O I/O K3 I/O I/O K4 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function K5 I/O I/O K6 I/O I/O K7 I/O I/O K8 I/O I/O K9 NC I/O K10 V DD VDD K11 NC I/O K12 V DDP VDDP K13 V DDP VDDP K14 V DDP VDDP K15 V DDP VDDP K16 V DDP VDDP K17 V DDP VDDP K18 V DDP VDDP K19 V DDP VDDP K20 NC I/O K21 V DD VDD K22 NC I/O K23 I/O I/O K24 I/O I/O K25 I/O I/O K26 I/O I/O K27 I/O I/O K28 I/O I/O K29 I/O I/O K30 I/O I/O L1 I/O I/O L2 I/O I/O L3 I/O I/O L4 I/O I/O L5 I/O I/O L6 I/O I/O L7 I/O I/O L8 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-63 L9 NC I/O L10 NC I/O L11 V DD VDD L12 V DD VDD L13 V DD VDD L14 V DD VDD L15 V DD VDD L16 V DD VDD L17 V DD VDD L18 V DD VDD L19 V DD VDD L20 V DD VDD L21 NC I/O L22 NC I/O L23 I/O I/O L24 I/O I/O L25 I/O I/O L26 I/O I/O L27 I/O I/O L28 I/O I/O L29 I/O I/O L30 I/O I/O M1 I/O I/O M2 I/O I/O M3 I/O I/O M4 I/O I/O M5 I/O I/O M6 I/O I/O M7 I/O I/O M8 I/O I/O M9 NC I/O M10 V DDP VDDP M11 V DD VDD M12 GND GND 896-Pin FBGA Pin Number APA750 Function APA1000 Function M13 GND GND M14 GND GND M15 GND GND M16 GND GND M17 GND GND M18 GND GND M19 GND GND M20 V DD VDD M21 V DDP VDDP M22 NC I/O M23 I/O I/O M24 I/O I/O M25 I/O I/O M26 I/O I/O M27 I/O I/O M28 I/O I/O M29 I/O I/O M30 I/O I/O N1 I/O I/O N2 I/O I/O N3 I/O I/O N4 I/O I/O N5 I/O I/O N6 I/O I/O N7 I/O I/O N8 I/O I/O N9 NC I/O N10 V DDP VDDP N11 V DD VDD N12 GND GND N13 GND GND N14 GND GND N15 GND GND N16 GND GND 896-Pin FBGA Pin Number APA750 Function APA1000 Function N17 GND GND N18 GND GND N19 GND GND N20 V DD VDD N21 V DDP VDDP N22 NC I/O N23 I/O I/O N24 I/O I/O N25 I/O I/O N26 I/O I/O N27 I/O I/O N28 I/O I/O N29 I/O I/O N30 I/O I/O P1 I/O I/O P2 I/O I/O P3 I/O I/O P4 I/O I/O P5 I/O I/O P6 I/O I/O P7 I/O I/O P8 I/O I/O P9 I/O I/O P10 V DDP VDDP P11 V DD VDD P12 GND GND P13 GND GND P14 GND GND P15 GND GND P16 GND GND P17 GND GND P18 GND GND P19 GND GND P20 V DD VDD 896-Pin FBGA Pin Number APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-64 v5.7 P21 V DDP VDDP P22 I/O I/O P23 I/O I/O P24 I/O I/O P25 I/O I/O P26 I/O I/O P27 I/O I/O P28 I/O I/O P29 I/O I/O P30 I/O I/O R1 I/O I/O R2 I/O / GLMX1 I/O / GLMX1 R3 AGND AGND R4 NPECL1 NPECL1 R5 I/O / GL1 I/O / GL1 R6 I/O I/O R7 I/O I/O R8 I/O I/O R9 NC I/O R10 V DDP VDDP R11 V DD VDD R12 GND GND R13 GND GND R14 GND GND R15 GND GND R16 GND GND R17 GND GND R18 GND GND R19 GND GND R20 V DD VDD R21 V DDP VDDP R22 I/O I/O R23 I/O I/O R24 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function R25 I/O I/O R26 I/O I/O R27 NPECL2 NPECL2 R28 AGND AGND R29 I/O / GLMX2 I/O / GLMX2 R30 I/O I/O T1 I/O I/O T2 AVDD AVDD T3 I/O / GL2 I/O / GL2 T4 PPECL1 / Input PPECL1 / Input T5 I/O I/O T6 I/O I/O T7 I/O I/O T8 I/O I/O T9 I/O I/O T10 V DDP VDDP T11 V DD VDD T12 GND GND T13 GND GND T14 GND GND T15 GND GND T16 GND GND T17 GND GND T18 GND GND T19 GND GND T20 V DD VDD T21 V DDP VDDP T22 I/O I/O T23 I/O I/O T24 I/O I/O T25 I/O I/O T26 PPECL2 / Input PPECL2 / Input T27 I/O / GL4 I/O / GL4 T28 I/O / GL3 I/O / GL3 896-Pin FBGA Pin Number APA750 Function APA1000 Function T29 AVDD AVDD T30 I/O I/O U1 I/O I/O U2 I/O I/O U3 I/O I/O U4 I/O I/O U5 I/O I/O U6 I/O I/O U7 I/O I/O U8 I/O I/O U9 NC I/O U10 V DDP VDDP U11 V DD VDD U12 GND GND U13 GND GND U14 GND GND U15 GND GND U16 GND GND U17 GND GND U18 GND GND U19 GND GND U20 V DD VDD U21 V DDP VDDP U22 NC I/O U23 I/O I/O U24 I/O I/O U25 I/O I/O U26 I/O I/O U27 I/O I/O U28 I/O I/O U29 I/O I/O U30 I/O I/O V1 I/O I/O V2 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-65 V3 I/O I/O V4 I/O I/O V5 I/O I/O V6 I/O I/O V7 I/O I/O V8 I/O I/O V9 NC I/O V10 V DDP VDDP V11 V DD VDD V12 GND GND V13 GND GND V14 GND GND V15 GND GND V16 GND GND V17 GND GND V18 GND GND V19 GND GND V20 V DD VDD V21 V DDP VDDP V22 NC I/O V23 I/O I/O V24 I/O I/O V25 I/O I/O V26 I/O I/O V27 I/O I/O V28 I/O I/O V29 I/O I/O V30 I/O I/O W1 I/O I/O W2 I/O I/O W3 I/O I/O W4 I/O I/O W5 I/O I/O W6 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function W7 I/O I/O W8 I/O I/O W9 NC I/O W10 V DDP VDDP W11 V DD VDD W12 GND GND W13 GND GND W14 GND GND W15 GND GND W16 GND GND W17 GND GND W18 GND GND W19 GND GND W20 V DD VDD W21 V DDP VDDP W22 NC I/O W23 I/O I/O W24 I/O I/O W25 I/O I/O W26 I/O I/O W27 I/O I/O W28 I/O I/O W29 I/O I/O W30 I/O I/O Y1 I/O I/O Y2 I/O I/O Y3 I/O I/O Y4 I/O I/O Y5 I/O I/O Y6 I/O I/O Y7 I/O I/O Y8 I/O I/O Y9 NC I/O Y10 NC I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function Y11 V DD VDD Y12 V DD VDD Y13 V DD VDD Y14 V DD VDD Y15 V DD VDD Y16 V DD VDD Y17 V DD VDD Y18 V DD VDD Y19 V DD VDD Y20 V DD VDD Y21 NC I/O Y22 NC I/O Y23 I/O I/O Y24 I/O I/O Y25 I/O I/O Y26 I/O I/O Y27 I/O I/O Y28 I/O I/O Y29 I/O I/O Y30 I/O I/O AA1 I/O I/O AA2 I/O I/O AA3 I/O I/O AA4 I/O I/O AA5 I/O I/O AA6 I/O I/O AA7 I/O I/O AA8 I/O I/O AA9 NC I/O AA10 V DD VDD AA11 NC I/O AA12 V DDP VDDP AA13 V DDP VDDP AA14 V DDP VDDP 896-Pin FBGA Pin Number APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-66 v5.7 AA15 V DDP VDDP AA16 V DDP VDDP AA17 V DDP VDDP AA18 V DDP VDDP AA19 V DDP VDDP AA20 NC I/O AA21 V DD VDD AA22 NC I/O AA23 I/O I/O AA24 I/O I/O AA25 I/O I/O AA26 I/O I/O AA27 I/O I/O AA28 I/O I/O AA29 I/O I/O AA30 I/O I/O AB1 I/O I/O AB2 I/O I/O AB3 I/O I/O AB4 I/O I/O AB5 I/O I/O AB6 I/O I/O AB7 V DDP VDDP AB8 I/O I/O AB9 V DD VDD AB10 NC I/O AB11 NC I/O AB12 NC I/O AB13 NC I/O AB14 NC I/O AB15 NC I/O AB16 NC I/O AB17 NC I/O AB18 NC I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function AB19 NC I/O AB20 NC I/O AB21 NC I/O AB22 V DD VDD AB23 I/O I/O AB24 V DDP VDDP AB25 I/O I/O AB26 I/O I/O AB27 I/O I/O AB28 I/O I/O AB29 I/O I/O AB30 I/O I/O AC1 I/O I/O AC2 I/O I/O AC3 I/O I/O AC4 I/O I/O AC5 I/O I/O AC6 I/O I/O AC7 I/O I/O AC8 GND GND AC9 NC I/O AC10 NC I/O AC11 NC I/O AC12 NC I/O AC13 NC I/O AC14 NC I/O AC15 NC I/O AC16 NC I/O AC17 NC I/O AC18 NC I/O AC19 NC I/O AC20 NC I/O AC21 NC I/O AC22 NC I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function AC23 GND GND AC24 I/O I/O AC25 I/O I/O AC26 I/O I/O AC27 I/O I/O AC28 I/O I/O AC29 I/O I/O AC30 I/O I/O AD1 GND GND AD2 I/O I/O AD3 I/O I/O AD4 I/O I/O AD5 V DDP VDDP AD6 I/O I/O AD7 V DD VDD AD8 I/O I/O AD9 V DDP VDDP AD10 I/O I/O AD11 I/O I/O AD12 I/O I/O AD13 I/O I/O AD14 I/O I/O AD15 I/O I/O AD16 I/O I/O AD17 I/O I/O AD18 I/O I/O AD19 I/O I/O AD20 I/O I/O AD21 I/O I/O AD22 V DDP VDDP AD23 TCK TCK AD24 V DD VDD AD25 TRST TRST AD26 V DDP VDDP 896-Pin FBGA Pin Number APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-67 AD27 I/O I/O AD28 I/O I/O AD29 I/O I/O AD30 GND GND AE1 I/O I/O AE2 V DD VDD AE3 I/O I/O AE4 I/O I/O AE5 I/O I/O AE6 GND GND AE7 I/O I/O AE8 I/O I/O AE9 I/O I/O AE10 I/O I/O AE11 I/O I/O AE12 I/O I/O AE13 I/O I/O AE14 I/O I/O AE15 I/O I/O AE16 I/O I/O AE17 I/O I/O AE18 I/O I/O AE19 I/O I/O AE20 I/O I/O AE21 I/O I/O AE22 I/O I/O AE23 I/O I/O AE24 I/O I/O AE25 GND GND AE26 I/O I/O AE27 I/O I/O AE28 I/O I/O AE29 V DD VDD AE30 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function AF1 GND GND AF2 I/O I/O AF3 V DDP VDDP AF4 I/O I/O AF5 V DD VDD AF6 I/O I/O AF7 V DDP VDDP AF8 I/O I/O AF9 I/O I/O AF10 I/O I/O AF11 I/O I/O AF12 I/O I/O AF13 I/O I/O AF14 I/O I/O AF15 I/O I/O AF16 I/O I/O AF17 I/O I/O AF18 I/O I/O AF19 I/O I/O AF20 I/O I/O AF21 I/O I/O AF22 I/O I/O AF23 I/O I/O AF24 V DDP VDDP AF25 I/O I/O AF26 V DD VDD AF27 TDO TDO AF28 V DDP VDDP AF29 V PN VPN AF30 GND GND AG1 I/O I/O AG2 V DD VDD AG3 I/O I/O AG4 GND GND 896-Pin FBGA Pin Number APA750 Function APA1000 Function AG5 I/O I/O AG6 I/O I/O AG7 I/O I/O AG8 I/O I/O AG9 I/O I/O AG10 I/O I/O AG11 I/O I/O AG12 I/O I/O AG13 I/O I/O AG14 I/O I/O AG15 I/O I/O AG16 I/O I/O AG17 I/O I/O AG18 I/O I/O AG19 I/O I/O AG20 I/O I/O AG21 I/O I/O AG22 I/O I/O AG23 I/O I/O AG24 I/O I/O AG25 I/O I/O AG26 I/O I/O AG27 GND GND AG28 RCK RCK AG29 V DD VDD AG30 I/O I/O AH1 GND GND AH2 I/O I/O AH3 V DD VDD AH4 I/O I/O AH5 V DDP VDDP AH6 I/O I/O AH7 I/O I/O AH8 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-68 v5.7 AH9 I/O I/O AH10 I/O I/O AH11 I/O I/O AH12 I/O I/O AH13 I/O I/O AH14 I/O I/O AH15 I/O I/O AH16 I/O I/O AH17 I/O I/O AH18 I/O I/O AH19 I/O I/O AH20 I/O I/O AH21 I/O I/O AH22 I/O I/O AH23 I/O I/O AH24 I/O I/O AH25 I/O I/O AH26 V DDP VDDP AH27 TDI TDI AH28 V DD VDD AH29 V PP VPP AH30 GND GND AJ1 GND GND AJ2 GND GND AJ3 I/O I/O AJ4 V DD VDD AJ5 I/O I/O AJ6 V DD VDD AJ7 I/O I/O AJ8 I/O I/O AJ9 I/O I/O AJ10 I/O I/O AJ11 I/O I/O AJ12 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function AJ13 I/O I/O AJ14 I/O I/O AJ15 I/O I/O AJ16 I/O I/O AJ17 I/O I/O AJ18 I/O I/O AJ19 I/O I/O AJ20 I/O I/O AJ21 I/O I/O AJ22 I/O I/O AJ23 I/O I/O AJ24 I/O I/O AJ25 V DD VDD AJ26 I/O I/O AJ27 V DD VDD AJ28 TMS TMS AJ29 GND GND AJ30 GND GND AK2 GND GND AK3 GND GND AK4 I/O I/O AK5 GND GND AK6 I/O I/O AK7 GND GND AK8 I/O I/O AK9 I/O I/O AK10 I/O I/O AK11 I/O I/O AK12 I/O I/O AK13 I/O I/O AK14 I/O I/O AK15 I/O I/O AK16 I/O I/O AK17 I/O I/O 896-Pin FBGA Pin Number APA750 Function APA1000 Function AK18 I/O I/O AK19 I/O I/O AK20 I/O I/O AK21 I/O I/O AK22 I/O I/O AK23 I/O I/O AK24 GND GND AK25 I/O I/O AK26 GND GND AK27 I/O I/O AK28 GND GND AK29 GND GND 896-Pin FBGA Pin Number APA750 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-69 1152-Pin FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AGAG AH AJ AK 123456789101112131415161718192021232425262728293031323334 AL AM AN AP A1 Ball Pad Corner

ProASICPLUS Flash Family FPGAs 2-70 v5.7 1152-Pin FBGA Pin Number APA1000 Function A2 NC A3 GND A4 GND A5 GND A6 I/O A7 V DD A8 V DD A9 V DD A10 V DD A11 I/O A12 GND A13 I/O A14 V DDP A15 V DDP A16 I/O A17 GND A18 GND A19 I/O A20 V DDP A21 V DDP A22 I/O A23 GND A24 I/O A25 V DD A26 V DD A27 V DD A28 V DD A29 I/O A30 GND A31 GND A32 GND A33 NC B1 NC B2 NC B3 GND B4 GND B5 GND B6 NC B7 I/O B8 NC B9 I/O B10 NC B11 I/O B12 GND B13 I/O B14 V DDP B15 V DDP B16 I/O B17 GND B18 GND B19 I/O B20 V DDP B21 V DDP B22 I/O B23 GND B24 I/O B25 NC B26 I/O B27 NC B28 I/O B29 NC B30 GND B31 GND B32 GND B33 NC B34 NC C1 GND C2 GND C3 NC C4 GND C5 GND C6 I/O C7 GND C8 I/O 1152-Pin FBGA Pin Number APA1000 Function C9 GND C10 I/O C11 I/O C12 I/O C13 I/O C14 I/O C15 I/O C16 I/O C17 I/O C18 I/O C19 I/O C20 I/O C21 I/O C22 I/O C23 I/O C24 I/O C25 I/O C26 GND C27 I/O C28 GND C29 I/O C30 GND C31 GND C32 NC C33 GND C34 GND D1 GND D2 GND D3 GND D4 GND D5 I/O D6 V DD D7 I/O D8 V DD D9 I/O D10 I/O D11 I/O 1152-Pin FBGA Pin Number APA1000 Function D12 I/O D13 I/O D14 I/O D15 I/O D16 I/O D17 I/O D18 I/O D19 I/O D20 I/O D21 I/O D22 I/O D23 I/O D24 I/O D25 I/O D26 I/O D27 V DD D28 I/O D29 V DD D30 I/O D31 GND D32 GND D33 GND D34 GND E1 GND E2 GND E3 GND E4 I/O E5 V DD E6 I/O E7 V DDP E8 I/O E9 I/O E10 I/O E11 I/O E12 I/O E13 I/O E14 I/O 1152-Pin FBGA Pin Number APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-71 E15 I/O E16 I/O E17 I/O E18 I/O E19 I/O E20 I/O E21 I/O E22 I/O E23 I/O E24 I/O E25 I/O E26 I/O E27 I/O E28 V DDP E29 I/O E30 V DD E31 I/O E32 GND E33 GND E34 GND F1 I/O F2 NC F3 I/O F4 V DD F5 I/O F6 GND F7 I/O F8 I/O F9 I/O F10 I/O F11 I/O F12 I/O F13 I/O F14 I/O F15 I/O F16 I/O F17 I/O 1152-Pin FBGA Pin Number APA1000 Function F18 I/O F19 I/O F20 I/O F21 I/O F22 I/O F23 I/O F24 I/O F25 I/O F26 I/O F27 I/O F28 I/O F29 GND F30 I/O F31 V DD F32 I/O F33 NC F34 NC G1 V DD G2 I/O G3 GND G4 I/O G5 V DDP G6 I/O G7 V DD G8 I/O G9 V DDP G10 I/O G11 I/O G12 I/O G13 I/O G14 I/O G15 I/O G16 I/O G17 I/O G18 I/O G19 I/O G20 I/O 1152-Pin FBGA Pin Number APA1000 Function G21 I/O G22 I/O G23 I/O G24 I/O G25 I/O G26 V DDP G27 I/O G28 V DD G29 I/O G30 V DDP G31 I/O G32 GND G33 I/O G34 V DD H1 V DD H2 NC H3 I/O H4 V DD H5 I/O H6 I/O H7 I/O H8 GND H9 I/O H10 I/O H11 I/O H12 I/O H13 I/O H14 I/O H15 I/O H16 I/O H17 I/O H18 I/O H19 I/O H20 I/O H21 I/O H22 I/O H23 I/O 1152-Pin FBGA Pin Number APA1000 Function H24 I/O H25 I/O H26 I/O H27 GND H28 I/O H29 I/O H30 I/O H31 V DD H32 I/O H33 NC H34 V DD J1 V DD J2 I/O J3 GND J4 I/O J5 I/O J6 I/O J7 V DDP J8 I/O J9 V DD J10 I/O J11 V DDP J12 I/O J13 I/O J14 I/O J15 I/O J16 I/O J17 I/O J18 I/O J19 I/O J20 I/O J21 I/O J22 I/O J23 I/O J24 V DDP J25 I/O J26 V DD 1152-Pin FBGA Pin Number APA1000 Function

ProASICPLUS Flash Family FPGAs 2-72 v5.7 J27 I/O J28 V DDP J29 I/O J30 I/O J31 I/O J32 GND J33 I/O J34 V DD K1 V DD K2 NC K3 I/O K4 I/O K5 I/O K6 I/O K7 I/O K8 I/O K9 I/O K10 GND K11 I/O K12 I/O K13 I/O K14 I/O K15 I/O K16 I/O K17 I/O K18 I/O K19 I/O K20 I/O K21 I/O K22 I/O K23 I/O K24 I/O K25 GND K26 I/O K27 I/O K28 I/O K29 I/O 1152-Pin FBGA Pin Number APA1000 Function K30 I/O K31 I/O K32 I/O K33 NC K34 V DD L1 I/O L2 I/O L3 I/O L4 I/O L5 I/O L6 I/O L7 I/O L8 I/O L9 V DDP L10 I/O L11 V DD L12 I/O L13 I/O L14 I/O L15 I/O L16 I/O L17 I/O L18 I/O L19 I/O L20 I/O L21 I/O L22 I/O L23 I/O L24 V DD L25 I/O L26 V DDP L27 I/O L28 I/O L29 I/O L30 I/O L31 I/O L32 I/O 1152-Pin FBGA Pin Number APA1000 Function L33 I/O L34 I/O M1 GND M2 GND M3 I/O M4 I/O M5 I/O M6 I/O M7 I/O M8 I/O M9 I/O M10 I/O M11 I/O M12 V DD M13 I/O M14 V DDP M15 V DDP M16 V DDP M17 V DDP M18 V DDP M19 V DDP M20 V DDP M21 V DDP M22 I/O M23 V DD M24 I/O M25 I/O M26 I/O M27 I/O M28 I/O M29 I/O M30 I/O M31 I/O M32 I/O M33 GND M34 GND N1 I/O 1152-Pin FBGA Pin Number APA1000 Function N2 I/O N3 I/O N4 I/O N5 I/O N6 I/O N7 I/O N8 I/O N9 I/O N10 I/O N11 I/O N12 I/O N13 V DD N14 V DD N15 V DD N16 V DD N17 V DD N18 V DD N19 V DD N20 V DD N21 V DD N22 V DD N23 I/O N24 I/O N25 I/O N26 I/O N27 I/O N28 I/O N29 I/O N30 I/O N31 I/O N32 I/O N33 I/O N34 I/O P1 V DDP P2 V DDP P3 I/O P4 I/O 1152-Pin FBGA Pin Number APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-73 P5 I/O P6 I/O P7 I/O P8 I/O P9 I/O P10 I/O P11 I/O P12 V DDP P13 V DD P14 GND P15 GND P16 GND P17 GND P18 GND P19 GND P20 GND P21 GND P22 V DD P23 V DDP P24 I/O P25 I/O P26 I/O P27 I/O P28 I/O P29 I/O P30 I/O P31 I/O P32 I/O P33 V DDP P34 V DDP R1 V DDP R2 V DDP R3 I/O R4 I/O R5 I/O R6 I/O R7 I/O 1152-Pin FBGA Pin Number APA1000 Function R8 I/O R9 I/O R10 I/O R11 I/O R12 V DDP R13 V DD R14 GND R15 GND R16 GND R17 GND R18 GND R19 GND R20 GND R21 GND R22 V DD R23 V DDP R24 I/O R25 I/O R26 I/O R27 I/O R28 I/O R29 I/O R30 I/O R31 I/O R32 I/O R33 V DDP R34 V DDP T1 I/O T2 I/O T3 I/O T4 I/O T5 I/O T6 I/O T7 I/O T8 I/O T9 I/O T10 I/O 1152-Pin FBGA Pin Number APA1000 Function T11 I/O T12 V DDP T13 V DD T14 GND T15 GND T16 GND T17 GND T18 GND T19 GND T20 GND T21 GND T22 V DD T23 V DDP T24 I/O T25 I/O T26 I/O T27 I/O T28 I/O T29 I/O T30 I/O T31 I/O T32 I/O T33 I/O T34 I/O U1 GND U2 GND U3 I/O U4 I/O / GLMX1 U5 AGND U6 NPECL1 U7 I/O / GL1 U8 I/O U9 I/O U10 I/O U11 I/O U12 V DDP U13 V DD 1152-Pin FBGA Pin Number APA1000 Function U14 GND U15 GND U16 GND U17 GND U18 GND U19 GND U20 GND U21 GND U22 V DD U23 V DDP U24 I/O U25 I/O U26 I/O U27 I/O U28 I/O U29 NPECL2 U30 AGND U31 I/O / GLMX2 U32 I/O U33 GND U34 GND V1 GND V2 GND V3 I/O V4 AVDD V5 I/O / GL2 V6 PPECL1 / Input V7 I/O V8 I/O V9 I/O V10 I/O V11 I/O V12 V DDP V13 V DD V14 GND V15 GND 1152-Pin FBGA Pin Number APA1000 Function

ProASICPLUS Flash Family FPGAs 2-74 v5.7 V16 GND V17 GND V18 GND V19 GND V20 GND V21 GND V22 V DD V23 V DDP V24 I/O V25 I/O V26 I/O V27 I/O V28 PPECL2 / Input V29 I/O / GL4 V30 I/O / GL3 V31 AVDD V32 I/O V33 GND V34 GND W1 I/O W2 I/O W3 I/O W4 I/O W5 I/O W6 I/O W7 I/O W8 I/O W9 I/O W10 I/O W11 I/O W12 V DDP W13 V DD W14 GND W15 GND W16 GND W17 GND 1152-Pin FBGA Pin Number APA1000 Function W18 GND W19 GND W20 GND W21 GND W22 V DD W23 V DDP W24 I/O W25 I/O W26 I/O W27 I/O W28 I/O W29 I/O W30 I/O W31 I/O W32 I/O W33 I/O W34 I/O Y1 V DDP Y2 V DDP Y3 I/O Y4 I/O Y5 I/O Y6 I/O Y7 I/O Y8 I/O Y9 I/O Y10 I/O Y11 I/O Y12 V DDP Y13 V DD Y14 GND Y15 GND Y16 GND Y17 GND Y18 GND Y19 GND Y20 GND 1152-Pin FBGA Pin Number APA1000 Function Y21 GND Y22 V DD Y23 V DDP Y24 I/O Y25 I/O Y26 I/O Y27 I/O Y28 I/O Y29 I/O Y30 I/O Y31 I/O Y32 I/O Y33 V DDP Y34 V DDP AA1 V DDP AA2 V DDP AA3 I/O AA4 I/O AA5 I/O AA6 I/O AA7 I/O AA8 I/O AA9 I/O AA10 I/O AA11 I/O AA12 V DDP AA13 V DD AA14 GND AA15 GND AA16 GND AA17 GND AA18 GND AA19 GND AA20 GND AA21 GND AA22 V DD AA23 V DDP 1152-Pin FBGA Pin Number APA1000 Function AA24 I/O AA25 I/O AA26 I/O AA27 I/O AA28 I/O AA29 I/O AA30 I/O AA31 I/O AA32 I/O AA33 V DDP AA34 V DDP AB1 I/O AB2 I/O AB3 I/O AB4 I/O AB5 I/O AB6 I/O AB7 I/O AB8 I/O AB9 I/O AB10 I/O AB11 I/O AB12 I/O AB13 V DD AB14 V DD AB15 V DD AB16 V DD AB17 V DD AB18 V DD AB19 V DD AB20 V DD AB21 V DD AB22 V DD AB23 I/O AB24 I/O AB25 I/O AB26 I/O 1152-Pin FBGA Pin Number APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-75 AB27 I/O AB28 I/O AB29 I/O AB30 I/O AB31 I/O AB32 I/O AB33 I/O AB34 I/O AC1 GND AC2 GND AC3 I/O AC4 I/O AC5 I/O AC6 I/O AC7 I/O AC8 I/O AC9 I/O AC10 I/O AC11 I/O AC12 V DD AC13 I/O AC14 V DDP AC15 V DDP AC16 V DDP AC17 V DDP AC18 V DDP AC19 V DDP AC20 V DDP AC21 V DDP AC22 I/O AC23 V DD AC24 I/O AC25 I/O AC26 I/O AC27 I/O AC28 I/O AC29 I/O 1152-Pin FBGA Pin Number APA1000 Function AC30 I/O AC31 I/O AC32 I/O AC33 GND AC34 GND AD1 I/O AD2 I/O AD3 I/O AD4 I/O AD5 I/O AD6 I/O AD7 I/O AD8 I/O AD9 V DDP AD10 I/O AD11 V DD AD12 I/O AD13 I/O AD14 I/O AD15 I/O AD16 I/O AD17 I/O AD18 I/O AD19 I/O AD20 I/O AD21 I/O AD22 I/O AD23 I/O AD24 V DD AD25 I/O AD26 V DDP AD27 I/O AD28 I/O AD29 I/O AD30 I/O AD31 I/O AD32 I/O 1152-Pin FBGA Pin Number APA1000 Function AD33 I/O AD34 I/O AE1 V DD AE2 NC AE3 I/O AE4 I/O AE5 I/O AE6 I/O AE7 I/O AE8 I/O AE9 I/O AE10 GND AE11 I/O AE12 I/O AE13 I/O AE14 I/O AE15 I/O AE16 I/O AE17 I/O AE18 I/O AE19 I/O AE20 I/O AE21 I/O AE22 I/O AE23 I/O AE24 I/O AE25 GND AE26 I/O AE27 I/O AE28 I/O AE29 I/O AE30 I/O AE31 I/O AE32 I/O AE33 NC AE34 V DD AF1 V DD 1152-Pin FBGA Pin Number APA1000 Function AF2 I/O AF3 GND AF4 I/O AF5 I/O AF6 I/O AF7 V DDP AF8 I/O AF9 V DD AF10 I/O AF11 V DDP AF12 I/O AF13 I/O AF14 I/O AF15 I/O AF16 I/O AF17 I/O AF18 I/O AF19 I/O AF20 I/O AF21 I/O AF22 I/O AF23 I/O AF24 V DDP AF25 TCK AF26 V DD AF27 TRST AF28 V DDP AF29 I/O AF30 I/O AF31 I/O AF32 GND AF33 I/O AF34 V DD AG1 V DD AG2 NC AG3 I/O AG4 V DD 1152-Pin FBGA Pin Number APA1000 Function

ProASICPLUS Flash Family FPGAs 2-76 v5.7 AG5 I/O AG6 I/O AG7 I/O AG8 GND AG9 I/O AG10 I/O AG11 I/O AG12 I/O AG13 I/O AG14 I/O AG15 I/O AG16 I/O AG17 I/O AG18 I/O AG19 I/O AG20 I/O AG21 I/O AG22 I/O AG23 I/O AG24 I/O AG25 I/O AG26 I/O AG27 GND AG28 I/O AG29 I/O AG30 I/O AG31 V DD AG32 I/O AG33 NC AG34 V DD AH1 V DD AH2 I/O AH3 GND AH4 I/O AH5 V DDP AH6 I/O AH7 V DD 1152-Pin FBGA Pin Number APA1000 Function AH8 I/O AH9 V DDP AH10 I/O AH11 I/O AH12 I/O AH13 I/O AH14 I/O AH15 I/O AH16 I/O AH17 I/O AH18 I/O AH19 I/O AH20 I/O AH21 I/O AH22 I/O AH23 I/O AH24 I/O AH25 I/O AH26 V DDP AH27 I/O AH28 V DD AH29 TDO AH30 V DDP AH31 V PN AH32 GND AH33 I/O AH34 V DD AJ1 I/O AJ2 NC AJ3 I/O AJ4 V DD AJ5 I/O AJ6 GND AJ7 I/O AJ8 I/O AJ9 I/O AJ10 I/O 1152-Pin FBGA Pin Number APA1000 Function AJ11 I/O AJ12 I/O AJ13 I/O AJ14 I/O AJ15 I/O AJ16 I/O AJ17 I/O AJ18 I/O AJ19 I/O AJ20 I/O AJ21 I/O AJ22 I/O AJ23 I/O AJ24 I/O AJ25 I/O AJ26 I/O AJ27 I/O AJ28 I/O AJ29 GND AJ30 RCK AJ31 V DD AJ32 I/O AJ33 NC AJ34 NC AK1 GND AK2 GND AK3 GND AK4 I/O AK5 V DD AK6 I/O AK7 V DDP AK8 I/O AK9 I/O AK10 I/O AK11 I/O AK12 I/O AK13 I/O 1152-Pin FBGA Pin Number APA1000 Function AK14 I/O AK15 I/O AK16 I/O AK17 I/O AK18 I/O AK19 I/O AK20 I/O AK21 I/O AK22 I/O AK23 I/O AK24 I/O AK25 I/O AK26 I/O AK27 I/O AK28 V DDP AK29 TDI AK30 V DD AK31 V PP AK32 GND AK33 GND AK34 GND AL1 GND AL2 GND AL3 GND AL4 GND AL5 I/O AL6 V DD AL7 I/O AL8 V DD AL9 I/O AL10 I/O AL11 I/O AL12 I/O AL13 I/O AL14 I/O AL15 I/O AL16 I/O 1152-Pin FBGA Pin Number APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-77 AL17 I/O AL18 I/O AL19 I/O AL20 I/O AL21 I/O AL22 I/O AL23 I/O AL24 I/O AL25 I/O AL26 I/O AL27 V DD AL28 I/O AL29 V DD AL30 TMS AL31 GND AL32 GND AL33 GND AL34 GND AM1 GND AM2 GND AM3 NC AM4 GND AM5 GND AM6 I/O AM7 GND AM8 I/O AM9 GND AM10 I/O AM11 I/O AM12 I/O AM13 I/O AM14 I/O AM15 I/O AM16 I/O AM17 I/O AM18 I/O AM19 I/O 1152-Pin FBGA Pin Number APA1000 Function AM20 I/O AM21 I/O AM22 I/O AM23 I/O AM24 I/O AM25 I/O AM26 GND AM27 I/O AM28 GND AM29 I/O AM30 GND AM31 GND AM32 NC AM33 GND AM34 GND AN1 NC AN2 NC AN3 GND AN4 GND AN5 GND AN6 NC AN7 I/O AN8 NC AN9 I/O AN10 NC AN11 I/O AN12 GND AN13 I/O AN14 V DDP AN15 V DDP AN16 I/O AN17 GND AN18 GND AN19 I/O AN20 V DDP AN21 V DDP AN22 I/O 1152-Pin FBGA Pin Number APA1000 Function AN23 GND AN24 I/O AN25 NC AN26 I/O AN27 NC AN28 I/O AN29 NC AN30 GND AN31 GND AN32 GND AN33 NC AN34 NC AP2 NC AP3 GND AP4 GND AP5 GND AP6 I/O AP7 V DD AP8 V DD AP9 V DD AP10 V DD AP11 I/O AP12 GND AP13 I/O AP14 V DDP AP15 V DDP AP16 I/O AP17 GND AP18 GND AP19 I/O AP20 V DDP AP21 V DDP AP22 I/O AP23 GND AP24 I/O AP25 V DD AP26 V DD 1152-Pin FBGA Pin Number APA1000 Function AP27 V DD AP28 V DD AP29 I/O AP30 GND AP31 GND AP32 GND AP33 NC 1152-Pin FBGA Pin Number APA1000 Function

ProASICPLUS Flash Family FPGAs 2-78 v5.7 624-Pin CCGA/LGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. Side View e AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 234 5 67 8 9 10 11121314 15 161718 19 202122 23 2524 e A1 Corner Index Area b E Top View Bottom View D A

ProASICPLUS Flash Family FPGAs v5.7 2-79 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function A2 I/O I/O A3 I/O I/O A4 I/O I/O A5 I/O I/O A6 I/O I/O A7 I/O I/O A8 I/O I/O A9 I/O I/O A10 I/O I/O A11 I/O I/O A12 I/O I/O A13 I/O I/O A14 I/O I/O A15 I/O I/O A16 I/O I/O A17 I/O I/O A18 I/O I/O A19 I/O I/O A20 I/O I/O A21 I/O I/O A22 I/O I/O A23 I/O I/O A24 V DDP VDDP A25 GND GND B1 I/O I/O B2 GND GND B3 V DDP VDDP B4 I/O I/O B5 I/O I/O B6 I/O I/O B7 I/O I/O B8 I/O I/O B9 I/O I/O B10 I/O I/O B11 I/O I/O B12 I/O I/O B13 I/O I/O B14 I/O I/O B15 I/O I/O B16 I/O I/O B17 I/O I/O B18 I/O I/O B19 I/O I/O B20 I/O I/O B21 I/O I/O B22 I/O I/O B23 V DD VDD B24 GND GND B25 V DDP VDDP C1 I/O I/O C2 V DDP VDDP C3 GND GND C4 V DD VDD C5 I/O I/O C6 I/O I/O C7 GND GND C8 I/O I/O C9 I/O I/O C10 I/O I/O C11 I/O I/O C12 I/O I/O C13 I/O I/O C14 I/O I/O C15 I/O I/O C16 I/O I/O C17 I/O I/O C18 I/O I/O C19 GND GND C20 I/O I/O C21 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function C22 I/O I/O C23 GND GND C24 V DD VDD C25 I/O I/O D1 I/O I/O D2 I/O I/O D3 V DD VDD D4 GND GND D5 I/O I/O D6 I/O I/O D7 I/O I/O D8 I/O I/O D9 I/O I/O D10 I/O I/O D11 GND GND D12 I/O I/O D13 I/O I/O D14 I/O I/O D15 GND GND D16 I/O I/O D17 I/O I/O D18 I/O I/O D19 I/O I/O D20 I/O I/O D21 I/O I/O D22 I/O I/O D23 I/O I/O D24 I/O I/O D25 I/O I/O E1 I/O I/O E2 I/O I/O E3 I/O I/O E4 I/O I/O E5 I/O I/O E6 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-80 v5.7 E7 I/O I/O E8 I/O I/O E9 I/O I/O E10 I/O I/O E11 I/O I/O E12 I/O I/O E13 I/O I/O E14 I/O I/O E15 I/O I/O E16 I/O I/O E17 I/O I/O E18 I/O I/O E19 I/O I/O E20 I/O I/O E21 I/O I/O E22 I/O I/O E23 I/O I/O E24 I/O I/O E25 I/O I/O F1 I/O I/O F2 I/O I/O F3 I/O I/O F4 I/O I/O F5 I/O I/O F6 I/O I/O F7 I/O I/O F8 GND GND F9 I/O I/O F10 I/O I/O F11 I/O I/O F12 I/O I/O F13 I/O I/O F14 I/O I/O F15 I/O I/O F16 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function F17 I/O I/O F18 GND GND F19 I/O I/O F20 I/O I/O F21 I/O I/O F22 I/O I/O F23 I/O I/O F24 I/O I/O F25 I/O I/O G1 I/O I/O G2 I/O I/O G3 I/O I/O G4 I/O I/O G5 I/O I/O G6 I/O I/O G7 I/O I/O G8 I/O I/O G9 I/O I/O G10 I/O I/O G11 I/O I/O G12 I/O I/O G13 I/O I/O G14 I/O I/O G15 I/O I/O G16 I/O I/O G17 I/O I/O G18 I/O I/O G19 I/O I/O G20 I/O I/O G21 I/O I/O G22 I/O I/O G23 I/O I/O G24 I/O I/O G25 I/O I/O H1 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function H2 I/O I/O H3 GND GND H4 I/O I/O H5 I/O I/O H6 I/O I/O H7 I/O I/O H8 V DDP VDDP H9 V DDP VDDP H10 V DDP VDDP H11 V DDP VDDP H12 V DDP VDDP H13 V DDP VDDP H14 V DDP VDDP H15 V DDP VDDP H16 V DDP VDDP H17 V DDP VDDP H18 V DDP VDDP H19 I/O I/O H20 I/O I/O H21 I/O I/O H22 I/O I/O H23 GND GND H24 I/O I/O H25 I/O I/O J1 I/O I/O J2 I/O I/O J3 I/O I/O J4 I/O I/O J5 I/O I/O J6 GND GND J7 I/O I/O J8 V DDP VDDP J9 GND GND J10 GND GND J11 GND GND 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-81 J12 GND GND J13 GND GND J14 GND GND J15 GND GND J16 GND GND J17 GND GND J18 V DDP VDDP J19 I/O I/O J20 GND GND J21 I/O I/O J22 I/O I/O J23 I/O I/O J24 I/O I/O J25 I/O I/O K1 I/O I/O K2 I/O I/O K3 I/O I/O K4 I/O I/O K5 I/O I/O K6 I/O I/O K7 I/O I/O K8 V DDP VDDP K9 GND GND K10 V DD VDD K11 V DD VDD K12 V DD VDD K13 V DD VDD K14 V DD VDD K15 V DD VDD K16 V DD VDD K17 GND GND K18 V DDP VDDP K19 I/O I/O K20 I/O I/O K21 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function K22 I/O I/O K23 I/O I/O K24 I/O I/O K25 I/O I/O L1 I/O I/O L2 I/O I/O L3 I/O I/O L4 I/O I/O L5 I/O I/O L6 I/O I/O L7 I/O I/O L8 V DDP VDDP L9 GND GND L10 V DD VDD L11 GND GND L12 GND GND L13 GND GND L14 GND GND L15 GND GND L16 V DD VDD L17 GND GND L18 V DDP VDDP L19 I/O I/O L20 I/O I/O L21 I/O I/O L22 I/O I/O L23 I/O I/O L24 I/O I/O L25 I/O I/O M1 I/O I/O M2 I/O I/O M3 I/O I/O M4 AGND AGND M5 NPECL1 NPECL1 M6 I/O / GL2 I/O / GL2 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function M7 I/O / GLMX1 I/O / GLMX1 M8 V DDP VDDP M9 GND GND M10 V DD VDD M11 GND GND M12 GND GND M13 GND GND M14 GND GND M15 GND GND M16 V DD VDD M17 GND GND M18 V DDP VDDP M19 I/O / GLMX2 I/O / GLMX2 M20 I/O / GL4 I/O / GL4 M21 NPECL2 NPECL2 M22 AGND AGND M23 I/O I/O M24 I/O I/O M25 I/O I/O N1 I/O I/O N2 I/O I/O N3 I/O I/O N4 AVDD AVDD N5 PPECL1 / Input PPECL1 / Input N6 I/O / GL1 I/O / GL1 N7 I/O I/O N8 V DDP VDDP N9 GND GND N10 V DD VDD N11 GND GND N12 GND GND N13 GND GND N14 GND GND N15 GND GND 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-82 v5.7 N16 V DD VDD N17 GND GND N18 V DDP VDDP N19 I/O I/O N20 I/O / GL3 I/O / GL3 N21 PPECL2 / Input PPECL2 / Input N22 AVDD AVDD N23 I/O I/O N24 I/O I/O N25 I/O I/O P1 I/O I/O P2 I/O I/O P3 I/O I/O P4 GND GND P5 I/O I/O P6 I/O I/O P7 I/O I/O P8 V DDP VDDP P9 GND GND P10 V DD VDD P11 GND GND P12 GND GND P13 GND GND P14 GND GND P15 GND GND P16 V DD VDD P17 GND GND P18 V DDP VDDP P19 I/O I/O P20 I/O I/O P21 I/O I/O P22 GND GND P23 I/O I/O P24 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function P25 I/O I/O R1 I/O I/O R2 I/O I/O R3 I/O I/O R4 I/O I/O R5 I/O I/O R6 I/O I/O R7 I/O I/O R8 V DDP VDDP R9 GND GND R10 V DD VDD R11 GND GND R12 GND GND R13 GND GND R14 GND GND R15 GND GND R16 V DD VDD R17 GND GND R18 V DDP VDDP R19 I/O I/O R20 I/O I/O R21 I/O I/O R22 I/O I/O R23 I/O I/O R24 I/O I/O R25 I/O I/O T1 I/O I/O T2 I/O I/O T3 I/O I/O T4 I/O I/O T5 I/O I/O T6 I/O I/O T7 I/O I/O T8 V DDP VDDP T9 GND GND 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function T10 V DD VDD T11 V DD VDD T12 V DD VDD T13 V DD VDD T14 V DD VDD T15 V DD VDD T16 V DD VDD T17 GND GND T18 V DDP VDDP T19 I/O I/O T20 I/O I/O T21 I/O I/O T22 I/O I/O T23 I/O I/O T24 I/O I/O T25 I/O I/O U1 I/O I/O U2 I/O I/O U3 I/O I/O U4 I/O I/O U5 I/O I/O U6 GND GND U7 I/O I/O U8 V DDP VDDP U9 GND GND U10 GND GND U11 GND GND U12 GND GND U13 GND GND U14 GND GND U15 GND GND U16 GND GND U17 GND GND U18 V DDP VDDP U19 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 2-83 U20 GND GND U21 I/O I/O U22 I/O I/O U23 I/O I/O U24 I/O I/O U25 I/O I/O V1 I/O I/O V2 I/O I/O V3 GND GND V4 I/O I/O V5 I/O I/O V6 I/O I/O V7 I/O I/O V8 V DDP VDDP V9 V DDP VDDP V10 V DDP VDDP V11 V DDP VDDP V12 V DDP VDDP V13 V DDP VDDP V14 V DDP VDDP V15 V DDP VDDP V16 V DDP VDDP V17 V DDP VDDP V18 V DDP VDDP V19 RCK RCK V20 I/O I/O V21 I/O I/O V22 I/O I/O V23 GND GND V24 I/O I/O V25 I/O I/O W1 I/O I/O W2 I/O I/O W3 I/O I/O W4 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function W5 I/O I/O W6 I/O I/O W7 I/O I/O W8 I/O I/O W9 I/O I/O W10 I/O I/O W11 I/O I/O W12 I/O I/O W13 I/O I/O W14 I/O I/O W15 I/O I/O W16 I/O I/O W17 I/O I/O W18 I/O I/O W19 TMS TMS W20 TDO TDO W21 I/O I/O W22 I/O I/O W23 I/O I/O W24 I/O I/O W25 I/O I/O Y1 I/O I/O Y2 I/O I/O Y3 I/O I/O Y4 I/O I/O Y5 I/O I/O Y6 I/O I/O Y7 I/O I/O Y8 GND GND Y9 I/O I/O Y10 I/O I/O Y11 I/O I/O Y12 I/O I/O Y13 I/O I/O Y14 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function Y15 I/O I/O Y16 I/O I/O Y17 GND GND Y18 I/O I/O Y19 TCK TCK Y20 VPP VPP Y21 VPN VPN Y22 I/O I/O Y23 I/O I/O Y24 I/O I/O Y25 I/O I/O AA1 I/O I/O AA2 I/O I/O AA3 I/O I/O AA4 I/O I/O AA5 I/O I/O AA6 I/O I/O AA7 I/O I/O AA8 I/O I/O AA9 I/O I/O AA10 I/O I/O AA11 I/O I/O AA12 I/O I/O AA13 I/O I/O AA14 I/O I/O AA15 I/O I/O AA16 I/O I/O AA17 I/O I/O AA18 I/O I/O AA19 I/O I/O AA20 TDI TDI AA21 TRST TRST AA22 I/O I/O AA23 I/O I/O AA24 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function

ProASICPLUS Flash Family FPGAs 2-84 v5.7 AA25 I/O I/O AB1 I/O I/O AB2 I/O I/O AB3 I/O I/O AB4 I/O I/O AB5 I/O I/O AB6 I/O I/O AB7 I/O I/O AB8 I/O I/O AB9 I/O I/O AB10 I/O I/O AB11 GND GND AB12 I/O I/O AB13 I/O I/O AB14 I/O I/O AB15 GND GND AB16 I/O I/O AB17 I/O I/O AB18 I/O I/O AB19 I/O I/O AB20 I/O I/O AB21 I/O I/O AB22 I/O I/O AB23 I/O I/O AB24 I/O I/O AB25 I/O I/O AC1 I/O I/O AC2 V DD VDD AC3 GND GND AC4 I/O I/O AC5 I/O I/O AC6 I/O I/O AC7 GND GND AC8 I/O I/O AC9 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function AC10 I/O I/O AC11 I/O I/O AC12 I/O I/O AC13 I/O I/O AC14 I/O I/O AC15 I/O I/O AC16 I/O I/O AC17 I/O I/O AC18 I/O I/O AC19 GND GND AC20 I/O I/O AC21 I/O I/O AC22 I/O I/O AC23 I/O I/O AC24 V DD VDD AC25 I/O I/O AD1 V DDP VDDP AD2 GND GND AD3 V DD VDD AD4 I/O I/O AD5 I/O I/O AD6 I/O I/O AD7 I/O I/O AD8 I/O I/O AD9 I/O I/O AD10 I/O I/O AD11 I/O I/O AD12 I/O I/O AD13 I/O I/O AD14 I/O I/O AD15 I/O I/O AD16 I/O I/O AD17 I/O I/O AD18 I/O I/O AD19 I/O I/O 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function AD20 I/O I/O AD21 I/O I/O AD22 I/O I/O AD23 V DD VDD AD24 GND GND AD25 V DDP VDDP AE1 GND GND AE2 V DDP VDDP AE3 I/O I/O AE4 I/O I/O AE5 I/O I/O AE6 I/O I/O AE7 I/O I/O AE8 I/O I/O AE9 I/O I/O AE10 I/O I/O AE11 I/O I/O AE12 I/O I/O AE13 I/O I/O AE14 I/O I/O AE15 I/O I/O AE16 I/O I/O AE17 I/O I/O AE18 I/O I/O AE19 I/O I/O AE20 I/O I/O AE21 I/O I/O AE22 I/O I/O AE23 I/O I/O AE24 V DDP VDDP AE25 GND GND 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function

ProASICPLUS Flash Family FPGAs v5.7 3-1 Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version (v5.7) Page v5.6 (August 2008) VOH and VOL data in Table 1-22 was changed back to the data in v5.5. page 1-38 v5.5 (February 2007) VOH and VOL data was updated in Table 1-22. page 1-38 v5.4 (October 2006) A statement about single cell and cascaded cell timing diagrams was added to the "Enclosed Timing Diagrams – FIFO Mode:" section. page 1-65 The following pins were updated in the "144-FBGA Pin" table: Pin Number Updated Function C2 I/O / GL1 F1 I/O / GL2 page 2-38 v5.3 The heading, MIL-STD-883B, and note 4 were added to the "Device Resources" table. page iii (May 2006) The "Temperature Grade Offerings" table was updated to include the military (M) temperature grade in the following device/packages: APA300-FG144 APA300-FG256 APA600-FG256 APA600-FG484 APA600-FG676 APA1000-FG896 page iv v5.2 90° and 270° phase shift suppor t was removed from the datasheet. N/A (December 2005) The "Ordering Information" section was updated to include RoHS information. page ii The last paragraph of the "Boundary Scan (JTAG)" section was updated. page 1-11 The Output Frequency Range in the "Timing Control and Characteristics" section. page 1-13 The title for Table 1-18 was updated. page 1-34 The caption was updated in Figure 1-48. page 1-72 v5.1 MIL-STD-883 was added to the datasheet. N/A V CC and VCCI were changed to VDDP.N / A Table 1-9 was updated to include 135°C. page 1-20 v5.0 In the "208-Pin PQFP" table, the following pin numbers have been updated: Pin Number Function

24 I/O / GL2

30 I/O / GL1

In the "208-Pin CQFP" table, the following pin numbers have been updated: Pin Number Function

23 I/O / GLMX1

28 PPECL1 / Input

128 I/O / GL3

129 PPECL2 / Input

134 I/O / GL4

135 I/O / GLMX2

ProASICPLUS Flash Family FPGAs 3-2 v5.7 v4.1 In the "624-Pin CCGA/LGA" table, the following pin numbers have been updated: Pin Number Function M6 I/O / GL2 M7 I/O / GLMX1 M19 I/O / GLMX2 M20 I/O / GL4 N5 PPECL1 / Input N6 I/O / GL1 N20 I/O / GL3 N21 PPECL2 / Input page 2-79 MIL-STD 883B data will be added into this datasheet after the MIL-STD 883B qualification is complete. Green packaging information in the "Ordering Information" section was updated. page ii The "Temperature Grade Offerings" table was updated for the CG624. page iv The "Ordering Information" section was updated. page ii The "Live at Power-Up" section is new. page 1-3 Note 2 in Figure 1-4 was updated. page 1-4 The 3.3 V column in Table 1-3 was updated. page 1-9 The "Input/Output Blocks" section was updated. page 1-9 The note was removed from Table 1-4. page 1-9 The "Power-Up Sequencing" section was updated. page 1-10 The first bullet in the "ProASICPLUS Clock Management System" section was updated. page 1-13 The first paragraph in the "Performance Retention" section was updated. page 1-33 Mixed Voltage was removed from Table 1-19. page 1-35 Table 1-20 was updated. page 1-35 Mixed Mode Voltage was removed from Table 1-21 and the Military/MIL-STD-883B column was updated. page 1-36 All tables from page 1-42 to page 1-51 were updated. page 1-42 to page 1-51 Table 1-48 is new. page 1-53 Figure 1-30 is new. page 1-53 Note 1 in Table 1-50 was updated. page 1-55 The notes in Table 1-54 were updated. page 1-59 A note was added to Figure 1-48. page 1-72 A note was added to Table 1-66. Table 1-66 The "TRST Test Reset Input" section was updated in the "Pin Description" section. page 1-73 The "624-Pin CCGA/LGA" section was updated for the APA600 and APA1000. Please review all pin data. page 2-78 v4.0 Figure 1-20 was updated. page 1-19 Table 1-46 was updated. page 1-52 The "1152-Pin FBGA" figure was updated. page 2-69 Pin names were changed to more accurately re flect the multiple func tions supported by each pin. Previous version Changes in current version (v5.7) Page

ProASICPLUS Flash Family FPGAs 3-4 v5.7 v2.0 The Table 1 was updated. page i-i The "Ordering Information" section was updated. page i-ii The "Plastic Device Resources" section was updated. page i-ii The "ProASICPLUS Architecture" section was updated. page 1-2 Table 1-2 was updated. page 1-8 Table 1-8 is new. page 1-16 Figure 1-11 is new. page 1-10 The I ntroduction section in the "ProASICPLUS Clock Management System" section was updated. page 1-13 The "Physical Implementation" section was updated. page 1-13 The "Functional Description" on page 1-13 was updated. page 1-13 Figure 1-14 on page 1-14 through Figure 1-20 on page 1-19 were updated. page 1-14 to page 1-19 The "PLL Electrical Specifications" on page 1-21 was updated. page 1-21 Figure 1-25 on page 1-26 was updated. page 1-26 The "Calculating Typical Power Dissipation" on page 1-30 was updated. page 1-30 The ’Nominal Supply Voltages’ section was updated. page 1-34 The Table 1-22 was updated. page 1-38 The "Tristate Buffer Delays" on page 1-42 was updated. page 1-42 The "Output Buffer Delays" on page 1-44 was updated. page 1-44 The"Input Buffer Delays" on page 1-46 was updated. page 1-46 "Global Routing Skew" on page 1-50 was updated. page 1-50 The"Sample Macrocell Library Listing" on page 1-51 was updated. page 1-51 The "Pin Description" on page 1-73 was updated. page 1-73 The following pins have been changed in the "100-Pin TQFP" table: Pin Number Function Pin Number Function

10 I/O (GLMX1) 60 GL3

11 GL1 61 PPECL2 (I/P)

13 NPECL1 63 NPECL2

15 PPECL1(I/P) 65 GL4

16 GL2 66 I/O (GLMX2)

"144-Pin TQFP" section is new. page 2-3 The following pins have been changed in the "208-Pin PQFP" table: Pin Number Function Pin Number Function

23 I/O (GLMX1) 128 GL3

24 GL1 129 PPECL2 (I/P)

26 NPECL1 132 NPECL2

28 PPECL1 (I/P) 134 GL4

30 GL2 135 I/O (GLMX2)

The following pins have been changed in the "456-Pin PBGA" table: Pin Number Function Pin Number Function M1 GL1 N22 NPECL2 M2 GL2 N23 GL3 M22 GL4 N25 I/O (GLMX2) N2 I/O (GLMX1) P5 NPECL1 N4 PPECL1 (I/P) P26 PPECL2 (I/P) page 2-22 Previous version Changes in current version (v5.7) Page

ProASICPLUS Flash Family FPGAs v5.7 3-5 v2.0 (continued) The following pins have been changed in the "144-Pin FBGA" table: Pin Number Function Pin Number Function C2 GL2 F9 GL4 D12 I/O (GLMX2 )F11 PPECL2 (I/P E11 NPECL2 F12 GL3 F1 GL1 G1 PPECL1 (I/P) F3 I/O (GLMX1) G4 NPECL1 page 2-37 The following pins have been changed in the "256-Pin FBGA" table: Pin Number Function Pin Number Function H1 GL1 H16 GL4 H2 NPECL1 J1 GL2 H3 I/O (GLMX1) J2 PPECL1 (I/P) H13 I/O (GLMX2) J13 PPECL2 (I/P) H14 NPECL2 J16 GL3 page 2-40 The following pins have been changed in the "484-Pin FBGA" table: Pin Number Function Pin Number Function L4 GL1 L19 GL4 L5 NPECL1 M4 GL2 L6 I/O (GLMX1) M5 PPECL1 (I/P) L16 I/O (GLMX2) M16 PPECL2 (I/P) L17 NPECL2 M19 GL3 page 2-45 The following pins have been changed in the "676-Pin FBGA" table: Pin Number Function Pin Number Function N1 GL1 N25 GL4 N3 I/O (GLMX1) P1 GL2 N5 NPECL1 P5 PPECL1 (I/P) N22 GL3 P22 I/O (GLMX2) N24 NPECL2 P24 PPECL2 (I/P) page 2-51 The following pins have been changed in the "896-Pin FBGA" table: Pin Number Function Pin Number Function R2 I/O (GLMX1) T3 GL2 R4 NPECL1 T4 PPECL1 (I/P) R5 GL1 T26 PPECL2 (I/P) R27 NPECL2 T27 GL4 R29 I/O (GLMX2) T28 GL3 page 2-59 The following pins have been changed in the "1152-Pin FBGA" table: Pin Number Function Pin Number Function U4 I/O (GLMX1) U29 NPECL2 U6 NPECL1 U31 I/O (GLMX2) U7 GL1 V28 PPECL2 (I/P) V5 GL2 V29 GL4 V6 PPECL1 (I/P) V30 GL3 page 2-69 Previous version Changes in current version (v5.7) Page

ProASICPLUS Flash Family FPGAs 3-8 v5.7 Data Sheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are desi gnated as "Product Brief," "Advance d," "Production," and "Datasheet Supplement." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. Export Administration Regulations (EAR) The products described in this datasheet are subject to th e Export Administration Regu lations (EAR). They could require an approved export license prior to export from th e United States. An export in cludes release of product or disclosure of technology to a foreign national inside or outside the United States.

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