APA1000-FG896A ACTEL | Alldatasheet
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© 2004 Actel Corporation Automotive-Grade ProASICPLUS Flash Family FPGAs Features and Benefits High Capacity
- 75,000 to 1 Million System Gates 27k to 198kbits of Two-Port SRAM 66 to 642 User I/Os Reprogrammable Flash Technology 0 . 2 2 µ 4LM Flash-based CMOS Process Live at Power-Up, Single-Chip Solution No Configuration Device Required Retains Programmed Design during Power-Down/Power-Up Cycles Extended Temperature Range Supports Automotive Temperature Range -40 to 125°C (Junction) Performance 3.3V, 32-Bit PCI (up to 50 MHz) Two Integrated PLLs External System Performance up to 150 MHz Secure Programming Industry’s Most Effective Security Key (FlashLock™) Prevents Read Back of Programming Bitstream Low Power Low Impedance Flash Switches Segmented Hierarchical Routing Structure Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells High Performance Routing Hierarchy Ultra-Fast Local and Long-Line Network High-Speed, Very Long-Line Network High Performance, Low-Skew, Splittable Global Network 100% Utilization and >95% Routability I/O Schmitt-Trigger Option on Every Input 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate Bidirectional Global I/Os Compliance with PCI Specification Revision 2.2 Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant Pin Compatible Packages across ProASIC PLUS Family Unique Clock Conditioning Circuitry PLLs with Flexible Phase, Multiply/Divide and Delay Capabilities Internal and/or External Dynamic PLL Configuration Two LVPECL Differential Pairs for Clock or Data Inputs Standard FPGA and ASIC Design Flow Flexibility with Choice of Industry-Standard Frontend Tools Efficient Design through Front-End Timing and Gate Optimization ISP Support In-System Programming (ISP) via JTAG Port SRAMs and FIFOs ACTgen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical) TM Table 1 • Automotive-Grade ProASICPLUS Product Profile Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000 Maximum System Gates 75,000 150,000 300,000 450,000 600,000 750,000 1,000,000 Maximum Tiles (Registers) 3,072 6,144 8,192 12,288 21,504 32,768 56,320 Embedded RAM Bits (k=1,024 bits) 27k 36k 72k 108k 126k 144k 198k Embedded RAM Blocks (256x9) 12 16 32 48 56 64 88 LVPECL 222 2 2 22 PLL 222 2 2 22 Global Networks 444 4 4 44 Maximum Clocks 24 32 32 48 56 64 88 Maximum User I/Os 158 186 186 344 370 562 642 JTAG ISP Yes Yes Yes Yes Yes Yes Yes PCI Yes Yes Yes Yes Yes Yes Yes Package (by pin count) PQFP 208 208 208 208 208 208 208 FBGA 144 144, 256 144, 256 144, 256, 484 256, 484 896 896 Automotive Supplement
Automotive-Grade ProASICPLUS Flash Family FPGAs
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Ordering Information
Contact your local Actel sales representative for device availability. User I/Os* Device TQFP 100-Pin PQFP 208-Pin FBGA 144-Pin FBGA 256-Pin FBGA 484-Pin FBGA 896-Pin APA075 66 158 100 APA150 66 158 100 186 APA300 158 100 186 APA450 158 100 186 344 APA600 158 186 370 APA750 158 562 APA1000 158 642 Package Definitions TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, FBGA = Fine Pitch Ball Grid Array *Each pair of PECL I/Os were counted as one user I/O. Std Automotive-Grade ✔ APA1000 FG Part Number Package Type PQ = Plastic Quad Flat Pack (0.5mm pitch) TQ = Thin Quad Flat Pack (1.4mm pitch) FG = Fine Pitch Ball Grid Array (1.0mm pitch) 896 A Package Lead Count Application 150,000 Equivalent System GatesAPA150 = 75,000 Equivalent System GatesAPA075 = APA450 APA600 APA750 APA1000 450,000 Equivalent System Gates 600,000 Equivalent System Gates 750,000 Equivalent System Gates 1,000,000 Equivalent System Gates APA300 300,000 Equivalent System Gates= A = Automotive (-40 to 125˚C)
Automotive-Grade ProASICPLUS Flash Family FPGAs Automotive Supplement 3 General Description ProASICPLUS devices offer a reprogrammable design integration solution at the automotive temperature range (-40°C to +125°C) through the use of nonvolatile Flash technology. ProASIC PLUS devices have a fine-grain architecture, similar to ASICs, and enable engineers to design high-density systems using existing ASIC or FPGA design flows and tools. Automotive-grade ProASIC PLUS devices offer up to 1 million system gates, support up to 198kbits of two-port SRAM and 642 user I/Os and provide 50 MHz PCI performance. The nonvolatile and reprogrammable Flash technology enables ProASIC PLUS devices to be live at power-up, and no external boot PROM is required to support device programming. While on-board security mechanisms prevent any access to the programmed information, reprogramming can be performed in-system to support future design iterations and field upgrades. The ProASIC PLUS device architecture mitigates the complexity of ASIC migration at higher user volume, making the automotive-grade ProASIC PLUS a cost-effective solution for in-cabin telematics and automobile interconnect applications. The ProASIC PLUS family is built on an advanced Flash- based 0.22µm LVCMOS process with four layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs, resulting in predictable performance fully compatible with gate arrays. The ProASIC PLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-Tiles . Each tile can be configured as a flip-flop, latch, or three-input/one-output logic function by programming the appropriate Flash switches. The combination of fine granularity, flexible routing resources, and abundant Flash switches allows 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a four-level routing hierarchy. Automotive-grade ProASIC PLUS devices feature embedded two-port SRAM blocks with built-in FIFO/RAM control logic and user-defined depth and width. Users can select programming for synchronous or asynchronous operation, as well as parity generation or checking. The automotive-grade ProASIC PLUS devices offer a unique clock conditioning circuit (CCC), with two clock conditioning blocks in each device. Each block provides a phase-locked loop (PLL) core, delay lines, phase shifts (0 °, 90°, 180°, 270°), and clock multipliers/dividers, as well as the circuitry required to provide bidirectional access to the PLL. The PLL block contains four programmable frequency dividers, which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit can perform a positive/ negative clock delay operation in increments of 0.25 ns by up to 8 ns. The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high speed clock and data inputs. The automotive-grade ProASIC PLUS devices are available in a variety of high-performance plastic packages to simplify the system board design. To support for comprehensive, lower cost board-level testing, Actel’s ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture.
Automotive-Grade ProASICPLUS Flash Family FPGAs
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Actel guarantees the performance numbers presented in the Actel Designer timing analysis software and in this datasheet, as long as the specified device performance retention period is not exceeded. For devices operated and stored at 110°C or less, the performance retention period is 20 years after programming. For devices operated and stored at temperatures greater than 110°C, refer to Table 2 on page 5 to determine the performance retention period. Actel does not guarantee performance if the performance retention period is exceeded. Evaluate the percentage of time spent at the highest temperature, then determine the next highest temperature to which the device will be exposed. In Table 2 on page 5, find the temperature profile that most closely matches the application. For example, the ambient temperature of a system cycles between 100°C (25% of the time) and 50°C (75% of the time). No forced ventilation cooling system is in use. An APA600-PQ208A FPGA operates in the system, dissipating 1W. The package thermal resistance (junction-to-ambient) in still air is 20°C/W, indicating that the junction temperature of the FPGA will be 120°C (25% of the time) and 70°C (75% of the time). The entry in Table 2 on page 5 , which most closely matches the application, is 25% at 125°C with 75% at 110°C. Performance retention in this example is at least 16.0 years. Note that exceeding the stated retention period may result in a performance degradation in the FPGA below the worst-case performance indicated in the Actel Timer. To ensure that performance does not degrade below the worst- case values in the Actel Timer, the FPGA must be reprogrammed within the performance retention period. In addition, note that performance retention is independent of whether or not the FPGA is operating. The retention period of a device in storage at a given temperature will be the same as the retention period of a device operating at that junction temperature. Table 1 Absolute Maximum Ratings* Parameter Condition Minimum Maximum Units Supply Voltage Core (VDD)– 0 . 3 3 . 0 V Supply Voltage I/O Ring (VDDP)– 0 . 3 4 . 0 V DC Input Voltage –0.3 V DDP + 0.3 V PCI DC Input Voltage –1.0 V DDP + 1.0 V PCI DC Input Clamp Current (absolute) V IN < –1V or VIN = VDDP + 1V 10 mA LVPECL Input Voltage –0.3 V DDP + 0.5 V GND 00 V Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Automotive-Grade ProASICPLUS Flash Family FPGAs Automotive Supplement 5 Table 2 Performance Retention Time at TJ 110°C or below Time at T J 125°C or below Minimum Program Retention (Years) 100% 0% 20.0 99% 1% 19.8 98% 2% 19.6 95% 5% 19.0 90% 10% 18.2 85% 15% 17.4 80% 20% 16.7 75% 25% 16.0 70% 30% 15.4 60% 40% 14.3 50% 50% 13.3 25% 75% 11.4 0% 100% 10.0 Table 3 Nominal Supply Voltages Mode V DD VDDP 2.5V Output 2.5V 2.5V 3.3V Output* 2.5V 3.3V Note: *Automotive-grade ProASICPLUS devices do not support mixed-mode I/Os. Table 4 Recommended Maximum Operating Conditions for Programming and PLL Supplies* Parameter Condition Automotive UnitsMinimum Maximum VPP During Programming 15.8 16.5 V Normal Operation 0 16.5 V VPN During Programming –13.8 –13.2 V Normal Operation –13.8 0 V I PP During Programming 25 mA IPN During Programming 10 mA AVDD V DD VDD V AGND GND GND V Note: *Devices should not be operated outside the Recommended Operating Conditions.
Automotive-Grade ProASICPLUS Flash Family FPGAs
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Table 5 Recommended Operating Conditions* Parameter Symbol Limits Automotive DC Supply Voltage (2.5V I/Os) V DD & VDDP 2.5V ± 5% DC Supply Voltage (3.3V I/Os) V DDP VDD 3.3V ± 5% 2.5V ± 5% Operating Junction Temperature Range T J -40°C to125°C Note: *Devices should not be operated outside the Recommended Operating Conditions. Table 6 DC Electrical Specifications (VDD and VDDP = 2.5V ±5%) Symbol Parameter Conditions Automotive1 Min. Typ. Max. Units VOH Output High Voltage High Drive (OB25LPH) Low Drive (OB25LPL) IOH = –6 mA IOH = –12 mA IOH = –24 mA IOH = –3 mA IOH = –6 mA IOH = –8 mA 2.1 2.0 1.7 2.1 1.9 1.7 V V OL Output Low Voltage High Drive (OB25LPH) Low Drive (OB25LPL) IOL = 8 mA IOL = 15 mA IOL = 24 mA IOL = 4 mA IOL = 8 mA IOL = 15 mA 0.2 0.4 0.7 0.2 0.4 0.7 V V IH Input High Voltage 1.7 V DDP + 0.3 V VIL Input Low Voltage –0.3 0.7 V RWEAKPULLUP Weak Pull-up Resistance (OTB25LPU) VIN ≥ 1.25V 6 56 k Ω HYST Input Hysteresis Schmitt 0.3 0.35 0.45 V IIN Input Current with pull up (V IN = GND) –240 – 20 µA without pull up (VIN = GND or VDD) –50 50 µA IDDQ Quiescent Supply Current (standby) VIN = GND2 or VDD 5.0 20 mA IOZ Tristate Output Leakage Current VOH = GND or VDD –50 50 µA IOSH Output Short Circuit Current High High Drive (OB25LPH) Low Drive (OB25LPL) V IN = VSS VIN = VSS –120 –100 mA IOSL Output Short Circuit Current Low High Drive (OB25LPH) Low Drive (OB25LPL) V IN = VDDP VIN = VDDP 100 mA CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF Notes: 1. All process conditions. Junction Temperature: –40 to +125°C. 2. No pull-up resistor.
Automotive-Grade ProASICPLUS Flash Family FPGAs Automotive Supplement 7 Table 7 DC Electrical Specifications (VDDP = 3.3V ±5% and VDD 2.5V ±5%) Symbol Parameter Conditions Automotive1 UnitsMin. Typ. Max. VOH Output High Voltage 3.3V I/O, High Drive (OB33P) 3.3V I/O, Low Drive (OB33L) IOH = –14 mA IOH = –24 mA IOH = –6 mA IOH = –12 mA 0.9∗VDDP 2.4 0.9∗VDDP 2.4 V VOL Output Low Voltage 3.3V I/O, High Drive (OB33P) 3.3V I/O, Low Drive (OB33L) IOL = 15 mA IOL = 20 mA IOL = 28 mA IOL = 7 mA IOL = 10 mA IOL = 15 mA 0.1VDDP 0.4 0.7 0.1VDDP 0.4 0.7 V VIH Input High Voltage 3.3V LVTTL/LVCMOS 2 V DDP + 0.3 V VIL Input Low Voltage 3.3V LVTTL/LVCMOS –0.3 0.8 V RWEAKPULLUP Weak Pull-up Resistance (IOB33U) VIN ≥ 1.5V 7 43 k Ω RWEAKPULLUP Weak Pull-up Resistance (IOB25U) VIN ≥ 1.5V 7 43 k Ω IIN Input Current with pull up (V IN = GND) –300 –40 µA without pull up (VIN = GND or VDD) –50 50 µA IDDQ Quiescent Supply Current (standby) VIN = GND2 or VDD 5.0 20 mA IOZ Tristate Output Leakage Current VOH = GND or VDD –10 10 µA IOSH Output Short Circuit Current High 3.3V High Drive (OB33P) 3.3V Low Drive (OB33L) V IN = GND VIN = GND –200 –100 mA IOSL Output Short Circuit Current Low 3.3V High Drive 3.3V Low Drive V IN = VDD VIN = VDD 200 100 mA CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF Notes: 1. All process conditions. Junction Temperature: –40 to +125°C. 2. No pull-up resistor.
Automotive-Grade ProASICPLUS Flash Family FPGAs
8 Automotive Supplement
Table 8 DC Specifications (3.3V PCI Revision 2.2 Operation)1 Symbol Parameter Condition Automotive2 UnitsMin. Max. VDD Supply Voltage for Core 2.375 2.625 V VDDP Supply Voltage for I/O Ring 3.135 3.465 V VIH Input High Voltage 0.5V DDP VDDP + 0.5 V VIL Input Low Voltage –0.5 0.3V DDP V IIPU Input Pull-up Voltage3 0.7VDDP V IIL Input Leakage Current4 0 < VIN < VCCI –50 50 µA VOH Output High Voltage I OUT = –500 µA 0.9V DDP V VOL Output Low Voltage I OUT = 1500 µA 0.1V DDP V CIN Input Pin Capacitance (except CLK) 10 pF CCLK CLK Pin Capacitance 5 12 pF Notes: 1. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cells only. 2. All process conditions. Junction Temperature: –40 to +125°C. 3. This specification is guaranteed by design. It is the minimu m voltage to which pull-up resistors are calculated to pull a floated network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum current at this input voltage. 4. Input leakage currents include hi-Z output leakage fo r all bidirectional buffers with tristate outputs.
Automotive-Grade ProASICPLUS Flash Family FPGAs Automotive Supplement 9 Table 9 AC Specifications (3.3V PCI Revision 2.2 Operation) Symbol Parameter Condition Automotive UnitsMin. Max. IOH(AC) Switching Current High 0 < V OUT ≤ 0.3VCCI * –12VCCI mA 0.3VCCI ≤ VOUT < 0.9VCCI * (–17.1 + (VDDP – VOUT)) mA 0.7VCCI < VOUT < VCCI * See equation C – page 124 of the PCI Specification document rev. 2.2 (Test Point) V OUT = 0.7VCC * –32VCCI mA IOL(AC) Switching Current Low V CCI > VOUT ≥ 0.6VCCI * 16VDDP mA 0.6VCCI > VOUT > 0.1VCCI 1 (26.7VOUT)m A 0.18VCCI > VOUT > 0* See equation D – page 124 of the PCI Specification document rev. 2.2 (Test Point) V OUT = 0.18VCC 38VCCI mA ICL Low Clamp Current –3 < V IN ≤ –1 –25 + (V IN + 1)/0.015 mA ICH High Clamp Current V CCI + 4 > VIN ≥ VCCI + 1 25 + (VIN – VDDP – 1)/0.015 mA slewR Output Rise Slew Rate 0.2V CCI to 0.6VCCI load* 14 V / n s slewF Output Fall Slew Rate 0.6V CCI to 0.2VCCI load* 14 V / n s Note: * Refer to the PCI Specification document rev. 2.2. pin output buffer 1/2 in. max 10 pF 1kΩ pin output buffer 10 pF 1kΩ Pad Loading Applicable to the Rising Edge PCI Pad Loading Applicable to the Falling Edge PCI
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