AP7217A DIODES | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 10

Technical content

3.3V 600mA CMOS LDO AP7217A Rev. 1 1 of 10 A P R I L 2 0 0 8 www.diodes.com © Diodes Incorporated Features General Description The AP7217A low-dropout linear regulator operates from a 3.3V to 5.5V supply and delivers a guaranteed 600mA (min) continuous load current.

  • Very Low Dropout Voltage
  • Low Current Consumption: Typ. 50μA
  • Output Voltage: 3.3V
  • Guaranteed 600mA (min) Output The high-accuracy output voltage is preset to an internally trimmed voltage. An active-low open-drain reset output remains asserted for at least 200ms (TYP) after output voltage reaches regulation.
  • Input Range up to 5.5V
  • Current Limiting
  • Stability with Low ESR Capacitors
  • Thermal shutdown Protection
  • Low Temperature Coefficient The space-saving SOP-8L and SOP-8L-EP packages are suitable for “pocket” and hand-held application. • SOP-8L and SOP-8L-EP: Available in “Green” Molding Compound (No Br, Sb)
  • Lead Free Finish/ RoHS Compliant (Note 1)

Applications

  • HD/ Blue Ray DVD & MP3/4 Players
  • CD and MP3 Players
  • Cellular and PCS Phones
  • Digital Still Camera
  • Hand-Held Computers

Ordering Information

S : SOP-8L Output voltage Package 33 : 3.3V -U : Tube PackingLead Free G : Green -13 : Tape & Reel XX SP : SOP-8L-EP Tube 13” Tape and Reel Device Package Code Packaging (Note 2) Quantity Part Number Suffix Quantity Part Number Suffix AP7217A-XXS S SOP-8L 100 -U 2500/Tape & Reel -13 AP7217A-XXSP SP SOP-8L-EP 100 -U 2500/Tape & Reel -13 Notes: 1. EU Directive 2002/95/EU (RoHS). All applicable RoHS exemptions applied, see EU Directive 2002/95/EU Annex Notes. 2. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.

3.3V 600mA CMOS LDO AP7217A Rev. 1 2 of 10 A P R I L 2 0 0 8 www.diodes.com © Diodes Incorporated Pin Assignments EN AP7217A VROUT GND VIN GND VD ( Top View ) OUTGND GND SOP-8L EN VROUT GND VIN GND VD ( Top View ) OUTGND GND SOP-8L-EP Pin Descriptions Pin Name Pin No. Function GND 1, 3, 5, 7 Ground VROUT 2 Voltage Output VIN 4 Supply Voltage VDOUT 6 VD Output (Reset on I/P) EN 8 Enable (VR On/Off)

3.3V 600mA CMOS LDO AP7217A Rev. 1 3 of 10 A P R I L 2 0 0 8 www.diodes.com © Diodes Incorporated Block Diagram Enable Bandgap Current Limit ERROR AMP 1.2V R4VD Comp. EN VDOUT GND VROUT VIN On Off Absolute Maximum Ratings Symbol Parameter Rating Unit ESD HBM Human Body Model ESD Protection 3.5 KV ESD MM Machine Model ESD Protection 500 V VIN Input Voltage +6 V IOUT Output Current PD/ (VIN-VO) mA VROUT Output Voltage GND - 0.3 ~ VIN+ 0.3 V SOP-8L 1010 PD Power Dissipation SOP-8L-EP 1650 mW TJ Operating Junction Temperature Range -40 to +125 ºC Recommended Operating Conditions Symbol Parameter Min Max Unit VIN Input Voltage 3.3 5.5 V IOUT Output Current 0 600 mA TA Operating Ambient Temperature -40 85 ºC

3.3V 600mA CMOS LDO AP7217A Rev. 1 4 of 10 A P R I L 2 0 0 8 www.diodes.com © Diodes Incorporated

Electrical Characteristics

(TA = 25°C, CIN = 1µF, COUT = 1µF, VEN = VIN, unless otherwise noted) Symbol Parameter Test Conditions Min Typ. Max Unit IQ Quiescent Current IO = 0mA - 50 80 μA ISTB Standby Current VEN = Off VIN = 5.0V 15 25 μA Output Voltage Accuracy IO = 30mA, VIN = 5V 3.234 3.300 3.366 V VROUT VOUT Temperature Coefficient -40°C to 85°C, IOUT = 30mA ±100 ppm / oC IOUT = 300mA 350 400 VDROPOUT Dropout Voltage IOUT = 600mA 800 900 mV IOUT Maximum Output Current VIN = 5.3V 600 mA ILIMIT Current Limit VIN = 5.3V 750 mA Ishort Short Circuit Current VIN = 5.3V 50 mA ΔVLINE/ΔVIN/VOUT Line Regulation 4.3V ≤ VIN ≤ 5.5V; IOUT = 30mA 0.01 ±0.2 %/V ΔVOUT Load Regulation 1mA ≤ IOUT ≤ 100mA, VIN = 5.3V 15 50 mV PSRR Power Supply Rejection V IN = 4.3V+ 0.5Vp-pAC, IOUT = 50mA F = 1KHz 55 dB VEH Output ON 1.6 V VEL EN Input Threshold Output OFF 0.25 V IEN Enable Pin Current -0.1 0.1 μA VDF Detect fall voltage 3.23 3.3 3.37 V VD Hysteresis Range VHysteresis VDF x1.02 VDF x1.05 VDF x1.08 V IVDout VD Supply Current VDout = 0.5V V IN = 2.0V 3.0V mA tRP V DOUT Delay Time VIN = 1.8V to VDF+ 1V 180 200 - mSec SOP-8L (Note 3) 134 θJA Thermal Resistance Junction-to-Ambient SOP-8L-EP (Note 4) 82 ºC/W SOP-8L (Note 3) 28 θJC Thermal Resistance Junction-to-Case SOP-8L-EP (Note 4) 12 ºC/W Notes: 3. Test condition for SOP-8L: Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layo ut. 4. Test condition for SOP-8L-EP: Device mounted on 2oz c opper, minimum recommended pad layout on top & bottom layer with thermal vias, double sided FR-4 PCB.

3.3V 600mA CMOS LDO AP7217A Rev. 1 5 of 10 A P R I L 2 0 0 8 www.diodes.com © Diodes Incorporated Typical Application AP7217A VIN VDOUT VOUT ENGND 100K VDOUT VIN CIN 1uF COUT 1uF ON OFF VROUT Typical Performance Characteristics Output Current vs. Dropout Voltage (Vout=3.3V) 100 200 300 400 500 600 700 800 900 30mA 100mA 300mA 600mA Output Current Dropout Voltage (mV) Input Voltage vs. Max Iout 100 200 300 400 500 600 700 800 Input Voltage Max Iout (mA) Quiescent Current vs. Temperature Temperature Quiescent Current (uA) Quiescent Current vs. Input Voltage 3.6V 56V 58V 61V 5.5V Input Voltage Quiescent Current (uA)

3.3V 600mA CMOS LDO AP7217A Rev. 1 6 of 10 A P R I L 2 0 0 8 www.diodes.com © Diodes Incorporated Typical Performance Characteristics (Continued) Short Current vs. Input Voltage 3.6V 4.3V 5V 5.3V 5.5V Input Voltage Short Current (mA) Short Current vs. Temperature (Vin=5.5V) -40℃ 25℃ 85℃ 105℃ Temperature Short Current (mA) Stand-by Current vs. Input Voltage 3.6V 4V 4.3V 5V 5.5V Input Voltage Stand-by Current (uA) Stand-by Current vs. Temperature Temperature Stand-by Current (uA) Load Transient Response Load Transient Response

3.3V 600mA CMOS LDO AP7217A Rev. 1 7 of 10 A P R I L 2 0 0 8 www.diodes.com © Diodes Incorporated Timing Diagram 200mSec-TYP. VIN VDOUT EN VROUT 1.6V tRP Application Note Input Capacitor A 1μF ceramic capacitor is recommended to connect between IN and GND pins to decouple input po wer supply glitch and noise. The amount of the capacitance may be increased without limit. A lower ESR (Equivalent Series Re sistance) capacitor allows the use of less capacitance, while higher ESR type requires more capacitance. This input capacitor must be located as close as possible to the device to assure input stability and less noise. For PCB layout, a wide copper trace is required for both IN and GND. Output Capacitor The output capacitor is required to stabilize and help the transient response of the LDO. The AP7217A is designed to have excellent transient response for most applications with a small amount of output capacitance. The AP7217 is stable with any small ceramic output capacitors of 1.0μF or higher value, and the temperature coefficients of X7R or X5R type. Additional capacitance helps to reduce un dershoot and overshoot during transient. For PCB layout, the output capacitor must be placed as close as possible to OUT and G ND pins, and keep the leads as short as possible. ENABLE/SHUTDOWN Operation The AP7217A is turned on by setting the EN pin high, and is turned off by pulling it low. If this feature is not used, the EN pin should be tied to IN pin to keep the regulator output on at all time. To ensure proper operation, the signal source used to drive the EN pin must be able to swi ng above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under V IL and VIH. VR OUT VD OUT EN=0 0V Φ EN=1 3.3V Φ Thermal Considerations Thermal Shutdown Protection limits power dissipation in AP7217A. When the operation junction temperature exceeds 150°C, the Over Temperature Protection circuit starts the thermal shutdown function and turns the pass element off. The pass element turn on again after the junction temperature cools by 40°C. For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The power dissipation definition in device is: PD = (VIN − VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature differenc e between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) - TA ) / θJA Where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance.

3.3V 600mA CMOS LDO AP7217A Rev. 1 8 of 10 A P R I L 2 0 0 8 www.diodes.com © Diodes Incorporated Current Limit Protection When output current at OUT pin is higher than current limit threshold, the current limit protection will be triggered and clamp the output current to approximately 750mA to prevent over-current and to protect the regulator from damage due to overheating. Short circuit protection When VROUT pin is shorted to GND or VR OUT voltage is less than 200mV, short circuit protection will be triggered and clamp the output current to approximately 50mA. VD OUT (reset output) ---Open-Drain Active-Low reset output--- In general, VD OUT is pulled up by a resistor (100Kohm) to V IN. The AP7217A microprocess (uP) supervisory circuitry asserts a guaranteed logic-low reset during power-up and power-down. Reset is asserted asserts when V IN is below the reset threshold and remain asserted for at least tRP after VIN rises above the reset threshold. As long as V IN is lower than the reset threshold, VDOUT remains at logic "0". When V IN become higher than V TH, a logic "1" is asserted after a time delay defined by tRP. Marking Information (1) SOP-8L 8 5 ( Top View ) Logo Part No. Internal code Year : "07" = 2007 "08" = 2008 Xth week : 01~52 ~14 7217A-33 YY WW X X G : Green (2) SOP-8L-EP 8 5 ( Top View ) Logo Part No. Internal code Year : "07" = 2007 "08" = 2008 Xth week : 01~52 ~14 7217A-33 YY WW X X E : SOP-8L-EPE G : Green Application Note (Continued) Vin Vout C Co ESR IN OUT GND AP7217A Iin Iout Iq

3.3V 600mA CMOS LDO AP7217A Rev. 1 9 of 10 A P R I L 2 0 0 8 www.diodes.com © Diodes Incorporated Package Information (All Dimensions in mm) (1) Package Type: SOP-8L 1.27typ 0.3/0.5 7°~9° 4.80/5.30 3.70/4.10 5.79/6.20 0.20typ 7°~9° 3.70/4.10 0.38/1.27 0.08/0.25 Gauge Plane 0.254 Seating Plane 0.35max. 45° Detail "A" Detail "A" 1.30/1.50 1.75max. Land Pattern Recommendation 0.78 (Unit: mm) 6x-1.27 8x-1.55 8x-0.60 5.4 (2) Package Type: SOP-8L-EP 1.27typ 0.3/0.5 7°~9° 4.80/5.30 3.70/4.10 5.79/6.20 0.20typ 7°~9° 3.70/4.10 0.38/1.27 0.08/0.25 Gauge Plane0.254 Seating Plane 0.35max. 45° Detail "A" Detail "A" 1.30/1.50 1.75max. Bottom View 2.4Ref. 3.3Ref. Exposed pad 8x-0.60 Land Pattem Recommendation Exposed pad 5.4 8x-1.55 6x-1.27

3.3V 600mA CMOS LDO AP7217A Rev. 1 10 of 10 A P R I L 2 0 0 8 www.diodes.com © Diodes Incorporated IMPORTANT NOTICE LIFE SUPPORT Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to any product herein. Diodes Incorporated does not assume any liability arising out of the application or use of any product described herein; neither does it convey any license under its patent rights, nor the rights of others. The user of products in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on our website, harmless against all damages. Diodes Incorporated products are not authorized for use as critical components in life support devices or systems without the expressed written approval of the President of Diodes Incorporated.