AP66200
Document overview
- Manufacturer or author: Diodes Incorporated
- PDF pages: 26
Technical content
Features
VIN 3.8 to 60V 2A Continuous Output Current VOUT Adjustable from 0.8V to 50V Enhanced Efficiency Mode with Bias Adjustable Switching Frequency. 500kHz Default Frequency Start-up with Pre-biased Output External Soft-Start with Tracking – Sequential, Ratiometric, or Absolute. Default Internal Soft-Start of 2ms Enable Pin with 5% tolerance Soft Discharge ±5% Power Good Detection with Internal Pull-up Resistor Overcurrent Protection (OCP) with Hiccup Thermal Protection Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) An automotive-compliant part is available under separate datasheet DIODES™ (AP66200Q) Pin Assignments PGND SS/TR BST PG 7 8 SW VIN VCC FB BIAS FS GND PGND 13141516 EN EPAD MSYNC VIN SW
Applications
General-purpose point-of-load DC/DC power conversion Telecommunication systems Distributed Power supplies Home Audio devices Consumer electronics Network supplies FPGA, DSP, and ASIC supplies Green electronics Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant . 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen - and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlori ne (<1500ppm total Br + Cl) and <1000ppm antimony compounds.
Document number: DS43720 Rev. 1 - 2 3 of 26 www.diodes.com December 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. AP66200 Pin Descriptions Pin Name Pin Number Function BIAS 1 The internal regulator will draw current from BIAS instead of VIN when BIAS is tied to a voltage higher than 4.4V. For output voltages of 5V to 15V this pin can be tied to VOUT. If this pin is tied to a supply other than VOUT use a 1µF local bypass capacitor on this pin. If no supply is available, this pin should tie to PGND. VCC 2 Internal power supply output pin to connect an additional capacitor. Connect a 1μF (typical) capacitor as close as possible to the VCC and PGND. This pin is not active when EN is low. VIN 3, 4 Power Input. VIN supplies the power to the IC, as well as the step-down converter switches. Drive VIN with a 3.8V to 60V power source. Bypass VIN to GND with a suitably large capacitor to eliminate noise on the input to the IC. See Input Capacitor. BST 5 High-Side Gate Drive Boost Input. BST supplies the drive for the high-side N-Channel MOSFET with a 0.1µF or greater capacitor from SW to BST to power the high side switch. SW 6, 7 Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter from SW to the output load. Note that a capacitor is required from SW to BST to power the high-side switch. PGND 8, 9 Power Ground. Connect PGND plane and EXPOSED PAD with as many via for thermal and efficiency performance. EN 10 Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator and low to turn it off. Connect directly to VIN for automatic startup. FS 11 This pin sets the oscillator switching frequency using a resistor, RFS, from FS pin to GND. The frequency of operation can be program from 300kHz to 2.5MHz. Connect FS to VCC or HIGH for a default frequency of 500kHz. MSYNC 12 Connect MSYNC to VCC or HIGH for forced PWM. Connect MSYNC to GND for PFM operation. Apply an external clock source for synchronization with positive edge trigger and PWM. PG 13 Open drain power-good output that is pulled to GND when the output voltage is out of its regulation limits or during soft-start interval. There is an internal 5MΩ pull-up resistor. SS/TR 14 Soft-start pin for the regulator. The SS/TR pin controls the soft-start and sequence of the output. A single capacitor from SS/TR to GND determines the output ramp rate. See the “Output Tracking and Sequencing” section for more application detail about soft-start, output tracking, and sequencing. If SS is tied to VCC, then an internal soft-start of 1.7ms will be used. FB 15 Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive divider connected to it from the output voltage to this pin. The feedback regulation voltage is 0.8V. See “Setting the Output Voltage”. GND 16 Analog ground that is used for the controller. Single point connection to the EPAD.
© 2022 Copyright Diodes Incorporated. All Rights Reserved. Figure 4. Functional Block Diagram
Document number: DS43720 Rev. 1 - 2 5 of 26 www.diodes.com December 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. AP66200 Absolute Maximum Ratings (@TA = +25°C, unless otherwise specified.) (Note 4) Symbol Parameter Rating Unit VIN Supply Voltage -0.3 to +72 V VSW Switch Node Voltage -1.0 to VIN +0.3 (DC) V VSW Switch Node Voltage -2.5 to VIN +2 (ns) V VEN Enable/UVLO Voltage -0.3V to +72 V VBST Bootstrap Voltage VSW -0.3 to VSW +6.0 V VBIAS Bias Voltage -0.3 to +18 V VCC VCC Voltage -0.3V to +6.0 V VFB Feedback Voltage -0.3V to +6.0 V VFS Frequency Adjust -0.3V to +6.0 V VPG Power Good Voltage -0.3V to +6.0 V VSS/TR Soft-start / Tracking -0.3V to +6.0 V VMSYNC Synchronization and MODE -0.3V to +6.0 V TST Storage Temperature -65 to +150 °C TJ Junction Temperature +150 °C TL Lead Temperature +300 °C ESD Susceptibility (Note 5) HBM Human Body Model ±2500 V CDM Charged Device Model ±1500 V Notes: 4. Stresses greater than the 'Absolute Maximum Ratings' specified above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not im plied. Device reliability may be affected by exposure to absolute maximum rating conditions for extended periods of time. 5. Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be take n when handling and transporting these devices. Thermal Resistance Symbol Parameter JEDEC (Note 6) EVM (Note 7) Unit θJA Junction to Ambient 46 30 °C/W θJC Junction to Case 5 5 °C/W Note: 6. Device mounted on FR-4 substrate, 1” sq. PC board, 2oz copper, with minimum recommended pad layout. 7. Device mounted on Diodes evaluation board. See user guide for more detail. Recommended Operating Conditions (@TA = +25°C, unless otherwise specified.) (Note 8) Symbol Parameter Min Max Unit VIN Supply Voltage 3.8 60 V VBIAS Supply Voltage 3.8 15 V TA Operating Ambient Temperature Range -40 +85 °C TJ Operating Junction Temperature Range -40 +125 °C Note: 8. The device function is not guaranteed outside of the recommended operating conditions.
Document number: DS43720 Rev. 1 - 2 6 of 26 www.diodes.com December 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. AP66200 Electrical Characteristics TA = +25°C, VIN = 48V, unless otherwise specified. Min/Max limits apply across the recommended junction temperature range, -40°C to +125°C, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit UVLO VCC Undervoltage Lockout Threshold — — 3.5 3.75 V Hysteresis — — 50 — mV ISHDN Shutdown Supply Current VEN = 0V, VIN=60V — 1.5 3.5 µA IQ Supply Current (Quiescent) VEN = 2.0V, VFB = 0.85V — 40 60 μA VCC Internal 5V supply VIN=6V to 60V 4.4 4.8 5.3 V IVCC VCC Output Current Limit — — 40 80 mA VBIAS Rising Edge Bias Switchover Voltage — — 4.5 4.7 V Falling Edge Bias Switchover Voltage — 4.05 4.25 — V RDS(ON)1 High-Side Switch On-Resistance — — 185 300 mΩ RDS(ON)2 Low-Side Switch On-Resistance — — 80 130 mΩ RDISCHARGE SW Soft Discharge On-Resistance — — 10 — kΩ ILIMIT HS Peak Current Limit VIN > 4.5V 2.7 3.2 3.7 A VIN < 4.5V — 2.1 — A IPFMPK PFM Peak Current Limit — 0.73 0.90 1.07 A IZC Zero Cross Current Threshold — — 0 — A ILIMIT_NEG LS Valley Current Limit — -2.1 -1.65 -1.20 A ISW_LKG Switch Leakage Current VEN = 0V, VSW =0V, VIN=60V — — 1 μA FSW Oscillator Frequency FS = VCC 440 500 560 kHz RFS =850kW 240 300 360 kHz RFS =62kW 2200 2500 2800 kHz MSYNC Synchronization Range — 300 — 2500 kHz VMSYNC_RISING MSYNC Rising Threshold — 1.4 — — V VMSYNC_FALLING MSYNC Falling Threshold — — — 0.8 V MSYNC PW MSYNC Pulse Width — — 250 — ns TON Minimum On-Time — — 110 — ns TOFF Minimum OFF-Time VFB=760mV — 120 — ns VFB Feedback Voltage VIN=3.8V to 60V 792 800 808 mV SS/TR=0.1V 0.09 0.11 0.13 V SS/TR=0.7V 0.68 0.7 0.71 V TSS Soft-Start Period SS/TR=VCC — 1.7 — ms ISS Soft-Start Charging Current SS/TR=0V 0.75 1.00 1.25 μA PGUV_FALL Undervoltage Falling Threshold Percent of Output Regulation, Fault 87 90 93 % PGUV_RISE Undervoltage Rising Threshold Percent of Output Regulation, Good 92 95 99 % PGOV_RISE Overvoltage Rising Threshold Percent of Output Regulation, Fault 107 110 114 % PGOV_FALL Overvoltage Falling Threshold Percent of Output Regulation, Good 102 105 108 % PG Pull-up PG Pull-up resistor — — 5 — MW PG Low PG Low Voltage IPG=-3mA — 0.1 0.3 V PG Delay PG Rising Edge Delay — — 1.5 — ms PG Falling Edge Delay — — 2 — μs VEN_TH EN Rising Threshold — 1.38 1.45 1.52 V Hysteresis — — 100 — mV REN EN Input Resistance — — 40 — MW TSHDN Thermal Shutdown (Note 9) — — 165 — °C THYS Thermal Hysteresis (Note 9) — — 20 — °C Note: 9. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.
Document number: DS43720 Rev. 1 - 2 13 of 26 www.diodes.com December 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. AP66200
Application Information
The AP66200 is a 2A current mode control, synchronous buck regulator with integrated power MOSFETs. Current mode control assures excellent line regulation, load regulation, and a wide loop bandwidth for fast response to load transients. Figure 1 and figure 4 depicts the typical application schematic and functional block diagram of AP66200. The buck controller drives the internal N -FETs. The buck regulator can operate from an unregulated DC source, such as a battery, with a voltage ranging from 3. 8V to 60V. The converter output can be regulated as low as 0.8V to as high as 50V. The feedback loop is compensated internally. See “Loop Compensation Design” for more details. Internal VCC Regulator An internal low dr opout regulator produces the 4.8 V supply from V IN that powers the drivers and the internal bias circuity. The VCC can supply enough current for the AP66200’s circuitry and must be bypassed to PGND with a minimum of 1µF ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the power MOSFET gate drivers. To improve efficiency, the interna l 5V regulator can also draw current from the BIA S pin when its voltage is at 4.5 V or higher. If BIAS is connected to an external supply far away, be sure to bypass with a local ceramic capacitor. If t he BIAS pin voltage is below 4.2 5V, the internal 5V regulator will source current from V IN. Application with high input voltage or high switching frequency where the internal 4.8V regulator pulls current from VIN will increase the die temperature. Enable, Soft-Start, Tracking, Sequencing, and Disable The enable (EN) input allows the user to control turning on or off the regulator. Once the voltage on the EN pin is above its threshold, the buck controller powers up and soft-start begins. The regulator does not allow the regulator to sink current durin g the soft-start period. The default time is 1.7 ms if SS/TR pin is tied to VCC. The soft-start time can be extended by connecting an external capacitor between SS/TR and GND. The capacitor along with an internal ISS of 1µA, sets the soft-start interval of the converter, TSS, according to equation below: CSS (nF) = 1.25*TSS (ms) Ratiometric tracking is achieved in figure 37 by using the same value for the soft-start capacitor on each power rail. IC#1SS/ TR IC#2SS/ TRCSS 3.3V Ratiometric Configuration Performance T 3.3V Figure 37. Ratiometic Configuration R3 and R4 should match with the ratio of feedback resistor divider of IC#2.
© 2022 Copyright Diodes Incorporated. All Rights Reserved. capacitor to PGND whenever the regulator is disabled. When the regulator remains enabled, the internal resistor disconnected from the output. device. AP66200 will exit Hiccup mode when the over current situation is resolved. Figure 40. Setting the Input UVLO
© 2022 Copyright Diodes Incorporated. All Rights Reserved. Figure 41. Output Current Derating Curve vs. Ambient Temperature, VIN = 12V voltage is within ±5% of its regulation. Any fault condition forces PG low. There is an internal 5MΩ pull-up resistor.
© 2022 Copyright Diodes Incorporated. All Rights Reserved. Figure 42. Feedback Divider Network Table 1 Recommended Component Selection Alternatively, the frequency of operation can be synchronized from 300kHz to 2.5MHz with an external signal applied to the MSYNC pin. It is recommended to use a MSYNC pulse width of at least 250ns. signal to a voltage output. The voltage loop is internally compensated with the 50pF and 320kΩ RC network that can support most applications. dotted lines illustrate the sum of the compensation ramp and the current-sense amplifier’s output.
© 2022 Copyright Diodes Incorporated. All Rights Reserved. Figure 43. CCM Operation Waveforms when the output voltage drops 2.5% below the nominal voltage.
8 CYCLES
Figure 44. PFM Operation Waveforms
Document number: DS43720 Rev. 1 - 2 19 of 26 www.diodes.com December 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. AP66200 Application Information (continued) Input Capacitor The input capacitor reduces the surge current drawn from the input supply and the switching noise from the device. The input capacitor has to sustain the ripple current produced during the on time on the upper MOSFET. It must hence have a low ESR to minimize the losses. The RMS current rating of the input capacitor is a critical parameter that must be higher than the RMS input current. As a ru le of thumb, select an input capacitor which has RMS rating that is greater than half of the maximum load current. Due to large d i/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must be surge prote cted. Otherwise, cap acitor failure could occur. For most applications, a 10µF ceramic capacitor is sufficient and 0.1 µF parallel capacitor is also recommended for improving the stability. Inductor Calculating the inductor value is a critical factor in designing a buck converter. For most designs, the following equation can be used to calculate the inductor value: SWLIN OUTINOUT fΔIV )V(VVL Where LΔI is the inductor ripple current and fSW is the buck converter switching frequency. Choose the inductor ripple current to be 30% to 40% of the maximum load current. The maximum inductor peak current is calculated from: ΔIII L LOADL(MAX) Peak current determines the required saturation current rating, which influences the size of the inductor. Saturating the inductor decreases the converter efficiency while increasing the temperatures of the inductor and the internal MOSFETs. Hence choosing an inductor w ith appropriate saturation current rating is important. An inductor with a DC current rating of at least 25% higher than the maximum load current is recommended for most applications. For highest efficiency, the inductor’s DC resistance should be as low as possible. Use a larger inductance for improved efficiency under light load conditions. Output Capacitor The output capacitor keeps the output voltage ripple small, ensures feedback loop stability and reduces the overshoot of the output voltage. The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it supplies the current to the load. The converter recognizes the load transient and sets the duty cycle to maximum, but the cur rent slope is limited by the inductor value. ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be approximate from the equation below: )8f 1 (ESR*ΔIVout SW inductorcapacitor OC An output capacitor with ample capacitance and low ESR is the best option. For most applications, a 22µF ceramic capacitor will be sufficient. out out 2inductor out o V)V V(Δ ΔIL(I C Where ΔV is the maximum output voltage overshoot. Bootstrap The internal driver of the HS FET is equipped with a BST undervoltage detection (UV) circuit. In the event that the voltage difference between BST and SW falls below 2V, the UV detection circuit allows the LS FET on for 400ns to recharge the bootstrap capacitor. Self Bias Mode For highest possible efficiency operation, it is recommended to connect the BIAS pin directly to Vout or other external suppl y in the range of 4.5V to 15V. In this condition, the internal LDO will source from the BIAS voltage to mi nimize the power dissipation. Therefore, the overall efficiency is improved.
Document number: DS43720 Rev. 1 - 2 20 of 26 www.diodes.com December 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. AP66200
Document number: DS43720 Rev. 1 - 2 22 of 26 www.diodes.com December 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. AP66200 Application Information (continued) Compensation design goals are the following: 1. Crossover frequency, fc, of approximately 1/10th of the switching frequency. 2. Phase margin > 40. 3. Gain margin > 10dB in magnitude. The loop gain at the crossover frequency has a unity gain. Therefore, the value of the top feedback resistance is determined by: 𝑅1 = 127𝑘 𝐶𝑜𝑓𝐶𝑉𝑂𝑈𝑇 Where, CO is the total output capacitance seen by the regulator. This may include ceramic high freq uency decoupling and bulk output capacitors. Ceramic will have derating factor by approximately 40% depending on dielectric, voltage stress, and thermal. An additional zero contribution due to R1 and C4 can boost the phase margin. Put the compensator zero between 1/2fc to fc frequency. 𝐶4 = 1 2𝜋𝑓𝑐𝑅1
© 2022 Copyright Diodes Incorporated. All Rights Reserved.
- The AP66200 is a high switching frequency converter. Hence , attention must be paid to the switching currents interference in the layout.
- Place the input capacitors as closely across VIN and GND as possible.
- Place the inductor as close to SW as possible.
- Place the output capacitors as close to GND as possible.
- Place the feedback components as close to FB as possible.
- If using four or more layers, use at least the 2nd and 3rd layers as GND to maximize thermal performance.
- Add as many vias as possible around both the GND pin and under the GND plane for heat dissipation to all the GND layers.
- Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers.
- See Figure 47 for more details.
Figure 47. PC Board Layout
Document number: DS43720 Rev. 1 - 2 24 of 26 www.diodes.com December 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. AP66200 Ordering Information (Note 10) AP66200xx - 13 PackingPackage xx : xxx 13 : Tape & Reel Part Number Package Code Package Identification Code Tape and Reel Quantity Part Number Suffix AP66200FVBW-13 FVBW U-QFN4040-16/SWP (Type UXB) F2 3000 -13 Marking Information ( Top View ) Y W X XX XX : Identification Code X : Internal Code Y : Year : 0~9 W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week Part Number Package Identification Code AP66200FVBW-13 U-QFN4040-16/SWP (Type UXB) F2 U-QFN4040-16/SWP (Type UXB)
Document number: DS43720 Rev. 1 - 2 25 of 26 www.diodes.com December 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. AP66200 Package Outline Dimensions Please see http://www.diodes.com/package-outlines.html for the latest version. U-QFN4040-16/SWP (Type UXB) U-QFN4040-16/SWP (Type UXB) Dim Min Max Typ A 0.57 0.63 0.60 A1 0.00 0.05 0.02 A3 -- -- 0.15 b 0.25 0.35 0.30 b1 -- -- 0.15 D 3.95 4.05 4.00 D2 2.40 2.60 2.50 E 3.95 4.05 4.00 E2 2.40 2.60 2.50 e -- -- 0.65 L 0.35 0.45 0.40 L1 -- -- 0.25 z 0.850 0.900 0.875 All Dimensions in mm Suggested Pad Layout Please see http://www.diodes.com/package-outlines.html for the latest version. U-QFN4040-16/SWP (Type UXB) Dimensions Value (in mm) C 0.650 G 0.250 G1 0.250 X 0.400 X1 2.350 X2 2.600 Y 0.600 Y1 2.350 Y2 2.600 Y3 4.300 Mechanical Data Moisture Sensitivity: Level 1 per J-STD-020 Terminals: Finish – Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 Weight: 34.54 grams (Approximate) D E e b L A A1 A3 ( Pin #1 ID) Seating Plane z( 8x) e 0.650 R0.200 C X(16x) Y(16x) G
Document number: DS43720 Rev. 1 - 2 26 of 26 www.diodes.com December 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. AP66200 IMPORTANT NOTICE 1. DIODES INCORPORATED (Diodes) AND ITS SUBSIDIARIES MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICUL AR PURPOSE OR NON -INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes’ products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. This document is intended for skilled and technically trained engin eering customers and users who design with Diodes’ products. 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