AP64501Q

Online Datasheet

Read AP64501Q online.

Document overview

Manufacturer or author: Diodes Incorporated
PDF pages: 26

Technical content

Features

AEC-Q100 Qualified with the Following Results ▪ Device Temperature Grade 1: -40°C to +125°C TA Range ▪ Device HBM ESD Classification Level H2 ▪ Device CDM ESD Classification Level C5
VIN: 3.8V to 40V
5A Continuous Output Current
0.8V ± 1% Reference Voltage
25µ A Low Quiescent Current (Pulse Frequency Modulation)
570kHz Switching Frequency
Programmable Soft-Start Time
Up to 85% Efficiency at 5mA Light Load
Proprietary Gate Driver Design for Best EMI Reduction
Frequency Spread Spectrum (FSS) to Reduce EMI
Low-Dropout (LDO) Mode
Precision Enable Threshold to Adjust UVLO
Protection Circuitry ▪ Undervoltage Lockout (UVLO) ▪ Output Overvoltage Protection (OVP) ▪ Cycle-by-Cycle Peak Current Limit ▪ Thermal Shutdown
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
The AP64501Q is suitable for automotive applications requiring specific change control; this part is AEC-Q100 qualified, PPAP capable, and manufactured in IATF 16949 certified facilities. https://www.diodes.com/quality/product-definitions/ Pin Assignments EXPOSED PAD 4 5 8BST VIN EN SS FB COMP GND SW (Top View) SO-8EP

Applications

Automotive power systems
Automotive infotainments
Automotive instrument clusters
Automotive telematics
Automotive lighting controls
Advanced driver assistance systems Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.

Document number: DS42749 Rev. 2 - 2 3 of 26 www.diodes.com December 2024 © 2024 Copyright Diodes Incorporated. All Rights Reserved. AP64501Q Pin Descriptions Pin Name Pin Number Function BST 1 High-Side Gate Drive Boost Input. BST supplies the drive for the high -side N-Channel power MOSFET. A 100nF capacitor is recommended from BST to SW to power the high-side driver. VIN 2 Power Input. VIN supplies the power to the IC as well as the step-down converter power MOSFETs. Drive VIN with a 3.8V to 40V power source. Bypass VIN to GND with a suitably large capacitor to eliminate noise due to the switching of the IC. See Input Capacitor section for more details. EN 3 Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator and low to turn it off. Connect to VIN or leave floating for automatic startup. The EN has a precision threshold of 1.18V for programing the UVLO. See Enable section for more details. SS 4 Soft-start. Place a ceramic capacitor from this pin to ground to program soft-start time. An internal 4μA current source pulls the SS pin to VCC. See Programming Soft-Start Time section for more details. FB 5 Feedback sensing terminal for the output voltage. Connect this pin to the resistive divider of the output. See Setting the Output Voltage section for more details. COMP 6 Compensation. Connect an external RC network to the COMP pin to adjust the loop response. See External Loop Compensation Design section for more details. GND 7 Power Ground. SW 8 Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter from SW to the output load. EXPOSED PAD 9 Heat dissipation path of the die. The exposed thermal pad must be electrically connected to GND and m ust be connected to the ground plane of the PCB for proper operation and optimized thermal performance.

Document number: DS42749 Rev. 2 - 2 5 of 26 www.diodes.com December 2024 © 2024 Copyright Diodes Incorporated. All Rights Reserved. AP64501Q Absolute Maximum Ratings (Note 4) (@ TA = +25° C, unless otherwise specified.) Symbol Parameter Rating Unit VIN Supply Pin Voltage -0.3 to +42.0 (DC) V VBST Bootstrap Pin Voltage VSW - 0.3 to VSW + 6.0 V VEN Enable/UVLO Pin Voltage -0.3 to +42.0 V VSS Soft-Start Pin Voltage -0.3 to +6.0 V VFB Feedback Pin Voltage -0.3 to +6.0 V VCOMP Compensation Pin Voltage -0.3 to +6.0 V VSW Switch Pin Voltage -0.3 to VIN + 0.3 (DC) V -2.5 to VIN + 2.0 (20ns) TST Storage Temperature -65 to +150 °C TJ Junction Temperature +160 °C TL Lead Temperature +260 °C ESD Susceptibility (Note 5) HBM Human Body Model ±2000 V CDM Charged Device Model ±1000 V Notes: 4. Stresses greater than the Absolute Maximum Ratings specified above can cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not im plied. Device reliability can be affected by exposure to absolute maximum rating conditions for extended periods of time. 5. Semiconductor devices are ESD sensitive and can be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices. Thermal Resistance (Note 6) Symbol Parameter Rating Unit θJA Junction to Ambient SO-8EP 45 ° C/W θJC Junction to Case SO-8EP 5 ° C/W Note: 6. Test condition for SO-8EP: Device mounted on FR-4 substrate, four-layer PC board, 2oz copper, with minimum recommended pad layout. Recommended Operating Conditions (Note 7) (@ TA = +25°C, unless otherwise specified.) Symbol Parameter Min Max Unit VIN Supply Voltage 3.8 40 V VOUT Output Voltage 0.8 VIN V TA Operating Ambient Temperature -40 +125 °C TJ Operating Junction Temperature -40 +150 °C Note: 7. The device function is not guaranteed outside of the recommended operating conditions.

Document number: DS42749 Rev. 2 - 2 6 of 26 www.diodes.com December 2024 © 2024 Copyright Diodes Incorporated. All Rights Reserved. AP64501Q Electrical Characteristics (@ TJ = +25° C, VIN = 12V, unless otherwise specified. Min/Max limits apply across the recommended operating junction temperature range, -40° C to +150° C, and input voltage range, 3.8V to 40V, unless otherwise specified.) Symbol Parameter Test Conditions Min Typ Max Unit ISHDN Shutdown Supply Current VEN = 0V — 1 — μA IQ Quiescent Supply Current VEN = Floating, R2 = OPEN, No Load, VBST - VSW = 5V — 25 — μA POR VIN Undervoltage Rising Threshold — — 3.5 3.7 V UVLO VIN Undervoltage Falling Threshold — — 3.1 — V RDS(ON)1 High-Side Power MOSFET On-Resistance (Note 8) — — 45 — mΩ RDS(ON)2 Low-Side Power MOSFET On-Resistance (Note 8) — — 20 — mΩ IPEAK_LIMIT HS Peak Current Limit (Note 8) — 6.8 8 9.2 A IVALLEY_LIMIT LS Valley Current Limit (Note 8) — — 9 — A IPFMPK PFM Peak Current Limit — — 950 — mA IZC Zero Cross Current Threshold — — 60 — mA fSW Oscillator Frequency — 500 570 640 kHz tON_MIN Minimum On-Time — — 100 — ns VFB Feedback Voltage CCM 0.792 0.800 0.808 V VEN_H EN Logic High Threshold — — 1.18 1.25 V VEN_L EN Logic Low Threshold — 1.03 1.09 — V IEN EN Input Current VEN = 1.5V — 5.5 — μA VEN = 1V 1 1.5 2 μA tSS Soft-Start Time CSS = 10nF — 4 — ms TSD Thermal Shutdown (Note 8) — — +160 — °C THys Thermal Shutdown Hysteresis (Note 8) — — +25 — °C Note: 8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.

Application Information

1 Pulse Width Modulation (PWM) Operation

The AP64501Q device is an automotive-compliant, 3.8V-to-40V input, 5A output, EMI friendly, fully integrated synchronous buck converter. Refer to the block diagram in Figure 3. The device employs fixed-frequency peak current mode control. The internal 570kHz clock’s rising edge initiates turning on the integrated high-side power MOSFET, Q1, for each cycle. When Q1 is on , the inductor current rises linearly and the device charges the output capacitor. The current across Q1 is sensed and converted to a voltage with a ratio of RT via the CSA block. The CSA output is combined with an internal slope compensation, SE, resulting in VSUM. When VSUM rises higher than the COMP node, the device turns off Q1 and turns on the low-side power MOSFET, Q2. The inductor current decreases when Q2 is on. On the rising edge of next clock cycle, Q2 turns off and Q1 turns on. This sequence repeats every clock cycle. The error amplifier generates the COMP voltage by comparing the voltage on the FB pin with an internal 0.8V reference. An increase in load current causes the feedback voltage to drop. The error amplifier thus raises the COMP voltage until the average inductor current matches the increased load current. This feedback loop regulates the output voltage. The internal slope compensation circuitry prevents subharmonic oscillation when the duty cycle is greater than 50% for peak current mode control. The peak current mode control simplifies the AP64501Q footprint.

2 Pulse Frequency Modulation (PFM) Operation

In heavy load conditions, the AP64501Q operates in forced PWM mode. As the load current decreases , the internal COMP node voltage also decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from decreasing any further. The voltage at which COMP is clamped corresponds to the 950mA PFM peak inductor current limit. As the load current approaches zero, the AP64501Q enters PFM mode to increase the converter power efficiency at light load conditions. When the inductor current decreases to 60mA, zero cross detection circuitry on the low-side power MOSFET, Q2, forces it off. The buck converter does not sink current from the output when the output load is light and while the device is in PFM. Because the AP64501Q works in PFM during light load conditions, it can achieve power efficiency of up to 85% at a 5mA load condition. The quiescent current of the AP64501Q is 25μA typical under a no-load, non-switching condition.

3 Enable

When disabled, the device shutdown supply current is only 1μA. When applying a voltage greater than the EN logic high threshold (typical 1.18V, rising), the AP64501Q enables all functions and the device initiates the soft-start phase. The EN pin is a high -voltage pin and can be directly connected to VIN to automatically start up the device as VIN increases. An internal 1.5µ A pull-up current source connected from the internal LDO- regulated VCC to the EN pin guarantees that if EN is left floating, the device still automatically enables once the voltage reaches the EN logic high threshold. The AP64501Q has a programmable soft-start time to prevent output voltage overshoot and inrush current. When the EN voltage falls below its logic low threshold (typical 1.09V, falling), the internal SS voltage discharges to ground and device operation disables. The EN pin can also be used to program the undervoltage lockout thresholds. See Undervoltage Lockout (UVLO) section for more details. Alternatively, a small ceramic capacitor can be added from EN to GND. When EN is not driven externally, this capacitor increases the time needed for the EN pin voltage to reach its logic high threshold, which delays the startup of the output voltage. This is useful when sequencing multiple power rails to minimize input inrush current. When the EN pin voltage starts from 0V, the amount of capacitance for a given delay time is approximated by: 𝐂𝐝[𝐧𝐅] ≈ 𝟏. 𝟐𝟕 ∙ 𝐭𝐝[𝐦𝐬] Eq. 1 Where:

Cd is the time delay capacitance in nF
td is the delay time in ms

5 Adjusting Undervoltage Lockout (UVLO)

high-side and low-side power MOSFETs turn off. on the EN pin along with an external resistive divider (R3 and R4) configures the VIN UVLO threshold voltages as shown in Figure 25. Figure 25. Programming UVLO

VON is the rising edge VIN voltage to enable the regulator and is greater than 3.7V
VOFF is the falling edge VIN voltage to disable the regulator and is greater than 3.3V

6 Output Overvoltage Protection (OVP)

continuing to increase. Once the output voltage decreases within 5% of its regulation, the low-side MOSFET turns off to exit OVP state.

7 Overcurrent Protection (OCP)

down time, the buck converter restarts powering up. Hiccup mode reduces the power dissipation in the overcurrent condition.

8 Thermal Shutdown (TSD)

9 Power Derating Characteristics

PD is the power dissipated by the regulator
θJA is the thermal resistance from the junction of the die to the ambient temperature The junction temperature, TJ, is given by: 𝐓𝐉 = 𝐓𝐀 + 𝐓𝐑𝐈𝐒𝐄 Eq. 5 Where:
TA is the ambient temperature of the environment For the SO-8EP package, the θJA is 45° C/W. The actual junction temperature should not exceed the maximum recommended opera ting junction temperature of +150° C when considering the thermal design. Figure 26 shows a typical derating curve versus ambient temperature.

Figure 26. Output Current Derating Curve vs. Ambient Temperature, VIN = 12V

10 Setting the Output Voltage

Table 1 shows a list of recommended component selections for common AP64501Q output voltages referencing Figure 1. Table 1. Recommended Components Selections

11 Programming Soft-Start Time

capacitor, CSS, from the SS pin to ground.

CSS is the capacitance in nF and is at least 10nF
tSS is the soft-start time in ms and is at least 4ms

12 Inductor

Calculating the inductor value is a critical factor in designing a buck converter. For most designs, the following equation can be used to calculate the inductor value: 𝐋 = 𝐕𝐎𝐔𝐓 ∙ (𝐕𝐈𝐍 − 𝐕𝐎𝐔𝐓) 𝐕𝐈𝐍 ∙ ∆𝐈𝐋 ∙ 𝐟𝐒𝐖 Eq. 8 Where:

∆IL is the inductor current ripple
fSW is the buck converter switching frequency For the AP64501Q, choose ∆IL to be 30% to 50% of the maximum load current of 5A. The inductor peak current is calculated by: 𝐈𝐋𝐏𝐄𝐀𝐊 = 𝐈𝐋𝐎𝐀𝐃 + ∆𝐈𝐋 𝟐 Eq. 9 Peak current determines the required saturation current rating, which influences the size of the inductor. Saturating the inductor decreases the converter efficiency while increasing the temperatures of the inductor and the internal power MOSFETs. Therefore, choosing an inductor with the appropriate saturation current rating is important. For most applications, it is recommended to select an inductor of approximately 1µ H to 10µ H with a DC current rating of at least 35% higher than the maximum load current. For highest efficiency, the inductor’s DC resistance should be less than 10mΩ. Use a larger inductance for improved efficiency under light load conditions.

13 Input Capacitor

The input capacitor reduces both the surge current drawn from the input supply as well as the switching noise from the device. The input capacitor must sustain the ripple current produced during the on -time of Q1. It must have a low ESR to minimize power dissipation due to the RMS input current. The RMS current rating of the input capacitor is a critical parameter and must be higher than the RMS input current. As a rul e of thumb, select an input capacitor with an RMS current rating greater than half of the maximum load current. Due to large dI/dt through the input capacitor, electrolytic or ceramic capacitors with low ESR should be used. If using a tantalum capacitor, it must be surge protected or else capacitor failure could occur. Using a ceramic capacitor of 20µ F or greater is sufficient for most applications.

14 Output Capacitor

The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces both the overshoots and undershoots of the output voltage during load transients. During the first few micro seconds of an increasing load transient, the converter recognizes the change from steady-state and enters 100% duty cycle to supply more current to the load. However, the inductor limits the change to increasing cu rrent depending on its inductance. Therefore, the output capacitor supplies the difference in current to the load during this time. Likewise, during the first few microseconds of a decreasing load transient, the converter recognizes the change from steady-state and sets the on-time to minimum to reduce the current supplied to the load. However, the inductor limits the change in decreasing current as well. Therefore, the output capacitor absorbs the excess current from the inductor during this time. The effective output capacitance, COUT, requirements can be calculated from the equations below. The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated by: 𝐕𝐎𝐔𝐓𝐑𝐢𝐩𝐩𝐥𝐞 = ∆𝐈𝐋 ∙ (𝐄𝐒𝐑 + 𝟏 𝟖 ∙ 𝐟𝐒𝐖 ∙ 𝐂𝐎𝐔𝐓) Eq. 10 Output capacitors with large capacitance and low ESR are the best option. For most applications, a total capacitance of 3 x 22 µ F using ceramic capacitors is sufficient. To meet the load transient requirements, the calculated COUT should satisfy the following inequality: 𝐂𝐎𝐔𝐓 > 𝐦𝐚𝐱 ( 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 ∆𝐕𝐎𝐯𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ 𝐕𝐎𝐔𝐓 , 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 ∆𝐕𝐔𝐧𝐝𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ (𝐕𝐈𝐍 − 𝐕𝐎𝐔𝐓)) Eq. 11 Where:

ITrans is the load transient
∆VOvershoot is the maximum output overshoot voltage
∆VUndershoot is the maximum output undershoot voltage

15 Bootstrap Capacitor and Low-Dropout (LDO) Operation

To ensure proper operation, a ceramic capacitor must be connected between the BST and SW pins to supply the drive voltage for the high -side power MOSFET. A 100nF ceramic capacitor is sufficient. If the bootstrap capacitor voltage falls below 2.3V, the boot undervoltage protection circuit turns Q2 on for 300ns to refresh the bootstrap capacitor and raise its voltage back above 2.55V. The bootstrap capacitor threshold voltage is always maintained to ensure enough driving capability for Q1. This operation may arise during long periods of no switching such as in PFM with light load conditions. Another event that requires the refreshing of the bootstrap capacitor is when the input voltage drops close to the output voltage. Under this condition, the regulator enters low-dropout mode by holding Q1 on for multiple clock cycles. To prevent the bootstrap capacitor from discharging, Q2 is forced to refresh. The effective duty cycle is approximately 100% so that it acts as an LDO to maintain the output voltage regulation.

16 External Loop Compensation Design

function to achieve good line regulation. Figure 27 shows the small signal model of the synchronous buck regulator. Figure 27. Small Signal Model of Buck Regulator

Tv(S) is the voltage loop
Ti(S) is the current loop
K(S) is the voltage sense gain
-Av(S) is the feedback compensation gain
He(S) is the current sampling function
Fm is the PWM comparator gain
Vin is the DC input voltage
D is the duty cycle
Rc is the ESR of the output capacitor, COUT
Ro is the output load resistance
v̂in is the AC small-signal input voltage
i ̂in is the AC small-signal input current
d̂ is the modulation of the duty cycle
i ̂L is the AC small signal of the inductor current
v̂o is the AC small signal of output voltage
v̂comp is the AC small signal voltage of the compensation network

16 External Loop Compensation Design (continued)

Figure 28. Type ll Compensator

High DC Gain
Gain Margin less than -10dB
Phase Margin greater than 45°
Loop Bandwidth Crossover Frequency (fc) less than 10% of fSW

Document number: DS42749 Rev. 2 - 2 19 of 26 www.diodes.com December 2024 © 2024 Copyright Diodes Incorporated. All Rights Reserved. AP64501Q Application Information (continued) The loop gain at the crossover frequency has unity gain. Therefore, the compensator resistance, R5, is determined by: 𝐑𝟓 = 𝟐𝛑 ∙ 𝐟𝐜 ∙ 𝐕𝐎𝐔𝐓 ∙ 𝐂𝐎 ∙ 𝐑𝐓 𝐠𝐦 ∙ 𝐕𝐅𝐁 = 𝟒. 𝟔𝟕𝐱𝟏𝟎𝟑[𝛀 𝐀] ∙ 𝐟𝐜 ∙ 𝐕𝐎𝐔𝐓 ∙ 𝐂𝐎𝐔𝐓 Eq. 17 Where:

gm is 0.15mS
RT is 0.089V/A
VFB is 0.8V
fc is the desired crossover frequency Be aware that most ceramic capacitors will degrade with voltage stress or temperature extremes. Refer to its datasheet and us e its worst case capacitance value for calculations. The compensation capacitors C5 and C6 are then equal to: 𝐂𝟓 = 𝐕𝐎𝐔𝐓 ∙ 𝐂𝐎𝐔𝐓 𝐈𝐎𝐔𝐓 ∙ 𝐑𝟓 Eq. 18 𝐂𝟔 = 𝐦𝐚𝐱 (𝐑𝐂 ∙ 𝐂𝐎 𝐑𝟓 , 𝟏 𝛑 ∙ 𝐟𝐬𝐰 ∙ 𝐑𝟓) Eq. 19 Where:
IOUT is the output load current The inclusion of C6 can increase gain margin and can decrease phase margin. In most cases, C6 is optional and may be omitted. The zero, z2, is optional as it can increase both the phase margin and gain bandwidth and can decrease gain margin. If used, place this zer o at around two to five times fC. Thus, C4 is in the approximate range of: 𝐂𝟒 = [ 𝟏 𝟏𝟎𝛑 ∙ 𝐟𝐂 ∙ 𝐑𝟏 , 𝟏 𝟒𝛑 ∙ 𝐟𝐂 ∙ 𝐑𝟏 ] Eq. 20

VIN = 12V
VOUT = 5V
IOUT = 5A
fSW = 570kHz
fc = 15kHz
R1 = 52.3kΩ
R2 = 10kΩ
L = 4.7µH
C2 = 3 × 22µF (Effectively, COUT ≈ 45µ F)
RC ≈ 1mΩ AP64501Q VIN EN SW BST FB GND INPUT 52.3kΩ C4 10kΩ L 4.7μH 100nF 3 x 22µF 2 x 10µF OUTPUT VOUT COMP SS Css 10nF VIN 12V

Figure 29. Example Circuit for Loop Compensation Calculations capacitors are used, their calculations are also required.

Document number: DS42749 Rev. 2 - 2 21 of 26 www.diodes.com December 2024 © 2024 Copyright Diodes Incorporated. All Rights Reserved. AP64501Q Application Information (continued) From Eq. 17, the value of R5 is calculated as: 𝐑𝟓 = 𝟒. 𝟔𝟕𝐱𝟏𝟎𝟑[𝛀 𝐀] ∙ 𝐟𝐜 ∙ 𝐕𝐎𝐔𝐓 ∙ 𝐂𝐎𝐔𝐓 = 𝟒. 𝟔𝟕𝐱𝟏𝟎𝟑[𝛀 𝐀] ∙ 𝟏𝟓𝐤𝐇𝐳 ∙ 𝟓𝐕 ∙ 𝟒𝟓𝛍𝐅 ≈ 𝟏𝟓. 𝟕𝟔𝐤𝛀 Choose a standard resistor value for R5 close to its calculated value. For example, choose R5 to be 15.8kΩ. From Eq. 18, C5 is calculated as: 𝐂𝟓 = 𝐕𝐎𝐔𝐓 ∙ 𝐂𝐎𝐔𝐓 𝐈𝐎𝐔𝐓 ∙ 𝐑𝟓 = 𝟓𝐕 ∙ 𝟒𝟓𝛍𝐅 𝟓𝐀 ∙ 𝟏𝟓. 𝟖𝐤𝛀 ≈ 𝟐. 𝟖𝐧𝐅 Choose a standard capacitor value for C5 close to its calculated value. For example, choose C5 to be 2.7nF. From Eq. 19, C6 is calculated as: 𝐂𝟔 = 𝐦𝐚𝐱 (𝐑𝐂 ∙ 𝐂𝐎𝐔𝐓 𝐑𝟓 , 𝟏 𝛑 ∙ 𝐟𝐬𝐰 ∙ 𝐑𝟓) = 𝐦𝐚𝐱 (𝟏𝐦𝛀 ∙ 𝟒𝟓𝛍𝐅 𝟏𝟓. 𝟖𝐤𝛀 , 𝟏 𝛑 ∙ 𝟓𝟕𝟎𝐤𝐇𝐳 ∙ 𝟏𝟓. 𝟖𝐤𝛀) ≈ 𝐦𝐚𝐱(𝟐. 𝟖𝐩𝐅, 𝟑𝟓. 𝟑𝐩𝐅) = 𝟑𝟓. 𝟑𝐩𝐅 C6 is optional. If used, choose a standard capacitor value for C6 close to its calculated value. For example, choose C6 to be 33pF. From Eq. 20, the approximate range of C4 is calculated as: 𝐂𝟒 = [ 𝟏 𝟏𝟎𝛑 ∙ 𝐟𝐂 ∙ 𝐑𝟏 , 𝟏 𝟒𝛑 ∙ 𝐟𝐂 ∙ 𝐑𝟏 ] = [ 𝟏 𝟏𝟎𝛑 ∙ 𝟏𝟓𝐤𝐇𝐳 ∙ 𝟓𝟐. 𝟑𝐤𝛀 , 𝟏 𝟒𝛑 ∙ 𝟏𝟓𝐤𝐇𝐳 ∙ 𝟓𝟐. 𝟑𝐤𝛀] C4 is optional. If used, choose a standard capacitor value for C4 that is close to its calculated range. For example, choose C4 to be 100pF.

Bandwidth is around 13.2kHz
Phase Margin is around 93.5°
Gain Margin is around -25.7dB

Figure 31. Closed-Loop Bandwidth Figure 32. Closed-Loop Phase Margin

The AP64501Q works at 5A load current so heat dissipation is a major concern in the layout of the PCB. 2oz copper for both the top and bottom
Place the input capacitors as closely across VIN and GND as possible.
Place the inductor as close to SW as possible.
Place the output capacitors as close to GND as possible.
Place the feedback components as close to FB as possible.
If using four or more layers, use at least the 2nd and 3rd layers as GND to maximize thermal performance.
Add as many vias as possible around both the GND pin and under the GND plane for heat dissipation to all the GND layers.
Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers.
See Figure 33 for more details.

Figure 33. Recommended PCB Layout

Ordering Information

SP : SO-8EP AP64501Q X - X 13 : Tape & Reel Package Packing Orderable Part Number Package Package Code Packing Qty. Carrier AP64501QSP-13 SO-8EP SP 4,000 13” Tape and Reel Marking Information SO-8EP AP64501Q (Top View) YY WW X X E Logo WW : Week : 01~52; 52 YY : Year : 19, 20, 21~ X X : Internal Code 8 7 6 5 1 2 3 4 represents 52 and 53 week E : SO-8EP Marking ID YY: Year: 24, 25, 26~ WW: Week: 01 to 52; 52 Represents 52 and 53 Week XX: Internal Code E: SO-8EP

Document number: DS42749 Rev. 2 - 2 25 of 26 www.diodes.com December 2024 © 2024 Copyright Diodes Incorporated. All Rights Reserved. AP64501Q Package Outline Dimensions Please see http://www.diodes.com/package-outlines.html for the latest version. SO-8EP SO-8EP Dim Min Max Typ A 1.40 1.50 1.45 A1 0.00 0.13 - b 0.30 0.50 0.40 C 0.15 0.25 0.20 D 4.85 4.95 4.90 E 3.80 3.90 3.85 E0 3.85 3.95 3.90 E1 5.90 6.10 6.00 e - - 1.27 F 2.75 3.35 3.05 H 2.11 2.71 2.41 L 0.62 0.82 0.72 N - - 0.35 Q 0.60 0.70 0.65 All Dimensions in mm Suggested Pad Layout Please see http://www.diodes.com/package-outlines.html for the latest version. SO-8EP Dimensions Value (in mm) C 1.270 X 0.802 X1 3.502 X2 4.612 Y 1.505 Y1 2.613 Y2 6.500 Mechanical Data

Moisture Sensitivity: Level 1 per J-STD-020
Terminals: Finish – Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208
Weight: 0.078 grams (Approximate) b e E1A 9° ( All side) 4° ±3° C Q N 45° R 0.1 D E L Seating Plane Gauge Plane F H EXPOSED PAD C X Y

Document number: DS42749 Rev. 2 - 2 26 of 26 www.diodes.com December 2024 © 2024 Copyright Diodes Incorporated. All Rights Reserved. AP64501Q IMPORTANT NOTICE 1. DIODES INCORPORATED (Diodes) AND ITS SUBSIDIARIES MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICUL AR PURPOSE OR NON -INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes ’ products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. This document is intended for skilled and technically trained engineering customers and users who design with Diodes’ products. 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All other trademarks are the property of their respective owners. © 2024 Diodes Incorporated. All Rights Reserved. www.diodes.com

Product Information

AP64501Q specifications and overview.

Summary

AUTOMOTIVE-COMPLIANT, 40V, 5A SYNCHRONOUS BUCK WITH PROGRAMMABLE SOFT-START TIME Rev. 1 - 2 December 2020

Description

AUTOMOTIVE-COMPLIANT, 40V, 5A SYNCHRONOUS BUCK WITH PROGRAMMABLE SOFT-START TIME Rev. 1 - 2 December 2020

Source title AP64501Q Datasheet(PDF) - Diodes Incorporated

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