AP64100 DIODES | Alldatasheet
Document overview
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Technical content
Features
VIN: 3.8V to 40V Output Voltage (VOUT): 0.8V to VIN 1A Continuous Output Current 0.8V ± 1% Reference Voltage 25µ A Low Quiescent Current (Pulse Frequency Modulation) Adjustable Switching Frequency: 100kHz to 2.2MHz External Clock Synchronization: 100kHz to 2.2MHz Up to 88% Efficiency at 5mA Light Load Proprietary Gate Driver Design for Best EMI Reduction Frequency Spread Spectrum (FSS) to Reduce EMI Low-Dropout (LDO) Mode Precision Enable Threshold to Adjust UVLO Protection Circuitry Undervoltage Lockout (UVLO) Output Overvoltage Protection (OVP) Cycle-by-Cycle Peak Current Limit Thermal Shutdown Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/ Pin Assignments EXPOSED PAD 4 5 8BST VIN EN RT/CLK FB COMP GND SW (Top View) SO-8EP (Standard)
Applications
Distributed Power Bus Supplies Power Tools and Laser Printers White Goods and Small Home Appliances Home Audio Network Systems Consumer Electronics General Purpose Point of Load Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.
Document number: DS43571 Rev. 1 - 2 3 of 26 www.diodes.com March 2021 © Diodes Incorporated AP64100 Pin Descriptions Pin Name Pin Number Function BST 1 High-Side Gate Drive Boost Input. BST supplies the drive for the high -side N-Channel power MOSFET. A 100nF capacitor is recommended from BST to SW to power the high-side driver. VIN 2 Power Input. VIN supplies the power to the IC as well as the step-down converter power MOSFETs. Drive VIN with a 3.8V to 40V power source. Bypass VIN to GND with a suitably large capacitor to eliminate noise due to the switching of the IC. See Input Capacitor section for more details. EN 3 Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator and low to turn it off. Connect to VIN or leave floating for automatic startup. The EN has a precision threshold of 1.18V for adjusting the UVLO. See Enable section for more details. RT/CLK 4 Resistor Timing and External Cloc k. This pin can be used to control the switching frequency by setting the internal oscillator frequency or by synchronizing to an external clock. Connect a resistor from RT/CLK to GND to set the internal oscillator frequency. An external clock can be input directly to the RT/CLK pin and t he internal oscillator synchronizes to the external clock freq uency using a PLL. If the external clock edges stop, the operating mode automatically returns to the resistor frequency setting. See Adjusting Switching Frequency section for more details. FB 5 Feedback sensing terminal for the output voltage. Connect this pin to the resistive divider of the output. See Setting the Output Voltage section for more details. COMP 6 Compensation. Connect an external RC network to the COMP pin to adjust the loop response. See External Loop Compensation Design section for more details. GND 7 Power Ground. SW 8 Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC fil ter from SW to the output load. EXPOSED PAD 9 Heat dissipation path of the die. The exposed thermal pad must be electrically connected to GND and m ust be connected to the ground plane of the PCB for proper operation and optimized thermal performance.
Figure 3. Functional Block Diagram
Document number: DS43571 Rev. 1 - 2 5 of 26 www.diodes.com March 2021 © Diodes Incorporated AP64100 Absolute Maximum Ratings (Note 4) (@ TA = +25° C, unless otherwise specified.) Symbol Parameter Rating Unit VIN Supply Pin Voltage -0.3 to +42.0 (DC) V VBST Bootstrap Pin Voltage VSW - 0.3 to VSW + 6.0 V VEN Enable/UVLO Pin Voltage -0.3 to +42.0 V VRT/CLK RT/CLK Pin Voltage -0.3 to +6.0 V VFB Feedback Pin Voltage -0.3 to +6.0 V VCOMP Compensation Pin Voltage -0.3 to +6.0 V VSW Switch Pin Voltage -0.3 to VIN + 0.3 (DC) V -2.5 to VIN + 2.0 (20ns) TST Storage Temperature -65 to +150 °C TJ Junction Temperature +160 °C TL Lead Temperature +260 °C ESD Susceptibility (Note 5) HBM Human Body Model ±2000 V CDM Charged Device Model ± 1000 V Notes: 4. Stresses greater than the Absolute Maximum Ratings specified above can cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not im plied. Device reliability can be affected by exposure to absolute maximum rating conditions for extended periods of time. 5. Semiconductor devices are ESD sensitive and can be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices. Thermal Resistance (Note 6) Symbol Parameter Rating Unit θJA Junction to Ambient SO-8EP (Standard) 45 ° C/W θJC Junction to Case SO-8EP (Standard) 5 ° C/W Note: 6. Test condition for SO-8EP (Standard): Device mounted on FR-4 substrate, four-layer PC board, 2oz copper, with minimum recommended pad layout. Recommended Operating Conditions (Note 7) (@ TA = +25° C, unless otherwise specified.) Symbol Parameter Min Max Unit VIN Supply Voltage 3.8 40 V VOUT Output Voltage 0.8 VIN V TA Operating Ambient Temperature -40 +85 °C TJ Operating Junction Temperature -40 +125 °C Note: 7. The device function is not guaranteed outside of the recommended operating conditions.
Document number: DS43571 Rev. 1 - 2 6 of 26 www.diodes.com March 2021 © Diodes Incorporated AP64100 Electrical Characteristics (@ TJ = +25° C, VIN = 12V, unless otherwise specified. Min/Max limits apply across the recommended operating junction temperature range, -40° C to +125° C, and input voltage range, 3.8V to 40V, unless otherwise specified.) Symbol Parameter Test Conditions Min Typ Max Unit ISHDN Shutdown Supply Current VEN = 0V — 1 — μA IQ Quiescent Supply Current VEN = Floating, R2 = OPEN, No Load, VBST - VSW = 5V — 25 — μA POR VIN Undervoltage Rising Threshold — — 3.5 3.7 V UVLO VIN Undervoltage Falling Threshold — — 3.1 — V RDS(ON)1 High-Side Power MOSFET On-Resistance (Note 8) — — 150 — mΩ RDS(ON)2 Low-Side Power MOSFET On-Resistance (Note 8) — — 80 — mΩ IPEAK_LIMIT HS Peak Current Limit (Note 8) — 1.5 2.2 3.5 A IVALLEY_LIMIT LS Valley Current Limit (Note 8) — — 2.2 — A IPFMPK PFM Peak Current Limit — — 400 — mA IZC Zero Cross Current Threshold — — 60 — mA fRANGE_RT Frequency Range Using RT (Note 8) — 100 — 2200 kHz fSW Oscillator Frequency RT = 200kΩ (±1%) 450 500 550 kHz fRANGE_CLK Frequency Range Using External CLK (Note 8) — 100 — 2200 kHz tON_MIN Minimum On-Time — — 100 — ns VFB Feedback Voltage CCM 0.792 0.800 0.808 V VEN_H EN Logic High Threshold — — 1.18 1.25 V VEN_L EN Logic Low Threshold — 1.03 1.09 — V IEN EN Input Current VEN = 1.5V — 5.5 — μA VEN = 1V 1 1.5 2 μA tSS Soft-Start Time — — 2 — ms TSD Thermal Shutdown (Note 8) — — +160 — °C THys Thermal Shutdown Hysteresis (Note 8) — — +25 — °C Note: 8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.
Document number: DS43571 Rev. 1 - 2 11 of 26 www.diodes.com March 2021 © Diodes Incorporated AP64100
Application Information
1 Pulse Width Modulation (PWM) Operation
The AP64100 device is a 3.8V-to-40V input, 1A output, EMI friendly, fully integrated synchronous buck converter. Refer to the block diagram in Figure 3. The device employs fixed-frequency peak current mode control. The switching frequency is adjustable from 100kHz to 2.2MHz through clock cycle, Q2 turns off and Q1 turns on. This sequence repeats every clock cycle. oscillation when the duty cycle is greater than 50% for peak current mode control. The peak current mode control and built-in 2ms soft-start time simplify the AP64100 footprint.
2 Pulse Frequency Modulation (PFM) Operation
decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from decreasing any further. efficiency of up to 88% at a 5mA load condition. The quiescent current of the AP64100 is 25μA typical under a no-load, non-switching condition.
3 Enable
its logic low threshold (typical 1.09V, falling), the internal SS voltage discharges to ground and device operation disables. The EN pin can also be used to adjust the undervoltage lockout thresholds. See Undervoltage Lockout (UVLO) section for more details.
stay in any one frequency for a significant period of time.
5 Adjusting Undervoltage Lockout (UVLO)
high-side and low-side power MOSFETs turn off. on the EN pin along with an external resistive divider (R3 and R4) configures the VIN UVLO threshold voltages as shown in Figure 25. Figure 25. Adjusting UVLO
6 Output Overvoltage Protection (OVP)
order to prevent the output voltage from continuing to increase.
7 Overcurrent Protection (OCP)
down time, the buck converter restarts powering up. Hiccup mode reduces the power dissipation in the overcurrent condition.
8 Thermal Shutdown (TSD)
9 Power Derating Characteristics
Figure 26. Output Current Derating Curve vs. Ambient Temperature, VIN = 12V, fSW = 500kHz
10 Setting the Output Voltage
Table 1 shows a list of recommended component selections for common AP64100 output voltages referencing Figure 1. Table 1. Recommended Components Selections, fSW = 500kHz
11 Adjusting Switching Frequency
The switching frequency of the AP64100 can be set through either of two modes, Resistor Timing or External Clock Synchronization. FSS is enabled when setting the switching frequency through Resistor Timing mode. FSS is disabled when setting the switching frequency through External Clock Synchronization mode.
11 Adjusting Switching Frequency (continued)
Figure 27. Switching Between Resistor Timing and External Clock Synchronization Modes Figure 27. Before an external clock signal is available at the RT/CLK pin, the device operates in Resistor Timing mode. When an external clock is
12 Inductor
For the AP64100, choose ∆IL to be 30% to 40% of the maximum load current of 1A. than 50mΩ. Use a larger inductance for improved efficiency under light load conditions.
Document number: DS43571 Rev. 1 - 2 16 of 26 www.diodes.com March 2021 © Diodes Incorporated AP64100 Application Information (continued)
13 Input Capacitor
The input capacitor reduces both the surge current drawn from the input supply as well as the switching noise from the device. The input capacitor must sustain the ripple current produced during the on -time of Q1. It must have a low ESR to minimize power dissipation due to the RMS input current. The RMS current rating of the input capacitor is a critical parameter and must be higher than the RMS input current. As a rul e of thumb, select an input capacitor with an RMS current rating greater than half of the maximum load current. Due to large dI/dt through the input capacitor, electrolytic or ceramic capacitors with low ESR should be used. If using a tantalum capacitor, it must be surge protected or else capacitor failure could occur. Using a ceramic capacitor of 20µ F or greater is sufficient for most applications.
14 Output Capacitor
The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces both the overshoots and undershoots of the output voltage during load transients. During the first few micro seconds of an increasing load transient, the converter recognizes the change from steady-state and enters 100% duty cycle to supply more current to the load. However, the inductor limits the change to increasing cu rrent depending on its inductance. Therefore, the output capacitor supplies the difference in current to the load during this time. Likewise, during the first few microseconds of a decreasing load transient, the converter recognizes the change from steady -state and sets the on -time to minimum to reduce the current supplied to the load. However, the inductor limits the change in decreasing current as well. Therefore, the output capacitor absorbs the excess current from the inductor during this time. The effective output capacitance, COUT, requirements can be calculated from the equations below. The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated by: 𝐕𝐎𝐔𝐓𝐑𝐢𝐩𝐩𝐥𝐞 = ∆𝐈𝐋 ∙ (𝐄𝐒𝐑 + 𝟏 𝟖 ∙ 𝐟𝐒𝐖 ∙ 𝐂𝐎𝐔𝐓) Eq. 10 Output capacitors with large capacitance and low ESR are the best option. For most applications, a total capacitance of 22 µ F using ceramic capacitors is sufficient. To meet the load transient requirements, the calculated COUT should satisfy the following inequality: 𝐂𝐎𝐔𝐓 > 𝐦𝐚𝐱 ( 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 ∆𝐕𝐎𝐯𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ 𝐕𝐎𝐔𝐓 , 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 ∆𝐕𝐔𝐧𝐝𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ (𝐕𝐈𝐍 − 𝐕𝐎𝐔𝐓)) Eq. 11 Where: ITrans is the load transient ∆VOvershoot is the maximum output overshoot voltage ∆VUndershoot is the maximum output undershoot voltage
15 Bootstrap Capacitor and Low-Dropout (LDO) Operation
To ensure proper operation, a ceramic capacitor must be connected between the BST and SW pins to supply the drive voltage for the high -side power MOSFET. A 100nF ceramic capacitor is sufficient. If the bootstrap capacitor voltage falls below 2.3V, the boot undervoltage protection circuit turns Q2 on for 300ns to refresh the bootstrap capacitor and raise its voltage back above 2.55V. The bootstrap capacitor threshold voltage is always maintained to ensure enough driving capability for Q1. This operation may arise during long periods of no switching such as in PFM with light load conditions. Another event that requires the refreshing of the bootstrap capacitor is when the input voltage drops close to the output voltage. Under this condition, the regulator enters low-dropout mode by holding Q1 on for multiple clock cycles. To prevent the bootstrap capacitor from discharging, Q2 is forced to refresh. T he effective duty cycle is approximately 100% so that it acts as an LDO to maintain the output voltage regulation.
16 External Loop Compensation Design
function to achieve good line regulation. Figure 28 shows the small signal model of the synchronous buck regulator. Figure 28. Small Signal Model of Buck Regulator
16 External Loop Compensation Design (continued)
Figure 29. Type ll Compensator
Document number: DS43571 Rev. 1 - 2 19 of 26 www.diodes.com March 2021 © Diodes Incorporated AP64100 Application Information (continued) The loop gain at the crossover frequency has unity gain. Therefore, the compensator resistance, R5, is determined by: 𝐑𝟓 = 𝟐𝛑 ∙ 𝐟𝐂 ∙ 𝐕𝐎𝐔𝐓 ∙ 𝐂𝐎 ∙ 𝐑𝐓 𝐠𝐦 ∙ 𝐕𝐅𝐁 = 𝟒. 𝟔𝟕𝐱𝟏𝟎𝟑[𝛀 𝐀] ∙ 𝐟𝐂 ∙ 𝐕𝐎𝐔𝐓 ∙ 𝐂𝐎𝐔𝐓 Eq. 17 Where: gm is 0.15mS RT is 0.089V/A VFB is 0.8V fC is the desired crossover frequency Be aware that most ceramic capacitors will degrade with voltage stress or temperature extremes. Refer to its datasheet and us e its worst case capacitance value for calculations. The compensation capacitors C5 and C6 are then equal to: 𝐂𝟓 = 𝐕𝐎𝐔𝐓 ∙ 𝐂𝐎𝐔𝐓 𝐈𝐎𝐔𝐓 ∙ 𝐑𝟓 Eq. 18 𝐂𝟔 = 𝐦𝐚𝐱 (𝐑𝐂 ∙ 𝐂𝐎 𝐑𝟓 , 𝟏 𝛑 ∙ 𝐟𝐒𝐖 ∙ 𝐑𝟓) Eq. 19 Where: IOUT is the output load current The inclusion of C6 can increase gain margin and can decrease phase margin. In most cases, C6 is optional and may be omitted. The zero, z2, is optional as it can increase both the phase margin and gain bandwidth and can decrease gain margin. If used, place this zer o at around two to five times fC. Thus, C4 is in the approximate range of: 𝐂𝟒 = [ 𝟏 𝟏𝟎𝛑 ∙ 𝐟𝐂 ∙ 𝐑𝟏 , 𝟏 𝟒𝛑 ∙ 𝐟𝐂 ∙ 𝐑𝟏 ] Eq. 20
circuit may vary slightly from the calculated first-order approximation equations. Figure 30. Example Circuit for Loop Compensation Calculations capacitors are used, their calculations are also required.
Document number: DS43571 Rev. 1 - 2 21 of 26 www.diodes.com March 2021 © Diodes Incorporated AP64100 Application Information (continued) From Eq. 17, the value of R5 is calculated as: 𝐑𝟓 = 𝟒. 𝟔𝟕𝐱𝟏𝟎𝟑[𝛀 𝐀] ∙ 𝐟𝐂 ∙ 𝐕𝐎𝐔𝐓 ∙ 𝐂𝐎𝐔𝐓 = 𝟒. 𝟔𝟕𝐱𝟏𝟎𝟑 [𝛀 𝐀] ∙ 𝟐𝟎𝐤𝐇𝐳 ∙ 𝟐. 𝟓𝐕 ∙ 𝟏𝟓𝛍𝐅 ≈ 𝟑. 𝟓𝟎𝐤𝛀 Choose a standard resistor value for R5 close to its calculated value. For example, choose R5 to be 3.48k. From Eq. 18, C5 is calculated as: 𝐂𝟓 = 𝐕𝐎𝐔𝐓 ∙ 𝐂𝐎𝐔𝐓 𝐈𝐎𝐔𝐓 ∙ 𝐑𝟓 = 𝟐. 𝟓𝐕 ∙ 𝟏𝟓𝛍𝐅 𝟏𝐀 ∙ 𝟑. 𝟒𝟖𝐤𝛀 ≈ 𝟏𝟎. 𝟕𝟖𝐧𝐅 Choose a standard capacitor value for C5 close to its calculated value. For example, choose C5 to be 10nF. From Eq. 19, C6 is calculated as: 𝐂𝟔 = 𝐦𝐚𝐱 (𝐑𝐂 ∙ 𝐂𝐎𝐔𝐓 𝐑𝟓 , 𝟏 𝛑 ∙ 𝐟𝐒𝐖 ∙ 𝐑𝟓) = 𝐦𝐚𝐱 (𝟓𝐦𝛀 ∙ 𝟏𝟓𝛍𝐅 𝟑. 𝟒𝟖𝐤𝛀 , 𝟏 𝛑 ∙ 𝟓𝟎𝟎𝐤𝐇𝐳 ∙ 𝟑. 𝟒𝟖𝐤𝛀) ≈ 𝐦𝐚𝐱(𝟐𝟏. 𝟓𝟓𝐩𝐅, 𝟏𝟖𝟐. 𝟗𝟒𝐩𝐅) = 𝟏𝟖𝟐. 𝟗𝟒𝐩𝐅 C6 is optional. If used, choose a standard capacitor value for C6 close to its calculated value. For example, choose C6 to be 180pF. However, use of C6 in the final example circuit will be omitted. From Eq. 20, the approximate range of C4 is calculated as: 𝐂𝟒 = [ 𝟏 𝟏𝟎𝛑 ∙ 𝐟𝐂 ∙ 𝐑𝟏 , 𝟏 𝟒𝛑 ∙ 𝐟𝐂 ∙ 𝐑𝟏 ] = [ 𝟏 𝟏𝟎𝛑 ∙ 𝟐𝟎𝐤𝐇𝐳 ∙ 𝟐𝟏. 𝟓𝐤𝛀 , 𝟏 𝟒𝛑 ∙ 𝟐𝟎𝐤𝐇𝐳 ∙ 𝟐𝟏. 𝟓𝐤𝛀] C4 is optional. If used, choose a standard capacitor value for C4 that is close to its calculated range. For example, choose C4 to be 180pF. However, use of C4 in the final example circuit will be omitted.
Figure 31. Example Circuit with Calculated Component Values for Loop Compensation Figure 32. Closed-Loop Bandwidth Figure 33. Closed-Loop Phase Margin
- The AP64100 works at 1A load current so heat dissipation is a major concern in the layout of the PCB. 2oz copper for both the top and
bottom layers is recommended.
- Place the input capacitors as closely across VIN and GND as possible.
- Place the inductor as close to SW as possible.
- Place the output capacitors as close to GND as possible.
- Place the feedback components as close to FB as possible.
- If using four or more layers, use at least the 2nd and 3rd layers as GND to maximize thermal performance.
- Add as many vias as possible around both the GND pin and under the GND plane for heat dissipation to all the GND layers.
- Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers.
- See Figure 34 for more details.
Figure 34. Recommended PCB Layout
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Ordering Information
SP : SO-8EP (Standard) AP64100 X - X 13 : Tape & Reel Package Packing Part Number Package Code Tape and Reel Quantity Part Number Suffix AP64100SP-13 SP 4,000 -13 Marking Information SO-8EP (Standard) AP64100 (Top View) YY WW X X E Logo WW : Week : 01 to 52; 52 YY : Year : 21, 22, 23~ X X : Internal Code 8 7 6 5 1 2 3 4 Represents 52 and 53 Week E : SO-8EP (Standard) Marking ID
Document number: DS43571 Rev. 1 - 2 25 of 26 www.diodes.com March 2021 © Diodes Incorporated AP64100 Package Outline Dimensions Please see http://www.diodes.com/package-outlines.html for the latest version. SO-8EP (Standard) SO-8EP (Standard) Dim Min Max Typ A1 0.00 0.13 — A2 1.35 1.55 1.45 b 0.30 0.51 0.40 c 0.15 0.25 0.20 D 4.70 5.10 4.90 D1 2.75 3.35 3.05 E 5.80 6.20 6.00 E1 3.80 4.00 3.85 E2 2.11 2.71 2.41 e — — 1.27 L 0.40 1.27 0.72 a 0° 8° 4° All Dimensions in mm Suggested Pad Layout Please see http://www.diodes.com/package-outlines.html for the latest version. SO-8EP (Standard) Dimensions Value (in mm) C 1.270 X 0.802 X1 3.502 X2 4.612 Y 1.505 Y1 2.613 Y2 6.500 Mechanical Data Moisture Sensitivity: Level 1 per J-STD-020 Terminals: Finish – Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 Weight: 0.081 grams (Approximate) b e 0.250 D E c OPTION A (TOP VIEW) OPTION B (TOP VIEW) OPTION A (BOTTOM VIEW) OPTION B (BOTTOM VIEW) Gauge Plane a L C X Y
Document number: DS43571 Rev. 1 - 2 26 of 26 www.diodes.com March 2021 © Diodes Incorporated AP64100 IMPORTANT NOTICE 1. DIODES INCORPORATED AND ITS SUBSIDIARIES (“DIODES”) MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTIC ULAR PURPOSE OR NON -INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. This document is intended for skilled and technically trained engineering customers and users who d esign with Diodes products. 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