AP64060 DIODES | Alldatasheet
Document overview
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Technical content
Features
VIN 4.5V to 40V 600mA Continuous Output Current Less than 0.1% Output Ripple at 12V 90µA Low Quiescent Current (Pulse Frequency Modulation) 2.2MHz Switching Frequency Supports Pulse Frequency Modulation (PFM) Proprietary Gate Driver Design for Best EMI Reduction Precision Enable Threshold to Adjust UVLO Protection Circuitry Undervoltage Lockout (UVLO) Output Overvoltage Protection (OVP) Cycle-by-Cycle Peak Current Limit Thermal Shutdown Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) An automotive-compliant part is available under separate datasheet (AP64060Q) Pin Assignments 3 4 FB EN VINGND SWBST TSOT26 TOP VIEW
Applications
5V, 12V, and 24V distributed power bus supplies eMeters Automotive devices White goods and small home appliances FPGA, DSP, and ASIC supplies General-purpose point-of-load devices Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen - and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.
capacitor is recommended from BST to SW to power the high-side driver. FB 3 Feedback sensing terminal for the output voltage. Connect this pin to the resistive divider of the output. See Setting the Output Voltage section for more details. turn it off. Connect to VIN for automatic startup. The EN has a precision threshold of 1.21V for programing the UVLO. See Enable section for more details. of the IC. See Input Capacitor section for more details. Figure 3. Functional Block Diagram
Document number: DS44123 Rev. 2 - 2 4 of 18 www.diodes.com August 2022 © Diodes Incorporated ADVANCED INFORMATION AP64060 Absolute Maximum Ratings (@TA = +25°C, unless otherwise specified.) (Note 4) Symbol Parameter Rating Unit VIN Supply Pin Voltage -0.3 to +42.0 (DC) V VFB Feedback Pin Voltage -0.3V to +6.0 V VEN Enable Pin Voltage -0.3 to +42.0 V VSW Switch Pin Voltage -0.3 to VIN + 0.3 (DC) V -2.5 to VIN + 2.0 (20ns) VBST Bootstrap Pin Voltage VSW - 0.3 to VSW + 6.0 V TST Storage Temperature -65 to +150 °C TJ Junction Temperature +170 °C TL Lead Temperature +260 °C ESD Susceptibility (Note 5) HBM Human Body Model ±2000 V CDM Charged Device Model ±1000 V Notes: 4. Stresses greater than the Absolute Maximum Ratings specified above can cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not im plied. Device reliability can be affected by exposure to absolute maximum rating conditions for extended periods of time. 5. Semiconductor devices are ESD sensitive and can be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices. Thermal Resistance (Note 6) Symbol Parameter Rating Unit θJA Junction to Ambient TSOT26 80 °C/W θJC Junction to Case TSOT26 39 °C/W Note: 6. Test condition for TSOT26: Device mounted on FR-4 substrate, single-layer PC board, 2oz copper, with minimum recommended pad layout. Recommended Operating Conditions (Note 7) (@ TA = +25°C, unless otherwise specified.) Symbol Parameter Min Max Unit VIN Supply Voltage 4.5 40 V VOUT Output Voltage 0.8 26 V TA Operating Ambient Temperature Range -40 +85 °C TJ Operating Junction Temperature Range -40 +125 °C Note: 7. The device function is not guaranteed outside of the recommended operating conditions.
Document number: DS44123 Rev. 2 - 2 5 of 18 www.diodes.com August 2022 © Diodes Incorporated ADVANCED INFORMATION AP64060 Electrical Characteristics (@ TJ = +25°C, VIN = 12V, unless otherwise specified. Min/Max limits apply across the recommended junction temperature range, -40°C to +125°C, and input voltage range, 3.8V to 40V, unless otherwise specified.) Symbol Parameter Test Conditions Min Typ Max Unit ISHDN Shutdown Supply Current VEN = 0V — 1 10 μA IQ Supply Current (Quiescent) VEN = Floating, R2 = OPEN, No Load, VBST - VSW = 5V — 90 — μA UVLO VIN Undervoltage Rising Threshold — — 4.2 4.4 V VIN Undervoltage Hysteresis — — 440 — mV RDS(ON)1 High-Side Power MOSFET On-Resistance (Note 8) — — 600 — mΩ RDS(ON)2 Low-Side Power MOSFET On-Resistance (Note 8) — — 300 — mΩ IPEAK_LIMIT HS Peak Current Limit (Note 8) — 0.80 0.90 1.30 A IVALLEY_LIMIT LS Valley Current Limit (Note 8) — — 0.7 — A IPFMPK PFM Peak Current Limit VOUT = 5V, L = 10μH — 40 — mA IZC Zero Cross Current Threshold — — 10 — mA fSW Oscillator Frequency — — 2 — MHz tON_MIN Minimum On-Time — — 60 — ns VFB Feedback Voltage CCM, TJ = -40ºC to +125 ºC 784 800 816 mV VEN_H EN Logic High — — 1.21 1.25 V VEN_L EN Logic Low — 1.03 1.10 — V tSS Soft-Start Time — — 1 — ms TSD Thermal Shutdown Threshold (Note 8) — — 170 — °C THys Thermal Shutdown Hysteresis (Note 8) — — 35 — °C Note: 8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.
Document number: DS44123 Rev. 2 - 2 10 of 18 www.diodes.com August 2022 © Diodes Incorporated ADVANCED INFORMATION AP64060
Application Information
1 Pulse Width Modulation (PWM) Operation
The AP64060 device is a 4.5V-to-340V input, 600mA output, EMI friendly, fully integrated synchronous buck converter. Refer to the block diagram in Figure 4. The device employs fixed -frequency peak current mode control. The internal 2MHz clock’s rising edge initiates turning on the integrated high-side power MOSFET, Q1, for each cycle. When Q1 is on , the inductor current rises linearly and the device charges the output capacitor. The current across Q1 is sensed and converted to a voltage with a ratio of R T via the CSA block. The CSA output is combined with an internal slope compensation, SE, resulting in V SUM. When VSUM rises higher than the COMP node, the device turns off Q1 and turns on the low - side power MOSFET, Q2. The inductor current decreases when Q2 is on. On the rising edge of next clock cycle, Q2 turns off and Q1 turns on. This sequence repeats every clock cycle. The error amplifier generates the COMP voltage by comparing the voltage on the FB pin with an internal 0.8V reference. An increase in load current causes the feedback voltage to drop. The error amplifier thus raises the COMP voltage until the average i nductor current matches the increased load current. This feedback loop regulates the output voltage. The internal slope compensation circuitry prevent s subharmonic oscillation when the duty cycle is greater than 50% for peak current mode control. The peak current mode control, integrated loop compensation network, and built -in 4ms soft-start time simplifies the AP64060 footprint as well as minimizes the external component count.
2 Pulse Frequency Modulation (PFM) Operation
In heavy load conditions, the AP64060 operates in forced PWM mode. As the load current decreases , t he internal COMP node voltage also decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from d ecreasing any further. The voltage at which COMP is clamped corresponds to the 200mA PFM peak inductor current limit. As the load current approaches zero, the AP64060 enters PFM mode to increase the converter power efficiency at light load conditions. When the inductor current decreases to 50mA, zero cross detection circuitry on the low -side power MOSFET, Q2, forces it off. The buck converter does not sink current from the output when the output load is light and while the device is in PFM. Because the AP64060 works in PFM during light load conditions, it can achieve power efficiency of up to 82% at a 5mA load condition. The quiescent current of the AP64060 is 90μA typical under a no-load, non-switching condition.
3 Enable
When disabled, the device shutdown supply current is only 1μA. When applying a voltage greater than the EN logic high threshold (typical 1.21V, rising), the AP64060 enables all functions and the device initiates the soft-start phase. The EN pin is a high -voltage pin and can be dir ectly connected to VIN to automatically start up the device as VIN increases. The AP64060 has a built-in 1ms soft-start time to prevent output voltage overshoot and inrush current. When the EN voltage falls below its logic low threshold (typical 1.10V, falling), the internal SS voltage discharges to ground and device operation disables. The EN pin can also be used to program the undervoltage lockout thresholds. See Undervoltage Lockout (UVLO) section for more details.
4 Adjusting Undervoltage Lockout (UVLO)
Undervoltage lockout is implemented to prevent the IC from insufficient input voltages. The AP64060 device has a UVLO comparator that monitors the input voltage and the internal bandgap reference. The AP64060 disables if the input voltage falls bel ow 3.8V. In this UVLO event, both the high-side and low-side power MOSFETs turn off. For applications requiring higher VIN UVLO threshold voltages than is provided by the default setup, an external resistor R3 added in series to the EN pin along with an internal 480kΩ configures the VIN UVLO threshold voltages as shown in Figure 24.
Figure 24. Programming UVLO
5 Output Overvoltage Protection (OVP)
output voltage from continuing to increase.
6 Overcurrent Protection (OCP)
7 Thermal Shutdown (TSD)
8 Power Derating Characteristics
temperature of 150°C when considering the thermal design. Figure 25 shows a typical derating curve versus ambient temperature. Figure 25. Output Current Derating Curve vs. Ambient Temperature, VIN = 12V
9 Setting the Output Voltage
Table 1 shows a list of recommended component selections for common AP64060 output voltages referencing Figure 1. Table 1. Recommended Component Selections
10 Inductor
For the AP64060, choose ∆IL to be 20% to 30% of the maximum load current of 1A. than 70mΩ. Use a larger inductance for improved efficiency under light load conditions.
Document number: DS44123 Rev. 2 - 2 14 of 18 www.diodes.com August 2022 © Diodes Incorporated ADVANCED INFORMATION AP64060 Application Information (continued)
11 Input Capacitor
The input capacitor reduces both the surge current drawn from the input supply as well as the switching noise from the device. The input capacitor must sustain the ripple current produced during the on -time of Q1. It must have a low ESR to minimize power dissipation due to the RMS input current. The RMS current rating of the input capacitor is a critical parameter and must be higher than the RMS input current. As a rul e of thumb, select an input capacitor with an RMS current rating greater than half of the maximum load current. Due to large dI/dt through the input capacitor, electrolytic or ceramic capacitors with low ESR should be used. If using a tantalum capacitor, it must be surge protected or else capacitor failure could occur. Using a ceramic capacitor greater than 10µF is sufficient for most applications.
12 Output Capacitor
The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces both the overshoots and undershoots of the output voltage during load transients. During the first few microseconds of an increasing load transient, the converter recognizes the change from steady-state and enters 100% duty cycle to supply more current to the load. However, the inductor limits the change to increasing cu rrent depending on its inductance. Therefore, the output capacitor supplies the difference in current to the load during this time. Likewise, during the first few microseconds of a decreasing load transient, the converter recognizes the change from steady -state and sets the on -time to minimum to reduce the current supplied to the load. However, the inductor limits the change in decreasing current as well. Therefore, th e output capacitor absorbs the excess current from the inductor during this time. The effective output capacitance, COUT, requirements can be calculated from the equations below. The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated by: 𝐕𝐎𝐔𝐓𝐑𝐢𝐩𝐩𝐥𝐞 = ∆𝐈𝐋 ∙ (𝐄𝐒𝐑 + 𝟏 𝟖 ∙ 𝐟𝐬𝐰 ∙ 𝐂𝐎𝐔𝐓) Eq. 7 An output capacitor with large capacitance and low ESR is the best option. For most applications, a 22µF to 68µF ceramic capacitor is sufficient. To meet the load transient requirements, the calculated COUT should satisfy the following inequality: 𝐂𝐎𝐔𝐓 > 𝐦𝐚𝐱 ( 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 ∆𝐕𝐎𝐯𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ 𝐕𝐎𝐔𝐓 , 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 ∆𝐕𝐔𝐧𝐝𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ (𝐕𝐈𝐍 − 𝐕𝐎𝐔𝐓)) Eq. 8 Where: ITrans is the load transient ∆VOvershoot is the maximum output overshoot voltage ∆VUndershoot is the maximum output undershoot voltage
13 Bootstrap Capacitor and Low-Dropout (LDO) Operation
To ensure proper operation, a ceramic capacitor must be connected between the BST and SW pins. A 100nF ceramic capacitor is sufficient. If the bootstrap capacitor voltage falls below 2.3V, the boot undervoltage protection circuit turns Q2 on for 220ns to refresh the bootstrap capacitor and raise its voltage back above 2.85V. The bootstrap capacitor voltage threshold is always maintained to ensure enough driving capability for Q1. This operation may arise during long periods of no switching such as in PFM with light load conditions. Another event that requires the refreshing of the bootstrap capacitor is when the input voltage drops close to the output voltage. Under this condition, the regulator enters low -dropout mode by holding Q1 on for multiple clock cycles. To prevent the bootstrap capacitor from discharging, Q2 is forced to refresh.
- The AP64060 works at 600mA load current so heat dissipation is a major concern in the layout of the PCB. 2oz copper for both the top and
bottom layers is recommended.
- Place the input capacitors as closely across VIN and GND as possible.
- Place the inductor as close to SW as possible.
- Place the output capacitors as close to GND as possible.
- Place the feedback components as close to FB as possible.
- If using four or more layers, use at least the 2nd and 3rd layers as GND to maximize thermal performance.
- Add as many vias as possible around both the GND pin and under the GND plane for heat dissipation to all the GND layers.
- Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers.
- See Figure 26 for more details.
Figure 26. Recommended PCB Layout
Document number: DS44123 Rev. 2 - 2 16 of 18 www.diodes.com August 2022 © Diodes Incorporated ADVANCED INFORMATION AP64060
Ordering Information
7: Tape & ReelWU: TSOT26 Packing Part Number Operation Mode Package Package Code Packing Qty. Carrier AP64060WU-7 PFM/PWM TSOT26 WU 3000 7” Tape & Reel Marking Information TSOT26 1 2 3 XX Y W X XX : Identification Code Y : Year 0~9 X : Internal Code ( Top View ) W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week Part Number Package Identification Code AP64060WU-7 TSOT26 TG
Document number: DS44123 Rev. 2 - 2 17 of 18 www.diodes.com August 2022 © Diodes Incorporated ADVANCED INFORMATION AP64060 Package Outline Dimensions Please see http://www.diodes.com/package-outlines.html for the latest version. TSOT26 TSOT26 Dim Min Max Typ A — 1.00 — A1 0.010 0.100 — A2 0.840 0.900 — D 2.800 3.000 2.900 E 2.800 BSC E1 1.500 1.700 1.600 b 0.300 0.450 — c 0.120 0.200 — e 0.950 BSC e1 1.900 BSC L 0.30 0.50 — L2 0.250 BSC θ 0° 8° 4° θ1 4° 12° — All Dimensions in mm Suggested Pad Layout Please see http://www.diodes.com/package-outlines.html for the latest version. TSOT26 Dimensions Value (in mm) C 0.950 X 0.700 Y 1.000 Y1 3.200 D E1/2 E E/2 e A Seating Plane0 L Gauge Plane 01(4x) 01(4x) c b Seating Plane C X Y
Document number: DS44123 Rev. 2 - 2 18 of 18 www.diodes.com August 2022 © Diodes Incorporated ADVANCED INFORMATION AP64060 IMPORTANT NOTICE 1. DIODES INCORPORATED (Diodes) AND ITS SUBSIDIARIES MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICUL AR PURPOSE OR NON -INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes’ products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. This document is intended for skil led and technically trained engineering customers and users who design with Diodes’ products. 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