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Document overview
- Manufacturer or author: Diodes Incorporated
- PDF pages: 22
Technical content
Features
VIN 3.8V to 32V 3A Continuous Output Current 0.8V ± 1% Reference Voltage 22µA Low Quiescent Current (Pulse Frequency Modulation) 500kHz Switching Frequency Supports Pulse Frequency Modulation (PFM) o AP63300 o Up to 88% Efficiency at 5mA Light Load Pulse Width Modulation (PWM) Regardless of Output Load o AP63301 Proprietary Gate Driver Design for Best EMI Reduction Frequency Spread Spectrum (FSS) to Reduce EMI o AP63300 Low-Dropout (LDO) Mode Precision Enable Threshold to Adjust UVLO Protection Circuitry o Undervoltage Lockout (UVLO) o Output Overvoltage Protection (OVP) o Cycle-by-Cycle Peak Current Limit o Thermal Shutdown Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) Pin Assignments 3 4 6FB EN VIN GND SW BST TSOT26 TOP VIEW
Applications
5V, 12V, and 24V Distributed Power Bus Supplies Flat Screen TV Sets and Monitors Power Tools and Laser Printers White Goods and Small Home Appliances FPGA, DSP, and ASIC Supplies Home Audio Network Systems Gaming Consoles Consumer Electronics General Purpose Point of Load Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant . 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlori ne (<1500ppm total Br + Cl) and <1000ppm antimony compounds.
Document number: DS42002 Rev. 3 - 2 3 of 22 www.diodes.com August 2019 © Diodes Incorporated AP63300/AP63301 Pin Descriptions Pin Name Pin Number Function FB 1 Feedback sensing terminal for the output voltage. Connect this pin to the resistive divider of the output. See Setting the Output Voltage section for more details. EN 2 Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator and low to turn it off. Connect to VIN or leave floating for automatic startup. The EN has a precision threshold of 1.18V for programing the UVLO. See Enable section for more details. VIN 3 Power Input. VIN supplies the power to the IC as well as the step-down converter power MOSFETs. Drive VIN with a 3.8V to 32V power source. Bypass VIN to GND with a suitably large capacitor to eliminate noise due to the switching of the IC. See Input Capacitor section for more details. GND 4 Power Ground. SW 5 Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter from SW to the output load. BST 6 High-Side Gate Drive Boost Input. BST supplies the drive for the high -side N-Channel power MOSFET. A 100nF capacitor is recommended from BST to SW to power the high-side driver.
Figure 4. Functional Block Diagram
Document number: DS42002 Rev. 3 - 2 5 of 22 www.diodes.com August 2019 © Diodes Incorporated AP63300/AP63301 Absolute Maximum Ratings (Note 4) (At TA = +25°C, unless otherwise specified.) Symbol Parameter Rating Unit VIN Supply Pin Voltage -0.3 to +35.0 (DC) V VFB Feedback Pin Voltage -0.3V to +6.0 V VEN Enable/UVLO Pin Voltage -0.3 to +35.0 V VSW Switch Pin Voltage -0.3 to VIN + 0.3 (DC) V -2.5 to VIN + 2.0 (20ns) VBST Bootstrap Pin Voltage VSW - 0.3 to VSW + 6.0 V TST Storage Temperature -65 to +150 °C TJ Junction Temperature +160 °C TL Lead Temperature +260 °C ESD Susceptibility (Note 5) HBM Human Body Model 2000 V CDM Charged Device Model 1000 V Notes: 4. Stresses greater than the Absolute Maximum Ratings specified above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not im plied. Device reliability may be affected by exposure to absolute maximum rating conditions for extended periods of time. 5. Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be take n when handling and transporting these devices. Thermal Resistance (Note 6) Symbol Parameter Rating Unit θJA Junction to Ambient TSOT26 89 °C/W θJC Junction to Case TSOT26 39 °C/W Note: 6. Test condition for TSOT26: Device mounted on FR-4 substrate, single-layer PC board, 2oz copper, with minimum recommended pad layout. Recommended Operating Conditions (Note 7) (At TA = +25°C, unless otherwise specified.) Symbol Parameter Min Max Unit VIN Supply Voltage 3.8 32 V VOUT Output Voltage 0.8 31 V TA Operating Ambient Temperature Range -40 +85 °C TJ Operating Junction Temperature Range -40 +125 °C Note: 7. The device function is not guaranteed outside of the recommended operating conditions.
Document number: DS42002 Rev. 3 - 2 6 of 22 www.diodes.com August 2019 © Diodes Incorporated AP63300/AP63301 Electrical Characteristics (At TA = +25°C, VIN = 12V, unless otherwise specified. Min/Max limits apply across the recommended ambient temperature range, -40°C to +85°C, and input voltage range, 3.8V to 32V, unless otherwise specified.) Symbol Parameter Test Conditions Min Typ Max Unit ISHDN Shutdown Supply Current VEN = 0V — 1 3 μA IQ Supply Current (Quiescent) AP63300: VEN = Floating, VFB = 1.0V — 22 — μA AP63301: VEN = Floating, VFB = 1.0V — 280 — μA UVLO VIN Undervoltage Rising Threshold — — 3.5 3.7 V VIN Undervoltage Hysteresis — — 440 — mV RDS(ON)1 High-Side Power MOSFET On-Resistance (Note 8) — — 75 — mΩ RDS(ON)2 Low-Side Power MOSFET On-Resistance (Note 8) — — 40 — mΩ IPEAK_LIMIT HS Peak Current Limit (Note 8) — 4.1 4.5 4.9 A IVALLEY_LIMIT LS Valley Current Limit (Note 8) — — 4.0 — A IPFMPK PFM Peak Current Limit — — 930 — mA IZC Zero Cross Current Threshold — — 60 — mA fSW Oscillator Frequency — 450 500 550 kHz tON_MIN Minimum On-Time — — 80 — ns VFB Feedback Voltage CCM 792 800 808 mV VEN_H EN Logic High — — 1.18 1.25 V VEN_L EN Logic Low — 1.03 1.09 — V IEN EN Input Current VEN = 1.5V — 5.5 — μA VEN = 1V 1 1.5 2 μA tSS Soft-Start Time — — 4 — ms TSD Thermal Shutdown Threshold (Note 8) — — 160 — °C THys Thermal Shutdown Hysteresis (Note 8) — — 25 — °C Note: 8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.
Document number: DS42002 Rev. 3 - 2 14 of 22 www.diodes.com August 2019 © Diodes Incorporated AP63300/AP63301
Application Information
1 Pulse Width Modulation (PWM) Operation
The AP63300/AP63301 device is a 3.8V -to-32V input, 3A output, EMI friendly, fully integrated synchronous buck converter. Refer to the block diagram in Figure 4. The device employs fixed-frequency peak current mode control. The internal 500kHz clock’s rising edge initiates turning on the integrated high-side power MOSFET, Q1, for each cycle. When Q1 is on , the inductor current rises linearly and the device charges the output capacitor. The current across Q1 is sensed and converted to a voltage with a ratio of R T via the CSA block. The CSA output is combined with an internal slope compensation, SE, resulting in V SUM. When VSUM rises higher than the COMP node, the device turns off Q1 and turns on the low - side power MOSFET, Q2. The inductor current decreases when Q2 is on. On the rising edge of next clock cycle, Q2 turns off and Q1 turns on. This sequence repeats every clock cycle. The error amplifier generates the COMP voltage by comparing the voltage on the FB pin with an internal 0.8V reference. An increase in load current causes the feedback voltage to drop. The error amplifier thus raises the COMP voltage until the average inductor current matches the increased load current. This feedback loop regulates the output voltage. The internal slope compensation c ircuitry prevents subharmonic oscillation when the duty cycle is greater than 50% for peak current mode control. The peak current mode control , integrated loop compensation network, and built-in 4ms soft-start time simplifies the AP63300/AP63301 footprint as well as minimizes the external component count. In order to provide a small output ripple during light load conditions, the AP63301 operates in PWM regardless of output load.
2 Pulse Frequency Modulation (PFM) Operation
In heavy load conditions, the AP63300 operates in forced PWM mode. As the load current decreases , t he internal COMP node voltage also decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from decreasing any further. The voltage at which COMP is clamped corresponds to the 930mA PFM peak inductor current limit. As the load current approaches zero, the AP63300 enters PFM mode to increase the converter power efficiency at light load conditions. When the inductor current decreases to 60mA, zero cross detection circuitry on the low -side power MOSFET, Q2, forces it off . The buck converter does not sink current from the output when the output load is light and while the device is in PFM. Because the AP63300 works in PFM during light load conditions, it can achieve power efficiency of up to 88% at a 5mA load condition. The quiescent current of AP63300 is 22μA typical under a no-load, non-switching condition.
3 Enable
When disabled, the device shutdown supply current is only 1μA. When applying a voltage greater than the EN logic high threshold (typical 1.18V, rising), the AP63300/AP63301 enables all functions and the device initiates the soft-start phase. The EN pin is a high -voltage pin and can be directly connected to VIN to automatically start up the device as VIN increases. An internal 1.5µA pull -up current source connected from the internal LDO-regulated VCC to the EN pin guarantees that if EN is left floating, the device still automatically enables once the voltage reaches the EN logic high threshold. The AP63300/AP63301 has a built-in 4ms soft-start time to prevent output voltage overshoot and inrush current. When the EN voltage falls below its logic low threshold (typical 1. 09V, falling), the internal SS voltage discharges to ground and device operation disables. The EN pin can also be used to program the undervoltage lockout thresholds. See Undervoltage Lockout (UVLO) section for more details. Alternatively, a small ceramic capacitor can be added from EN to GND. This delays the triggering of EN , which delays the startup of the output voltage. This is useful when sequencing multiple power rails to minimize input inrush current. The amount of capacitance is calculated by: Eq. 1 Where: Cd is the time delay capacitance in nF td is the delay time in ms
converter’s power efficiency. stay in any one frequency for a significant period of time.
5 Adjusting Undervoltage Lockout (UVLO)
UVLO event, both the high-side and low-side power MOSFETs turn off. the EN pin along with an external resistive divider (R3 and R4) configures the VIN UVLO threshold voltages as shown in Figure 37. Figure 37. Programming UVLO
6 Output Overvoltage Protection (OVP)
the output voltage from continuing to increase.
7 Overcurrent Protection (OCP)
The AP63300/AP63301 has cycle-by-cycle peak current limit protection by sensing the current through the internal high-side power MOSFET, Q1. 8192 cycles of down time, the buck converter restarts powering up. Hiccup mode reduces the power dissipation in the overcurrent condition.
8 Thermal Shutdown (TSD)
9 Power Derating Characteristics
temperature of 125°C when considering the thermal design. Figure 38 shows a typical derating curve versus ambient temperature. Figure 38. Output Current Derating Curve vs. Ambient Temperature, VIN = 12V
10 Setting the Output Voltage
improves efficiency at light loads. However, values too high cause the device to be more susceptible to noise affecting its output voltage accuracy. Table 1 shows a list of recommended component selections for common AP63300/AP63301 output voltages referencing Figure 1. Table 1. Recommended Component Selections
11 Inductor
For AP63300/AP63301, choose ∆IL to be 30% to 50% of the maximum load current of 3A. than 30mΩ. Use a larger inductance for improved efficiency under light load conditions.
Document number: DS42002 Rev. 3 - 2 18 of 22 www.diodes.com August 2019 © Diodes Incorporated AP63300/AP63301 Application Information (cont.)
12 Input Capacitor
The input capacitor reduces both the surge current drawn from the input supply as well as the switching noise from the device. The input capacitor must sustain the ripple current produced during the on -time of Q1. It must have a low ESR to minimize power dissipation due to the RMS input current. The RMS current rating of the input capacitor is a critical parameter and must be higher than the RMS input current. As a rule of thumb, sel ect an input capacitor with an RMS current rating greater than half of the maximum load current. Due to large dI/dt through the input capacitor, electrolytic or ceramic capacitors with low ESR should be used. If using a tantalum capacitor, it must be surge protected or else capacitor failure could occur. Using a ceramic capacitor greater than 10µF is sufficient for most applications.
13 Output Capacitor
The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces both the overshoots and undershoots of the output voltage during load transients. During the first few micro seconds of an increasing load transient, the converter recognizes the change from steady-state and enters 100% duty cycle to supply more current to the load. However, the inductor limits the change to increasing current depending on its inductance. Therefore, the output capacitor supplies the difference in current to the load during this time. Likewise, during the first few microseconds of a decreasing load transient, the converter recognizes the change from steady -state and sets the on -time to minimum to reduce the current supplied to the load. However, the inductor limits the change in decreasing current as well. Therefore, th e output capacitor absorbs the excess current from the inductor during this time. The effective output capacitance, COUT, requirements can be calculated from the equations below. The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated by: ) Eq. 9 An output capacitor with large capacitance and low ESR is the best option. For most applications, a 22µF to 68µF ceramic capacit or is sufficient. To meet the load transient requirements, the calculated COUT should satisfy the following inequality: ) Eq. 10 Where: ITrans is the load transient ∆VOvershoot is the maximum output overshoot voltage ∆VUndershoot is the maximum output undershoot voltage
14 Bootstrap Capacitor and Low-Dropout (LDO) Operation
To ensure proper operation, a ceramic capacitor must be connected between the BST and SW pins. A 100nF ceramic capacitor is sufficient. If the bootstrap capacitor voltage falls below 2.3V, the boot undervoltage protection circuit turns Q2 on for 220ns to refresh the bootstrap capacitor and raise its voltage back above 2. 85V. The bootstrap capacitor voltage threshold is always maintained to ensure enough driving capability for Q1. This operation may arise during long periods of no switching such as in PFM with light load conditions. Another event that re quires the refreshing of the bootstrap capacitor is when the input voltage drops close to the output voltage. Under this cond ition, the regulator enters low-dropout mode by holding Q1 on for multiple clock cycles. To prevent the bootstrap capacitor from discharging, Q2 is forced to refresh. The effective duty cycle is approximately 100% so that it acts as an LDO to maintain the output voltage regulation.
- The AP63300/AP63301 works at 3A load current so heat dissipation is a major concern in the layout of the PCB. 2oz copper for both the top
and bottom layers is recommended.
- Place the input capacitors as closely across VIN and GND as possible.
- Place the inductor as close to SW as possible.
- Place the output capacitors as close to GND as possible.
- Place the feedback components as close to FB as possible.
- If using four or more layers, use at least the 2nd and 3rd layers as GND to maximize thermal performance.
- Add as many vias as possible around both the GND pin and under the GND plane for heat dissipation to all the GND layers.
- Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers.
- See Figure 39 for more details.
Figure 39. Recommended PCB Layout
Document number: DS42002 Rev. 3 - 2 20 of 22 www.diodes.com August 2019 © Diodes Incorporated AP63300/AP63301
Ordering Information
7: Tape & ReelWU: TSOT260: AP63300 1: AP63301 PackingProduct Version Part Number Operation Mode FSS Feature Package Code Tape and Reel Quantity Part Number Suffix AP63300WU-7 PFM/PWM Yes WU 3000 -7 AP63301WU-7 PWM Only No WU 3000 -7 Marking Information TSOT26 1 2 3 XX Y W X XX : Identification Code Y : Year 0~9 X : Internal Code ( Top View ) W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week Part Number Package Identification Code AP63300WU-7 TSOT26 T6 AP63301WU-7 TSOT26 T7
Document number: DS42002 Rev. 3 - 2 21 of 22 www.diodes.com August 2019 © Diodes Incorporated AP63300/AP63301 Package Outline Dimensions Please see http://www.diodes.com/package-outlines.html for the latest version. TSOT26 TSOT26 Dim Min Max Typ A — 1.00 — A1 0.010 0.100 — A2 0.840 0.900 — D 2.800 3.000 2.900 E 2.800 BSC E1 1.500 1.700 1.600 b 0.300 0.450 — c 0.120 0.200 — e 0.950 BSC e1 1.900 BSC L 0.30 0.50 — L2 0.250 BSC θ 0° 8° 4° θ1 4° 12° — All Dimensions in mm Suggested Pad Layout Please see http://www.diodes.com/package-outlines.html for the latest version. TSOT26 Dimensions Value (in mm) C 0.950 X 0.700 Y 1.000 Y1 3.199 D E1/2 E E/2 e A Seating Plane0 L Gauge Plane 01(4x) 01(4x) c b Seating Plane C X Y
Document number: DS42002 Rev. 3 - 2 22 of 22 www.diodes.com August 2019 © Diodes Incorporated AP63300/AP63301 IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other c hanges without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license unde r its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products d escribed herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diod es Incorporated website, harmless against all damages. Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel. Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application. Products described herein may be covered by one or more United States, international or foreign patents pending. Product name s and markings noted herein may also be covered by one or more United States, international or foreign trademarks. This document is written in English but may be translated into multiple languages for reference. Only the English version of this docum ent is the final and determinative format released by Diodes Incorporated. LIFE SUPPORT Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein: A. Life support devices or systems are devices or systems which: 1. are intended to implant into the body, or 2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided i n the labeling can be reasonably expected to result in significant injury to the user. B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or to affect its safety or effectiveness. Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety -critical, life support devices or systems, notwithstanding any devices - or systems -related information or support that may be provided by Diodes Incorporated. Further, Cust omers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems. Copyright © 2019, Diodes Incorporated www.diodes.com