AP63200Q DIODES | Alldatasheet
Document overview
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Technical content
Features
AEC-Q100 Qualified for Automotive Applications Device Temperature Grade 1: -40°C to +125°C TA Range VIN: 3.8V to 32V Output Voltage (VOUT) 0.8V to VIN: AP63200Q and AP63201Q Fixed 3.3V: AP63203Q Fixed 5V: AP63205Q 2A Continuous Output Current 0.8V ± 1% Reference Voltage 22µ A Low Quiescent Current (Pulse Frequency Modulation) Switching Frequency 500kHz: AP63200Q and AP63201Q 1100kHz: AP63203Q and AP63205Q Supports Pulse Frequency Modulation (PFM) AP63200Q, AP63203Q, and AP63205Q Up to 88% Efficiency at 5mA Light Load Pulse Width Modulation (PWM) Regardless of Output Load AP63201Q Proprietary Gate Driver Design for Best EMI Reduction Frequency Spread Spectrum (FSS) to Reduce EMI AP63200Q, AP63203Q, and AP63205Q Low-Dropout (LDO) Mode Precision Enable Threshold to Adjust UVLO Protection Circuitry Undervoltage Lockout (UVLO) Output Overvoltage Protection (OVP) Cycle-by-Cycle Peak Current Limit Thermal Shutdown Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) The AP63200Q, AP63201Q, AP63203Q, and AP63205Q are suitable for automotive applications requiring specific change control; these parts are AEC-Q100 qualified, PPAP capable, and manufactured in IATF 16949 certified facilities. https://www.diodes.com/quality/product-definitions/ Pin Assignments 3 4 6FB EN VIN GND SW BST TSOT26 (Top View)
Applications
Automotive Power Systems Automotive Infotainment Automotive Instrument Clusters Automotive Body Electronics and Lighting Automotive Telematics Advanced Driver Assistance Systems Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen - and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.
FB 1 Feedback sensing terminal for the output voltage. Connect this pin to the resistive divider of the output. See Setting the Output Voltage section for more details. adjusting the UVLO. See Enable section for more details. switching of the IC. See Input Capacitor section for more details. capacitor is recommended from BST to SW to power the high-side driver. Figure 7. Functional Block Diagram
AP63200Q/AP63201Q/AP63203Q/AP63205Q Document number: DS43698 Rev. 1 - 2 5 of 30 www.diodes.com September 2021 © Diodes Incorporated AP63200Q/AP63201Q/AP63203Q/AP63205Q Absolute Maximum Ratings (Note 4) (@ TA = +25° C, unless otherwise specified.) Symbol Parameter Rating Unit VIN Supply Pin Voltage -0.3 to +35.0 (DC) V -0.3 to +40.0 (400ms) VFB Feedback Pin Voltage -0.3 to +6.0 V VEN Enable/UVLO Pin Voltage -0.3 to +35.0 V VSW Switch Pin Voltage -0.3 to VIN + 0.3 (DC) V -2.5 to VIN + 2.0 (20ns) VBST Bootstrap Pin Voltage VSW - 0.3 to VSW + 6.0 V TSTG Storage Temperature -65 to +150 °C TJ Junction Temperature +160 °C TL Lead Temperature +260 °C ESD Susceptibility (Note 5) HBM Human Body Model ±2000 V CDM Charged Device Model ±1500 V Notes: 4. Stresses greater than the Absolute Maximum Ratings specified above can cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not im plied. Device reliability can be affected by exposure to absolute maximum rating conditions for extended periods of time. 5. Semiconductor devices are ESD sensitive and can be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices. Thermal Resistance (Note 6) Symbol Parameter Rating Unit θJA Junction to Ambient TSOT26 89 ° C/W θJC Junction to Case TSOT26 39 ° C/W Note: 6. Test condition for TSOT26: Device mounted on FR-4 substrate, single-layer PC board, 2oz copper, with minimum recommended pad layout. Recommended Operating Conditions (Note 7) (@ TA = +25°C, unless otherwise specified.) Symbol Parameter Min Max Unit VIN Supply Voltage 3.8 32 V VOUT Output Voltage 0.8 VIN V TA Operating Ambient Temperature -40 +125 °C TJ Operating Junction Temperature -40 +150 °C Note: 7. The device function is not guaranteed outside of the recommended operating conditions.
AP63200Q/AP63201Q/AP63203Q/AP63205Q Document number: DS43698 Rev. 1 - 2 6 of 30 www.diodes.com September 2021 © Diodes Incorporated AP63200Q/AP63201Q/AP63203Q/AP63205Q Electrical Characteristics (@ TJ = +25° C, VIN = 12V, unless otherwise specified. Min/Max limits apply across the recommended operating junction temperature range, -40° C to +150° C, and input voltage range, 3.8V to 32V, unless otherwise specified.) Symbol Parameter Conditions Min Typ Max Unit ISHDN Shutdown Supply Current VEN = 0V — 1 — μA IQ Quiescent Supply Current AP63200Q: L = Open, VEN = Floating, VFB = 1.0V — 22 — μA AP63201Q: L = Open, VEN = Floating, VFB = 1.0V — 370 — μA AP63203Q: L = Open, VEN = Floating, VFB = 3.5V — 22 — μA AP63205Q: L = Open, VEN = Floating, VFB = 5.2V — 22 — μA POR VIN Power-on Reset Rising Threshold — — 3.5 3.7 V UVLO VIN Undervoltage Lockout Falling Threshold — — 3.06 — V RDS(ON)1 High-Side Power MOSFET On-Resistance (Note 8) — — 125 — mΩ RDS(ON)2 Low-Side Power MOSFET On-Resistance (Note 8) — — 68 — mΩ IPEAK_LIMIT HS Peak Current Limit (Note 8) From Drain to Source 2.35 2.8 3.25 A IVALLEY_LIMIT LS Valley Current Limit (Note 8) From Source to Drain — 3.2 — A fSW Oscillator Frequency AP63200Q/AP63201Q, CCM 450 500 550 kHz AP63203Q/AP63205Q, CCM 990 1100 1210 kHz tON_MIN Minimum On-Time — — 80 — ns VFB Feedback Voltage AP63200Q/AP63201Q, CCM 0.792 0.800 0.808 V AP63203Q, CCM 3.267 3.300 3.333 V AP63205Q, CCM 4.950 5.000 5.050 V VEN_H EN Logic High Threshold — — 1.18 1.25 V VEN_L EN Logic Low Threshold — 1.03 1.09 — V IEN EN Input Current VEN = 1.5V — 5.5 — μA VEN = 1V 1.0 1.5 2.0 μA tSS Soft-Start Time — — 4 — ms TSD Thermal Shutdown (Note 8) — — +160 — °C THys Thermal Shutdown Hysteresis (Note 8) — — +25 — °C Note: 8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.
AP63200Q/AP63201Q/AP63203Q/AP63205Q Document number: DS43698 Rev. 1 - 2 21 of 30 www.diodes.com September 2021 © Diodes Incorporated AP63200Q/AP63201Q/AP63203Q/AP63205Q
Application Information
1 Pulse Width Modulation (PWM) Operation
The AP63200Q/AP63201Q/AP63203Q/AP63205Q device is an automotive-compliant, 3.8V-to-32V input, 2A output, EMI friendly, fully integrated synchronous buck converter. Refer to the block diagram in Figure 7. The device employs fixed-frequency peak current mode control. The internal clock’s rising edge (500kHz for AP63200Q/AP63201Q, 1100kHz for AP63203Q/Ap 63205Q) initiates turning on the integrated high -side power MOSFET, Q1, for each cycle. When Q1 is on , the inductor current rises linearly and the device charges the output capacitor. The current across Q1 is sensed and converted to a voltage with a ratio of RT via the CSA block. The CSA output is combined with an internal slope compensation, SE, resulting in VSUM. When VSUM rises higher than the COMP node, the device turns off Q1 and turns on the low -side power MOSFET, Q2. The inductor current decreases when Q2 is on. On the rising edge of next clock cycle, Q2 turns off and Q1 turns on. This sequence repeats every clock cycle. The error amplifier generates the COMP voltage by comparing the voltage on the FB pin with an internal 0.8V reference. An increase in load current causes the feedback voltage to drop. The error amplifier thus raises the COMP voltage until the average i nductor current matches the increased load current. This feedback loop regulates the output voltage. The internal slope compensation circuitry prevent s subharmonic oscillation when the duty cycle is greater than 50% for peak current mode control. The peak current mode control , integrated loop compensation network, and built -in 4 ms soft -start time simplifies the AP63200Q/AP63201Q/AP63203Q/AP63205Q footprint as well as minimizes the external component count. In order to provide a small output ripple during light load conditions, the AP63201Q operates in PWM regardless of output load.
2 Pulse Frequency Modulation (PFM) Operation
In heavy load conditions, the AP63200Q/AP63203Q/AP63205Q operates in forced PWM mode. As the load current decreases, the internal COMP node voltage also decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from decreasing any further. The voltage at which COMP is clamped corresponds to the 600mA PFM peak inductor current limit. As the load current approaches zero, the AP63200Q/AP63203Q/AP63205Q enters PFM mode to increase the converter power efficiency at light load conditions. When the inductor current decreases to 50mA, zero cross detection circuitry on the low-side power MOSFET, Q2, forces it off. The buck converter does not sink current from the output when the output load is light and while the device is in PFM. Because the AP63200Q/AP63203Q/AP63205Q works in PFM during light load conditions, it can achieve power efficiency of up to 88% at a 5mA load condition. The quiescent current of AP63200Q/AP63203Q/AP63205Q is 22μA typical under a no-load, non-switching condition.
3 Enable
When disabled, the device shutdown supply current is only 1μA. When applying a voltage greater than the EN logic high threshold (typical 1.18V, rising), the AP63200Q/AP63201Q/AP63203Q/AP63205Q enables all functions and the device initiates the soft-start phase. The EN pin is a high - voltage pin and can be directly conn ected to VIN to automatically start up the device as VIN increases. An internal 1.5µ A pull-up current source connected from the internal LDO-regulated VCC to the EN pin guarantees that if EN is left floating, the device still automatically enables once the voltage reaches the EN logic high threshold. The AP63200Q/AP63201Q/AP63203Q/AP63205Q has a built-in 4ms soft-start time to prevent output voltage overshoot and inrush current. When the EN voltage falls below its logic low threshold (typical 1.09V, falling), the internal SS voltage discharges to ground and device operation disables. The EN pin can also be used to adjust the undervoltage lockout thresholds. See Undervoltage Lockout (UVLO) section for more details. Alternatively, a small ceramic capacitor can be added from EN to GND. When EN is not driven externally, this capacitor increases the time needed for the EN pin voltage to reach its logic high threshold, which delays the startup of the output voltage. This is useful when sequencing multiple power rails to minimize input inrush current. When the EN pin voltage starts from 0V, t he amount of capacitance for a given delay time is approximated by: 𝐂𝐝[𝐧𝐅] ≈ 𝟏. 𝟐𝟕 ∙ 𝐭𝐝[𝐦𝐬] Eq. 1 Where: Cd is the time delay capacitance in nF td is the delay time in ms
and fall slew rates as well as the converter’s power efficiency. To further improve EMI reduc tion, the AP63200Q/AP63203Q/AP63205Q device also implements FSS with a switching frequency jitter of ± 6%. not allowing emitted energy to stay in any one frequency for a significant period of time. inductor current is 0A. See Figure 73 for an example waveform. Figure 73. AP63203Q/AP63205Q SW Pin Waveform
5 Adjusting Undervoltage Lockout (UVLO)
disables if the input voltage falls below 3.06V. In this UVLO event, both the high-side and low-side power MOSFETs turn off. on the EN pin along with an external resistive divider (R3 and R4) configures the VIN UVLO threshold voltages as shown in Figure 74. Figure 74. Adjusting UVLO
AP63200Q/AP63201Q/AP63203Q/AP63205Q Document number: DS43698 Rev. 1 - 2 23 of 30 www.diodes.com September 2021 © Diodes Incorporated AP63200Q/AP63201Q/AP63203Q/AP63205Q Application Information (continued)
5 Adjusting Undervoltage Lockout (UVLO) (continued)
The resistive divider resistor values are calculated by: 𝐑𝟑 = 𝟎. 𝟗𝟐𝟒 ∙ 𝐕𝐎𝐍 − 𝐕𝐎𝐅𝐅 𝟒. 𝟏𝟏𝟒𝛍𝐀 Eq. 2 𝐑𝟒 = 𝟏. 𝟎𝟗 ∙ 𝐑𝟑 𝐕𝐎𝐅𝐅 − 𝟏. 𝟎𝟗𝐕 + 𝟓. 𝟓𝛍𝐀 ∙ 𝐑𝟑 Eq. 3 Where: VON is the rising edge VIN voltage to enable the regulator and is greater than 3.7V VOFF is the falling edge VIN voltage to disable the regulator and is greater than 3.26V
6 Output Overvoltage Protection (OVP)
The AP63200Q/AP63201Q/AP63203Q/AP63205Q implements output OVP circuitry to minimize output voltage overshoots during decreasing load transients. The high-side power MOSFET turns off , and the low-side power MOSFET turns on , when the feedback voltage exceeds 110% of the 0.8V internal reference voltage in order to prevent the output voltage from continuing to increase.
7 Overcurrent Protection (OCP)
The AP63200Q/AP63201Q/AP63203Q/AP63205Q has cycle-by-cycle peak current limit protection by sensing the current through the internal high-side power MOSFET, Q1. While Q1 is on, the internal sensing circuitry monitors its conduction current. Once the current through Q1 exceeds the peak current limit, Q1 immediately turns off. If Q1 consistently hits the peak current limit for 512 cycles, the buck converter enters hiccup mode and shuts down. After 8192 cycles of down time, the buck converter restarts powering up. Hiccup mode reduces the power dissip ation in the overcurrent condition.
8 Thermal Shutdown (TSD)
If the junction temperature of the device reaches the thermal shutdown limit of +160° C, the AP63200Q/AP63201Q/AP63203Q/AP63205Q shuts down both its high-side and low-side power MOSFETs. When the junction temperature reduces to the required level ( +135° C typical), the device initiates a normal power-up cycle with soft-start.
9 Power Derating Characteristics
To prevent the regulator from exceeding the maximum recommended operating junction temperature, some thermal analysis is requ ired. The regulator’s temperature rise is given by: 𝐓𝐑𝐈𝐒𝐄 = 𝐏𝐃 ∙ (𝛉𝐉𝐀) Eq. 4 Where: PD is the power dissipated by the regulator θJA is the thermal resistance from the junction of the die to the ambient temperature The junction temperature, TJ, is given by: 𝐓𝐉 = 𝐓𝐀 + 𝐓𝐑𝐈𝐒𝐄 Eq. 5 Where: TA is the ambient temperature of the environment
9 Power Derating Characteristics (continued)
temperature of +150° C when considering the thermal design. Figure 75 and Figure 76 show typical derating curves versus ambient temperature. Figure 75. Output Current Derating Curve vs. Ambient Temperature, AP63200Q/AP63201Q, VIN = 12V Figure 76. Output Current Derating Curve vs. Ambient Temperature, AP63203Q/AP63205Q, VIN = 12V
10 Setting the Output Voltage
improves efficiency at light loads. However, values too high cause the device to be more susceptible to noise affecting its output voltage accuracy.
10 Setting the Output Voltage (continued)
Table 1 shows a list of recommended component selections for common AP63200Q/AP63201Q output voltages referencing Figure 1. Table 1. Recommended Component Selections for AP63200Q/AP63201Q AP63205Q referencing Figure 4. Table 2. Recommended Component Selections for AP63203Q Table 3. Recommended Component Selections for AP63205Q
11 Inductor
For the AP63200Q/AP63201Q/AP63203Q/AP63205Q, choose ∆IL to be 30% to 40% of the maximum load current of 2A. than 30mΩ. Use a larger inductance for improved efficiency under light load conditions.
AP63200Q/AP63201Q/AP63203Q/AP63205Q Document number: DS43698 Rev. 1 - 2 26 of 30 www.diodes.com September 2021 © Diodes Incorporated AP63200Q/AP63201Q/AP63203Q/AP63205Q Application Information (continued)
12 Input Capacitor
The input capacitor reduces both the surge current drawn from the input supply as well as the switching noise from the device. The input capacitor must sustain the ripple current produced during the on -time of Q1. It must have a low ESR to minimize power dissipation due to the RMS input current. The RMS current rating of the input capacitor is a critical parameter and must be higher than the RMS input current. As a rule of thu mb, select an input capacitor with an RMS current rating greater than half of the maximum load current. Due to large dI/dt through the input capacitor, electrolytic or ceramic capacitors with low ESR should be used. If using a tantalum capacitor, it must be surge protected or else capacitor failure could occur. Using a ceramic capacitor of 10µ F or greater is sufficient for most applications.
13 Output Capacitor
The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces both the overshoots and undershoots of the output voltage during load transients. During the first few micro seconds of an increasing load transient, the converter recognizes the change from steady-state and enters 100% duty cycle to supply more current to the load. However, the inductor limits the change to increasing cu rrent depending on its inductance. Therefore, the output capacitor supplies the difference in current to the load during this time. Likewise, during the first few microseconds of a decreasing load transient, the converter recognizes the change from steady -state and sets the on -time to minimum to reduce the cu rrent supplied to the load. However, the inductor limits the change in decreasing current as well. Therefore, the output capacitor absorbs the excess current from the inductor during this time. The effective output capacitance, COUT, requirements can be calculated from the equations below. The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated by: 𝐕𝐎𝐔𝐓𝐑𝐢𝐩𝐩𝐥𝐞 = ∆𝐈𝐋 ∙ (𝐄𝐒𝐑 + 𝟏 𝟖 ∙ 𝐟𝐬𝐰 ∙ 𝐂𝐎𝐔𝐓) Eq. 9 Output capacitors with large capacitance and low ESR are the best option. For most applications, a total capacitance of 2 x 22 µ F using ceramic capacitors is sufficient. To meet the load transient requirements, the calculated COUT should satisfy the following inequality: 𝐂𝐎𝐔𝐓 > 𝐦𝐚𝐱 ( 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 ∆𝐕𝐎𝐯𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ 𝐕𝐎𝐔𝐓 , 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 ∆𝐕𝐔𝐧𝐝𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ (𝐕𝐈𝐍 − 𝐕𝐎𝐔𝐓)) Eq. 10 Where: ITrans is the load transient ∆VOvershoot is the maximum output overshoot voltage ∆VUndershoot is the maximum output undershoot voltage
14 Bootstrap Capacitor and Low-Dropout (LDO) Operation
To ensure proper operation, a ceramic capacitor must be connected between the BST and SW pins to supply the drive voltage for the high -side power MOSFET. A 100nF ceramic capacitor is sufficient. If the bootstrap capacitor voltage falls below 2.3V, the boot undervoltage protection circuit turns Q2 on for 220ns to refresh the bootstrap capacitor and raise its voltage back above 2.85V. The bootstrap capacitor’s voltage is always maintained to ensure enough driving capability for Q1. This operation may arise during long periods of no switching such as in PFM with light load conditions. Another event that requires the refreshing of the bootstrap capacitor is when the input voltage drops close to the output voltage. Under this condition, the regulator enters low -dropout mode by holding Q1 on for multiple clock cycles. To prevent the bootstrap capacitor from discharging, Q2 is forced to refresh. The effective duty cycle is approximately 100% so that it acts as an LDO to maintain the output voltage regulation.
- The AP63200Q/AP63201Q/AP63203Q/AP63205Q works at 2A load current so heat dissipation is a major concern in the layout of the PCB.
2oz copper for both the top and bottom layers is recommended.
- Place the input capacitors as closely across VIN and GND as possible.
- Place the inductor as close to SW as possible.
- Place the output capacitors as close to GND as possible.
- Place the feedback components as close to FB as possible, if applicable. If using AP63203Q/AP63205Q, tie the FB pin directly to VOUT as
there is no need for R1, R2, or C4.
- If using four or more layers, use at least the 2nd and 3rd layers as GND to maximize thermal performance.
- Add as many vias as possible around both the GND pin and under the GND plane for heat dissipation to all the GND layers.
- Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers.
- See Figure 77 for more details.
Figure 77. Recommended PCB Layout
AP63200Q/AP63201Q/AP63203Q/AP63205Q Document number: DS43698 Rev. 1 - 2 28 of 30 www.diodes.com September 2021 © Diodes Incorporated AP63200Q/AP63201Q/AP63203Q/AP63205Q
Ordering Information
WU : TSOT26 AP6320XQ X - X 7 : Tape & Reel0 : AP63200Q 1 : AP63201Q 3 : AP63203Q 5 : AP63205Q Package PackingProduct Version Part Number Output Voltage (V) Switching Frequency (kHz) Operation Mode FSS Feature Package Code Tape and Reel Quantity Part Number Suffix AP63200QWU-7 Adjustable 500 PFM/PWM Yes WU 3,000 -7 AP63201QWU-7 Adjustable 500 PWM Only No WU 3,000 -7 AP63203QWU-7 3.3 1100 PFM/PWM Yes WU 3,000 -7 AP63205QWU-7 5.0 1100 PFM/PWM Yes WU 3,000 -7 Marking Information TSOT26 1 2 3 XXX Y W X XXX : Identification Code Y : Year 0~9 X : Internal Code ( Top View ) W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week Part Number Package Identification Code AP63200QWU-7 TSOT26 T2Q AP63201QWU-7 TSOT26 T3Q AP63203QWU-7 TSOT26 T4Q AP63205QWU-7 TSOT26 T5Q
AP63200Q/AP63201Q/AP63203Q/AP63205Q Document number: DS43698 Rev. 1 - 2 29 of 30 www.diodes.com September 2021 © Diodes Incorporated AP63200Q/AP63201Q/AP63203Q/AP63205Q Package Outline Dimensions Please see http://www.diodes.com/package-outlines.html for the latest version. TSOT26 TSOT26 Dim Min Max Typ A — 1.00 — A1 0.010 0.100 — A2 0.840 0.900 — D 2.800 3.000 2.900 E 2.800 BSC E1 1.500 1.700 1.600 b 0.300 0.450 — c 0.120 0.200 — e 0.950 BSC e1 1.900 BSC L 0.30 0.50 — L2 0.250 BSC θ 0° 8° 4° θ1 4° 12° — All Dimensions in mm Suggested Pad Layout Please see http://www.diodes.com/package-outlines.html for the latest version. TSOT26 Dimensions Value (in mm) C 0.950 X 0.700 Y 1.000 Y1 3.200 Mechanical Data Moisture Sensitivity: Level 1 per J-STD-020 Terminals: Finish – Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 Weight: 0.013 grams (Approximate) D E1/2 E E/2 e A Seating Plane0 L Gauge Plane 01( 4x) 01( 4x) c b Seating Plane C X Y
AP63200Q/AP63201Q/AP63203Q/AP63205Q Document number: DS43698 Rev. 1 - 2 30 of 30 www.diodes.com September 2021 © Diodes Incorporated AP63200Q/AP63201Q/AP63203Q/AP63205Q IMPORTANT NOTICE 1. DIODES INCORPORATED AND ITS SUBSIDIARIES (“DIODES”) MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTIC ULAR PURPOSE OR NON -INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operati on of Diodes products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. 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