AP62500
Document overview
- Manufacturer or author: Diodes Incorporated
- PDF pages: 27
Technical content
Features
VIN: 4.5V to 18V Output Voltage (VOUT): 0.6V to 7V 5A Continuous Output Current 0.6V ± 1% Reference Voltage 195μA Quiescent Current Selectable Switching Frequency 400kHz 800kHz 1.2MHz Selectable Operation Modes Pulse Frequency Modulation (PFM) Ultrasonic Mode (USM) Pulse Width Modulation (PWM) Programmable Soft-Start Time Proprietary Gate Driver Design for Best EMI Reduction Power-Good Indicator with 5MΩ Internal Pull-Up Resistor Precision Enable Threshold to Adjust UVLO Protection Circuitry Undervoltage Lockout (UVLO) Cycle-by-Cycle Valley Current Limit Thermal Shutdown Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product -definitions/ Pin Assignments 12 11 10 9 3 4 5 6 PGND VIN BST SW EN MODE FSEL PG VCC SS/TR GND FB (Top View) V-QFN2030-12 (Type A)
Applications
5V and 12V Distributed Power Bus Supplies Television Sets and Monitors White Goods and Small Home Appliances FPGA, DSP, and ASIC Supplies Home Audio Network Systems Gaming Consoles Consumer Electronics General Purpose Point of Load Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant . 2. See https://www.diodes.com/quality/lead -free/ for more information about Diodes Incorporated’s definitions of Halogen - and Antimony -free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlori ne (<1500ppm total Br + Cl) and <1000ppm antimony compounds .
Document number: DS44664 Rev. 1 - 2 3 of 27 www.diodes.com November 2022 © Diodes Incorporated AP62500
Document number: DS44664 Rev. 1 - 2 4 of 27 www.diodes.com November 2022 © Diodes Incorporated AP62500 Pin Descriptions Pin Name Pin Number Function PGND 1 Power Ground. PGND must be connected to a single point ground and to as large a PGND plane as possible on the PCB for proper operation and optimized thermal performance. VIN 2 Power Input. VIN supplies the power to the IC as well as the step-down converter power MOSFETs. Drive VIN with a 4.5V to 18V power source. Bypass VIN to GND with a suitably large capacitor to eliminate noise due to the switching of the IC. See Input Capacitor section for more details. EN 3 Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator and low to turn it off. It can be left open for automatic startup. The EN has a precision threshold of 1.18V for programing the UVLO. See Enable section for more details. MODE 4 MODE Select. MODE is used to select the operation mode of the device. Connect MODE to GND to program the device to operate in PFM Mode. Leave MODE floating to program the device to operate in USM. Connect MODE to VCC to program the device to operate in PWM Only Mode. FSEL 5 Frequency Select. FSEL is used to select the switching frequency of the device. Connect FSEL to GND to program the switching frequency to 400kHz. Leave FSEL floating to program the switching frequency to 800kHz. Connect FSEL to VCC to program the switching frequency to 1.2MHz. PG 6 Power-Good. PG is an open-drain output that is pulled to GND when the output voltage is out of its regulation limits or during soft-start. Connect an external pull-up resistor from PG to VCC. BST 7 High-Side Gate Drive Boost Input. BST supplies the drive voltage for the high-side N-Channel power MOSFET. A 100nF capacitor is recommended from BST to SW to power the high-side driver. SW 8 Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC fil ter from SW to the output load. VCC 9 Internal Power Supply. VCC supplies the internal logic circuitry as well as the gate drivers. Connect a 1μF capacitor as close as possible to VCC and PGND. This pin is not active when EN is low. SS/TR 10 Soft-start and Tracking. SS/TR controls the soft-start, tracking, and sequencing of the output. Connect a ceramic capacitor from SS/TR to GND to program the soft -start time. Leave SS/TR floating to use the internal soft-start. See Soft-Start, Tracking, and Sequencing section for more details. GND 11 Ground. GND is the main power ground for the control logic circuitry. It must have a Kelvin Connection to PGND. FB 12 Feedback. FB is the sensing terminal for the output voltage . Connect this pin to the resistive divider of the output. See Setting the Output Voltage section for more details.
Figure 4. Functional Block Diagram
Document number: DS44664 Rev. 1 - 2 6 of 27 www.diodes.com November 2022 © Diodes Incorporated AP62500 Absolute Maximum Ratings (Note 4) (@ TA = +25°C, unless otherwise specified.) Symbol Parameter Rating Unit VIN Supply Pin Voltage -0.3 to +20.0 (DC) V -0.3 to 22.0 (400ms) VCC VCC Pin Voltage -0.3 to +6.0 V VEN Enable/UVLO Pin Voltage -0.3 to +20.0 V VMODE MODE Select Pin Voltage -0.3 to +6.0 V VFSEL Frequency Select Pin Voltage -0.3 to +6.0 V VPG Power-Good Pin Voltage -0.3 to +6.0 V VBST Bootstrap Pin Voltage VSW - 0.3 to VSW + 6.0 V VSW Switch Pin Voltage -1.0 to VIN + 0.3 (DC) V -2.5 to VIN + 2.0 (20ns) VSS/TR Soft-Start/Tracking Pin Voltage -0.3 to +6.0 V VFB Feedback Pin Voltage -0.3 to +6.0 V TST Storage Temperature -65 to +150 °C TJ Junction Temperature +160 °C TL Lead Temperature +260 °C ESD Susceptibility (Note 5) HBM Human Body Model ±2000 V CDM Charged Device Model ±500 V Notes: 4. Stresses greater than the Absolute Maximum Ratings specified above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specifica tion is not implied. Device reliability may be affected by exposure to absolute maximum rating conditions for extended periods of time. 5. Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices. Thermal Resistance (Note 6) Symbol Parameter Rating Unit θJA Junction to Ambient V-QFN2030-12 (Type A) 40 °C/W θJC Junction to Case V-QFN2030-12 (Type A) 5.5 °C/W Note: 6. Test condition for V-QFN2030 -12: Device mounted on FR -4 substrate, four-layer PCB, 2oz copper, with minimum recommended pad layout . Recommended Operating Conditions (Note 7) (@ TA = +25°C, unless otherwise specified.) Symbol Parameter Min Max Unit VIN Supply Voltage 4.5 18.0 V VOUT Output Voltage 0.6 7.0 V TA Operating Ambient Temperature -40 +85 °C TJ Operating Junction Temperature -40 +125 °C Note: 7. The device function is not guaranteed outside of the recommended operating conditions.
Document number: DS44664 Rev. 1 - 2 7 of 27 www.diodes.com November 2022 © Diodes Incorporated AP62500 Electrical Characteristics (@ TJ = +25°C, VIN = 12V, VCC=5V, unless otherwise specified. Min/Max limits apply across the recommended junction temperature range, -40°C to +125°C, and input voltage range, 4.5V to 18V, unless otherwise specified. ) Symbol Parameter Conditions Min Typ Max Unit ISHDN Shutdown Supply Current VEN = 0V — 1 — μA IQ Quiescent Supply Current VFB = 0.85V — 195 — μA POR VIN Power-on Reset Rising Threshold — 4.0 4.25 4.45 V UVLO VIN Undervoltage Lockout Falling Threshold — — 3.95 — V VCC VCC Output Voltage 6.0V < VIN < 18V, 0 < IVCC < 5mA 4.75 5.0 5.25 V IVCC VCC Current Source VIN = 6V, VCC = 0V — — 35 mA RDS(ON)1 High-Side Power MOSFET On -Resistance (Note 8) — — 47 — mΩ RDS(ON)2 Low-Side Power MOSFET On -Resistance (Note 8) — — 18 — mΩ IVALLEY_LIMIT LS Valley Current Limit (Note 8) From Source to Drain 6.0 7.0 8.0 A INCL LS Negative Current Limit From Drain to Source — 2.5 — A fSW Oscillator Frequency VFSEL = GND, VOUT = 5V, CCM — 400 — kHz VFSEL = Floating, VOUT = 5V, CCM — 800 — kHz VFSEL = VCC, VOUT = 5V, CCM — 1200 — kHz VMODE_PFM PFM Mode Logic Threshold VMODE = GND — — 0.7 V VMODE_USM Ultrasonic Mode Logic Threshold VMODE = Floating — 2.5 — V VMODE_PWM PWM Mode Logic Threshold VMODE = VCC 4.2 — — V tON_MIN Minimum On-Time — — 70 — Ns tOFF_MIN Minimum Off-Time — — 255 — Ns VFB Feedback Voltage CCM 0.594 0.600 0.606 V VEN_H EN Logic High Threshold — — 1.20 1.25 V VEN_L EN Logic Low Threshold — 1.03 1.12 — V IEN EN Input Current VEN = 1.5V — 5.1 — μA VEN = 1V 1.0 1.4 2.0 μA tSS Soft-Start Time VSS/TR = Floating — 1 — ms ISS Soft-Start Current Source VSS/TR = 1.2V — 5 — μA PGUV_FALL Undervoltage Falling Threshold Percent of Output Regulation, Fault — 85 — % PGUV_RISE Undervoltage Rising Threshold Percent of Output Regulation, Good — 95 — % PGOV_RISE Overvoltage Rising Threshold Percent of Output Regulation, Fault — 115 — % PGOV_FALL Overvoltage Falling Threshold Percent of Output Regulation, Good — 105 — % tPG_RD Power-Good Rise Delay Time — — 0.5 — ms VPG_OL Power-Good Output Logic Low IPG = -3mA — — 0.4 V TSD Thermal Shutdown (Note 8) — — 160 — °C THYS Thermal Shutdown Hysteresis (Note 8) — — 30 — °C Note: 8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.
Document number: DS44664 Rev. 1 - 2 16 of 27 www.diodes.com November 2022 © Diodes Incorporated AP62500
Application Information
1 Pulse Width Modulation (PWM) Operation
The AP62500 device is a 4. 5V-to-18V input, 5A output, EMI friendly, fully integrated synchronous buck converter. Refer to the block diagram in Figure 4. The device employs constant on -time control to provide fast transient response and easy loop stabilization. At the beg inning of each voltage, which then triggers the on-time duration to start again. The minimum off -time is 255ns typical. Connecting the MODE pin to VCC pro grams the device to operate in PWM Mode regardless of output load.
2 Pulse Frequency Modulation (PFM) and Ultrasonic Mode (USM) Operation
cycle begins, and Q1 turns on. AP62500 enters USM during light load conditions when the MODE pin is left floating. USM is similar to PFM Mode but with one key diffe rence. amount of time to force switching action on SW. The quiescent current of AP62500 is 195μA typical under a no-load, non-switching condition.
3 Enable
4 Soft-Start, Tracking, and Sequencing
capacitance, which programs the same soft -start time for each device. See Figure 47 and Figure 48 for more details. Figure 47. Ratiometric Tracking Configuration Figure 48. Ratiometric Tracking Function
4 Soft-start, Tracking, and Sequencing (continued)
IC#2. See Figure 49 and Figure 50 for more details. Figure 49. Coincidental Tracking Configuration Figure 50. Coincidental Tracking Function from low to high and enables the start -up sequence of IC#2. See Figure 51 and Figure 52 for more details. Figure 51. Output Sequencing Configuration Figure 52. Output Sequencing Function
5 Electromagnetic Interference (EMI) Reduction with Ringing-Free Switching Node
6 Power-Good (PG) Indicator
rising edge transition is delayed by 0.5ms. Connect an external pull-up resistor of 100kΩ from PG to VCC.
7 Adjusting Undervoltage Lockout (UVLO)
high-side and low-side power MOSFETs turn off. source on the EN pin along with an external resistive divider (R3 and R4) configures the VIN UVLO threshold voltages as shown in Figure 53. Figure 53. Programming UVLO
8 Overcurrent Protection (OCP)
converter restarts powering up. Hiccup mode reduces the power dissipation in the overcurrent condition. the temperature dependency of R DS(ON).
9 Thermal Shutdown (TSD)
10 Power Derating Characteristics
Figure 54. Output Current Derating Curve vs. Ambient Temperature, VIN = 12V, fSW = 800kHz
11 Setting the Output Voltage
additional external components. Consult Diodes Incorporated for more information if such output voltages are required. Table 1. Recommended Component Selections
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12 Inductor
Calculating the inductor value is a critical factor in designing a buck converter. For most designs, the following equation c an be used to calculate the inductor value: 𝐋 = 𝐕𝐎𝐔𝐓 ∙ (𝐕𝐈𝐍 − 𝐕𝐎𝐔𝐓) 𝐕𝐈𝐍 ∙ ∆𝐈𝐋 ∙ 𝐟𝐒𝐖 Eq. 9 Where: ∆IL is the inductor current ripple fSW is the buck converter switching frequency For AP62500, choose ∆IL to be 30% to 50% of the maximum load current of 5A. The inductor peak current is calculated by: 𝐈𝐋𝐏𝐄𝐀𝐊 = 𝐈𝐋𝐎𝐀𝐃 + ∆𝐈𝐋 𝟐 Eq. 10 Peak current determines the required saturation current rating, which influences the size of the inductor. Saturating the ind uctor decreases the converter efficiency while increasing the temperatures of the inductor and the internal power MOSFETs. Therefore, choosing an inductor with the appropriate saturation current rating is important. For most applications, it is recommended to select an inductor of approx imately 0.47µH to 4.7µH with a DC current rating of at least 35% higher than the maximum load current. For highest efficiency, the inductor’s DC resistanc e should be less than 10mΩ. Use a larger inductance for improved efficiency under light load conditions.
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13 Input Capacitor
The input capacitor reduces both the surge current drawn from the input supply as well as the switching noise from the device. The input capacitor must sustain the ripple current produced during the on -time of Q 1. It must have a low ESR to minimize power dissipation due to the RMS input current. The RMS current rating of the input capacitor is a critical parameter and must be higher than the RMS input current. As a rul e of thumb, select an input capacitor with an RMS current rating greater than half of the maximum load current. Due to large dI/dt through the input capa citor, electrolytic or ceramic capacitors with low ESR should be used. If using a tantalum capacitor, it must be surge protected or else capacito r failure could occur. Using a ceramic capacitor of 22µF or greater is sufficient for most applications.
14 Output Capacitor
The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces both the overshoot s and undershoots of the output voltage during load transients. During the first few micro seconds of a n increasing load transient, the converter recognizes the change from steady -state and sets the off -time to minimum to supply more current to the load. However, the inductor lim its the change to increasing current depending on its inductance. Therefore, the output capacitor supplies the difference in current to the load during this time. Likewise, during the first few microseconds of a decreasing load transient, the converter recognizes the change from steady -state and increases the off -time to reduce the current supplied to the load . However, t he inductor limits the change in decreasing current as well. Therefore, the output capacitor absorbs the excess current from the inductor during this time. The effective output capacitance, COUT , requirements can be calculated from the equations below. The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated by: 𝐕𝐎𝐔𝐓𝐑𝐢𝐩𝐩𝐥𝐞 = ∆𝐈𝐋 ∙ (𝐄𝐒𝐑 + 𝟏 𝟖 ∙ 𝐟𝐒𝐖 ∙ 𝐂𝐎𝐔𝐓) Eq. 11 An output capacitor with large capacitance and low ESR is the best option. For most applications, a total capacitance of 3 x 22µF using ceramic is sufficient. To meet the load transient requirement s, the calculated COUT should satisfy the following inequality: 𝐂𝐎𝐔𝐓 > 𝐦𝐚𝐱 ( 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 ∆𝐕𝐎𝐯𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ 𝐕𝐎𝐔𝐓 , 𝐋 ∙ 𝐈𝐓𝐫𝐚𝐧𝐬 ∆𝐕𝐔𝐧𝐝𝐞𝐫𝐬𝐡𝐨𝐨𝐭 ∙ (𝐕𝐈𝐍 − 𝐕𝐎𝐔𝐓)) Eq. 12 Where: ITrans is the load transient ∆VOvershoot is the maximum output overshoot voltage ∆VUndershoot is the maximum output undershoot voltage
13 Bootstrap Capacitor
To ensure proper operation, a ceramic capacitor must be connected between the BST and SW pins to supply the drive voltage for the high -side power MOSFET. A 100nF ceramic capacitor is sufficient.
- The AP62500 works at 5A load current so heat dissipation is a major concern in the layout of the PCB. 2oz copper for both the top and
bottom layers is recommended.
- Place the input capacitors as closely across VIN and PGND as possible.
- Place the inductor as close to SW as possibl e.
- Place the output capacitors as close to PGND as possible.
- Place the feedback components as close to FB as possible.
- If using four or more layers, use at least the 2 nd and 3rd layers as PGND to maximize thermal performance.
- Add as many vias as possible around both the PGND pin and under the PGND plane for heat dissipation to all the PGND layers.
- Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers.
- See Figure 55 for more details.
Figure 55. Recommended PCB Layout
Document number: DS44664 Rev. 1 - 2 25 of 27 www.diodes.com November 2022 © Diodes Incorporated AP62500 Ordering Information (Note 9) SJ : V-QFN2030-12 (Type A) AP62500 X - X 7 : Tape & Reel Package Packing Orderable Device Package Code Tape and Reel Quantity Part Number Suffix AP62500SJ-7 SJ 3000 -7 Note: 9. For packaging details, go to our website at https://www.diodes.com/design/support/packaging/diodes -packaging/. Marking Information V-QFN2030-12 (Type A) ( Top View ) Y W X XX XX : Identification Code X : Internal Code Y : Year : 0~9 W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week Orderable Device Package Identification Code AP62500SJ-7 V-QFN2030-12 (Type A) KA
Document number: DS44664 Rev. 1 - 2 26 of 27 www.diodes.com November 2022 © Diodes Incorporated AP62500 Package Outline Dimensions Please see http://www.diodes.com/package -outlines.html for the latest version . V-QFN2030-12 (Type A) V-QFN2030-12 (Type A) Dim Min Max Typ A 0.75 0.85 0.80 A1 0.00 0.05 0.02 A3 –– –– 0.203 b 0.20 0.30 0.25 D 1.95 2.05 2.00 E 2.95 3.05 3.00 e 0.50 BSC e1 1.50 BSC e2 1.00 BSC L 0.35 0.45 0.40 L2 1.15 1.25 1.20 z –– –– 0.125 All Dimensions in mm Suggested Pad Layout Please see http://www.diodes.com/package -outlines.html for the latest version . V-QFN2030-12 (Type A) Dimensions Value (in mm) C 0.500 C1 1.000 X 0.350 X1 1.400 X2 1.850 X3 2.300 Y 0.600 Y1 0.350 Y2 3.300 Mechanical Data Moisture Sensitivity: Level 1 per J-STD-020 Terminals: Finish – SnAgCu Plated, Solderable per MIL-STD-202, Method 208 Weight: 0.0114 grams (Approximate) A Seating Plane D E e e L(9x) b(12x) R0.075 L2(3x) z CX Y C
Document number: DS44664 Rev. 1 - 2 27 of 27 www.diodes.com November 2022 © Diodes Incorporated AP62500 IMPORTANT NOTICE 1. DIODES INCORPORATED (Diodes) AND ITS SUBSIDIARIES MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICUL AR PURPOSE OR NON -INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes ’ products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. This document is intended for skilled and technically trained engineering customers and users who d esign with Diodes’ products. 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