AP393 ANACHIP | Alldatasheet
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Low Power Low Offset Voltage Dual Comparators This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. Rev. 1.0 Sep 7, 2004 Features - Wide supply Voltage range: 2.0V to 36V Single or dual supplies: ±1.0V to ±18V - Very low supply current drain (0.4 mA) – independent of supply voltage - Low input biasing current: 25 nA - Low input offset current: ±5 nA - Maximum offset voltage: ±3 mV - Input common-mode voltage range includes ground - Differential input voltage range equal to the power supply voltage - Low output saturation voltage: 250 mV at 4 mA - Output voltage compatible with TTL, DTL, ECL, MOS and CMOS logic systems - 8-pin PDIP and SOP Pb-Free packages Advantages - High precision comparators - Reduced VOS drift over temperature - Eliminates need for dual supplies - Allows sensing near ground - Compatible with all forms of logic - Power drain suitable for battery operation Pin Assignment General Description The AP393 consists of two independent precision voltage comparators with an offset voltage specification as low as 2.0 mV max for two comparators which were designed specifically to operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. These comparators also have a unique characteristic in that the input common-mode voltage range includes ground, even though operated from a single power supply voltage. Application areas include limit comparators, simple analog to digital converters; pulse, squarewave and time delay generators; wide range VCO; MOS clock timers; multivibrators and high voltage digital logic gates. The AP393 is designed to directly interface with TTL and CMOS. When operated from both plus and minus power supplies, the AP393 will directly interface with MOS logic where their low power drain is a distinct advantage over standard comparators. SOP-8L/PDIP-8L (Top View) INVERTING INPUT 1 GND AP393NON-INVERTING INPUT 1 OUTPUT 2 OUTPUT 1 V+ INVERTING INPUT 2 NON-INVERTING INPUT 2 Pin Descriptions Pin Name Pin No. Description OUTPUT 1 1 Channel 1 Output INVERTING INPUT 1 2 Channel 1 Negative Input NON-INVERT ING INPUT 1 3 Channel 1 Positive Input GND 4 Ground Pin Name Pin No. Description NON-INVERT ING INPUT 2 5 Channel 2 Positive Input INVERTING INPUT 2 6 Channel 2 Negative Input OUTPUT 2 7 Channel 2 Output V+ 8 Vcc
Low Power Low Offset Voltage Dual Comparators This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. Rev. 1.0 Sep 7, 2004 Ordering Information AP393 X X Package Packing N: PDIP-8L S: SOP-8L Blank: Tube A : Taping Block Diagram INVERTING INPUT 1 GND NON-INVERTING INPUT 1 OUTPUT 2 OUTPUT 1 INVERTING INPUT 2 NON-INVERTING INPUT 2 4 5 AB +-+ - V + 100µA3.5µA100µA3.5µA +INPUT -INPUT OUTPUTQ1 Q2 Q3 Q7Q8
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Absolute Maximum Ratings (Note 10) Symbol Parameter Rating Unit VCC Supply Voltage 36 V VIN Differential Input Voltage (Note 8) 36 V VIN Input Voltage -0.3 to +36 V ICC Input Current (V IN-0.3V) (Note 3) 50 mA Molded DIP 780 Metal Can 660 PD Power Dissipation (Note 1) Small Outline Package 510 mW Output Short-Circuit to Ground (Note 2) Continuous TOP Operating Temperature Range 0 to +70 oC TST Storage Temperature Range -65 to +150 oC TLead Lead Temperature Range (Soldering, 10 sec) +260 oC PDIP Soldering (10 sec) +260 Vapor Phase (60 sec) +215 Soldering Information SOP Infrared (15 sec) +220 oC ESD rating (1.5k Ω in with 100pF) 1300 V Electrical Characteristics (VCC=5V, TA=25oC, unless otherwise stated) Symbol Parameter Conditions Min. Typ. Max. Unit VOFFSET Input Offset Voltage (Note 9) - 1.0 5.0 mV IBIAS Input Bias Current IIN(+) or I IN(-) with Output In Linear Range, VCM=0V (Note 5) - 25 250 nA IOFFSET Input Offset Current I IN(+) - IIN(-) VCM=0V - 5.0 50 nA Input Common Mode Voltage Range V + =30V (Note 6) 0 - V + -1.5 V V+ =5V - 0.4 1 ICC Supply Current R L=∞ V+ =36V - 1 2.5 mA Voltage Gain RL > 15kΩ, V+ =15V VO=1V to 11V 50 200 - V/mV Large Signal Response Time VIN=TTL Logic Swing, VREF=1.4V, VRL=5V, RL=5.1kΩ - 300 - ns Response Time V RL=5V, RL=5.1kΩ (Note 7) - 1.3 - µs IO(Sink) Output Sink Current V IN(-)=1V, VIN(+)=0, VO <1.5V 6.0 16 - mA VSAT Saturation Voltage VIN(-)=1V, VIN(+)=0, ISINK < 4mA - 250 400 mV IO(Leak) Output Leakage Current V IN(-)=0, VIN(+)=1V, VO=5V - 0.1 - nA Electrical Characteristics (VCC=5V) (Note 4) Symbol Parameter Conditions Min. Typ. Max. Unit VOFFSET Input Offset Voltage (Note 9) - - 9 mV IOFFSET Input Offset Current I IN(+) -IIN(-), VCM=0V - - 150 nA IBIAS Input Bias Current IIN(+) or I IN(-) with Output In Linear Range, VCM=0V (Note 5) - - 400 nA Input Common Mode Voltage Range V + =30V (Note 6) 0 - V + -2.0 V VSAT Saturation Voltage VIN(-)=1V, VIN(+)=0, ISINK < 4mA - - 700 mV IO(Leak) Output Leakage Current V IN(-)=0, VIN(+)=1V, VO=30V - - 1.0 µA Differential Input Voltage Keep All VIN’s > 0V (or V-, if Used), (Note 8) - - 36 V
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Note 1: For operating at high temperatures, the AP393 must be derated based on a 125°C maximum junction temperature and a thermal resistance of 170°C/W which applies for the device soldered in a printed circuit board, operating in a still air ambien t. The AP393 must be derated based on a 150°C maximum junction temperature. The low bias dissipation and the “ON-OFF” characteristic of the outputs keeps the chip dissipation very small (P D <100 mW), provided the output transistors are allowed to saturate. Note 2: Short circuits from the output to V can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output current is approximately 20 mA independent of the magnitude of V Note 3: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-ba se junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which is negativ e, again returns to a value greater than -0.3V. Note 4: The AP393 temperature specifications are limited to 0°C < TA < +70°C. Note 5: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independe nt of the state of the output so no loading change exists on the reference or input lines. Note 6: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode voltage range is V -1.5V at 25°C, but either or both inputs can go to 36V without damage, independent of the magnitude of V Note 7: The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 300 ns can be obtained, see typical performance characteristics section. Note 8: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than -0.3V (or 0.3V below the magnitude of the negative power supply, if used). Note 9: At output switch point, V O ~ 1.4V, RS=0Ω with V from 5V to 30V; and over the full input common-mode range (0V to V -1.5V), at 25°C. Note 10: Refer to RETS193AX for AP393 military specifications. Typical Circuit (VCC =5.0VDC) VO 3.0K +VIN +VREF Basic Comparator AP393 Driving CMOS +5.0VDC 100K AP393 1/4 MM54CXX Driving TTL AP393 1/4 DM54XX +5VDC 10K VO 100K 100K 100K 100K 75 pF 4.3K Squarewave Oscillator 1:100kHz 1/2 AP393
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Typical Circuit (Continued) (VCC =5.0VDC) Pulse Generator VO 100K 80 pF 15K +15VDC 1N914 1N914 60µs6µs -V+ 0tOt1 t2 *For large ratios of R1/R2, D1 can be omitted 1/2 AP393 Crystal Controlled Oscillator VO 200K 0.1µF 2.0K 100K200K CRYSTAL f=100KHz 1/2 AP393 +VC FREQUENCY CONTROL VOLTAGE INPUT 0.1µF 20K 20K 50K V+/2 OUTPUT2 OUTPUT1 500pF 0.01µF 3.0K 5.1K 100K 3.0K Two-Decade High Frequency VCO V+/2 1/2 AP393 1/2 AP393 1/2 AP393 100K VO 3.0K +VIN +VREF Basic Comparator V*=+30VDC +250mVDC < VC < +50VDC 700Hz < fO < 100KHz 1/2 AP393 Non-Inverting Comparator with Hysteresis VO +VIN +VREF 10M 10K 1/2 AP393
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Typical Circuit (Continued) (VCC =5.0VDC) Inverting Comparator with Hysteresis 3K+VIN VO 1/2 AP393 VO 6.2K Output Strobing STROBE INPUT* * OR LOGIC GATE WITHOUT PULL-UP RESISTOR 1/2 AP393 AND Gate f A B C 100K 100K 100K 39K +0.375V "0" "1" 1/2 AP393 Or Gate A B C 100K 100K 100K 200K +0.075V "0" "1" f1/2 AP393 Large Fan-in AND Gate A + B C 100K 10K "0" "1" D ALL DIODES 1N914 100K VOUT1/2 AP393 Limit Comparator -2RS 2RS RS 10K V+ (12VDC) LAMP
12 ESB
+VIN +VREF LOW +VREF HI 2N2222 1/2 AP393 1/2 AP393
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Typical Circuit (Continued) (VCC =5.0VDC) 5.1K Comparing Input Voltages of Opposite Polarity 2N2222100K 100K +VIN1 -VIN2 1/2 AP393 ORing the Outputs 3.0K VO 1/2 AP393 1/2 AP393 Zero Crossing Detector (Single Power Supply) 5.1K VO 100K 100K 5.1K5.1K 1N914 VIN 10K 20M 1/2 AP393 One-Shot Multivibrator 10K VO 1N914 1M 1N914 100pF 0.001µF PW t0 t1 1ms 1/2 AP393 Bi-Stable Multivibrator 15K VO 100K S 100K 100K 51K R +15V S R 1/2 AP393
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Typical Circuit (Continued) (VCC =5.0VDC) One-Shot Multivibrator with Input Lock Out VO100pF 100K t0 t1 100K 1M +VIN 240K 62K 10M 15K560K10M 40µs 1µs +4V 1/2 AP393 1/2 AP393 Time Delay Generator 3.0K VO3 10M 3.0K VO2 3.0K VO1 t0 t1 t2 t3 t4 t VC1 51K 51K 51K 10K 10K 10K 200K15K10K VC1 0.001µF 10M 10M t0 t4 +VIN 10K INPUT GATING SIGNAL t0 t1 t0 t2 t0 t3 1/2 AP393 1/2 AP393 1/2 AP393 1/2 AP393
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Split-Supply Applications (V+=+15VDC and V- =-15 VDC) 2.4K2.4K φA φB 2K8.2K 3.9K2K 10K51K51K 5.1K 50pF 6.8K MOS Clock Driver 1/2 AP393 1/2 AP393 1/2 AP393 1/2 AP393 Zero Crossing Detector VIN 5.1K 1/2 AP393 VO VIN V 5.1K 1/2 AP393 VO -5 VDC Comparator With a Negative Reference
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Typical Characteristics Supply Current Input Current Output Saturation Voltage Response Time for Various Input Overdrives—Negative Transition Response Time for Various Input Overdrives—Positive Transition
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Application Information The AP393 is high gain, wide bandwidth devices which, like most comparators, can easily oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only during the output voltage transition intervals as the comparator change states. Power supply bypassing is not required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling. Reducing the input resistors to < 10k Ω reduces the feedback signal levels and finally, adding even a small amount (1.0 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause input-output oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required. All input pins of any unused comparators should be tied to the negative supply. The bias network of the AP393 establishes a drain current which is independent of the magnitude of the power supply voltage over the range of from 2.0 V DC to 30 V DC. It is usually unnecessary to use a bypass capacitor across the power supply line. The differential input voltage may be larger than V+ without damaging the device (Note 8). Protection should be provided to prevent the input voltages from going negative more than -0.3 V DC (at 25°C). An input clamp diode can be used as shown in the applications section. The output of the AP393 is the uncommitted collector of a grounded-emitter NPN output transistor. Many collectors can be tied together to provide an output OR’ing function. An output pull-up resistor can be connected to any available power supply voltage within the permitted supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage which is applied to the V + terminal of the AP393 package. The output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of current which the output device can sink is limited by the drive available (which is independent of V +) and the β of this device. When the maximum current limit is reached (approximately 16mA), the output transistor will come out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the approximately 60 Ω r SAT of the output transistor. The low offset voltage of the output transistor (1.0 mV) allows the output to clamp essentially to ground level for small load currents. Marking Information (Top View) SOP-8L/PDIP-8L AP393 YY WW X Logo Part No. ID code: internal Year: "01" =2001 "02" =2002 Xth week: 01~52
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Package Information (1) PDIP-8L (Plastic Dual-in-line Package ) D 7 (4X) AL A2A1 B2B1 B eS 15 (4X) E C eB E-PIN O0.118 inch PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch
Low Power Low Offset Voltage Dual Comparators Anachip Corp. Package Information (Continued) (2) SOP- 8L(JEDEC Small Outline Package) VIEW "A" L C VIEW "A" H E A A2A1Be D 7 (4X) 0.015x45 7 (4X) y A1 0.10 - 0.25 0.040 - 0.100 θ 0O - 8 O 0 O - 8 O