AP2011

AP2011 ANACHIP | Alldatasheet

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Synchronous PWM with VFC Controller Anachip Corp „ Features - Single 10V to 40V Supply Application - 1.25V + 2.0% Voltage Reference - Virtual Frequency ControlTM. - Fast Transient Response. - Synchronous Operation for High Efficiency - Current Limit Function. - Small Size with Minimum External Components - Soft Start and Shutdown Functions - Industrial Temperature Range - Under Voltage Lockout Function - SOP-14L Pb-Free Package „ Applications - Microprocessor Core Supply - Low Cost Synchronous Applications - Voltage Regulator Modules (VRM) - Networking Power Supplies - Sequenced Power Supplies - Telecommunication Power Supplies. „ Pin Assignments SOP-14L (Top View) PVCC OCSET PHASE PDRV PGND CAP FB AP2011 7 8 VCC PGATE VIN NGATE VREF SGND SS/SHDN „ Ordering Information AP2011 X X Package Packing S: SOP-14L Blank : Tube A : Taping „ General Description The AP2011 is a low-cost, full featured, synchronous voltage-mode controller designed for use in single ended power supply applications where efficiency is of primary concern. Synchronous operation allows for the elimination of heat sinks in many applications. The AP2011 is ideal for implementing DC/DC converters needed to power advanced microprocessors in low cost systems or in distributed power applications where efficiency is important. Internal level-shift, high-side drive circuitry, and preset shoot-thru control, allows the use of inexpensive 1P+1N-channel power switches. AP2011’s features include temperature ompensated voltage reference, Virtual Frequency ControlTM method to reduce external component count, an internal virtual frequency 200KHz oscillator, under-voltage lockout protection, soft-start, shutdown function and current sense comparator circuitry. Virtual Frequency Control is a trademark of PWRTEK, LLC. „ Pin Descriptions Pin Name Pin No. Description PGATE 1 Level shift-gate driver VCC 2 Internal regulator voltage PVCC 3 Power VCC PDRV 4 PMOS Gat driver PGND 5 Power Ground NGATE 6 Low side driver output (N MOSFET) VIN 7 Chip supply voltage CAP 8 Charge pump pin SS/ SHDN 9 Soft start, a capacitor to ground sets the slow start time/set low for shutdown function. FB 10 Feedback input OCSET 11 Sets the converter over-current trip point SGND 12 Signal Ground PHASE 13 Input from the phase node between the MOSFETs VREF 14 Reference voltage

Synchronous PWM Controller Anachip Corp „ Block Diagram CROSS CURRENT CONTROL DRVN VIRTUAL FREQ OSCILLATOR 200kHz DRVPR Q S Q S QB R VOLTAGE REFERENCE VCC 1.25V UNDER VOLTAGE ERROR COMP 0.3V VCC 12ua 2ua 0.2V 0.9V FB GND OCSET PHASE 70uA PVCC PDRV NGATE AP2011 FUNCTIONAL BLOCK DIAGRAM Virtual Frequency Control - Patent Number 6,456,050. INTERNAL REGULATOR 8V PGATE BIAS VIN CAP PGATE SS/SHDN VREF PGND „ Absolute Maximum Ratings Symbol Parameter Range. Unit VIN VCC to GND 0 to 42 V VPHASE PHASE to GND 0 to 42 V ΘJC Thermal Resistance Junction to Case 60 oC/W ΘJA Thermal Resistance Junction to Ambient 150 oC/W TOP Operating Temperature Range -40 to +85 oC TST Storage Temperature Range -65 to +150 oC TLEAD Lead Temperature (Soldering) 10 Sec. 300 oC

Synchronous PWM Controller Anachip Corp „ Electrical Characteristics Unless specified: VIN=20V; GND = 0V;VO = 5V; TJ = 25 o C Symbol Parameter Conditions Min. Typ. Max. Unit Power Supply VIN Supply Voltage (Recommended) 10 - 40 V IIN Supply Current - 8 10 mA ∆VLoad Load Regulation 0A < I Load < 3A - 50 70 mV ∆VLINE Line Regulation VIN= 10V to 40V ILoad =1A - 110 150 mV VCC Internal Regulator Voltage V IN =10V to 40V 8 8.5 9 V VIN -VCC V CC Dropout Voltage - 1.5 3.0 V VIN -PGATE P-Gate to Source Voltage (Off) VIN =10V Error Comparator AOL Gain (A OL) - 60 - dB IB Input Bias - 0.2 1 uA Oscillator DCMAX Oscillator Max Duty Cycle 80 85 - % Protection TDEAD Dead Time 100 150 250 nS IOCSET Over Current Set Isink VIN –1.5V < VOCSET < VIN - 70 - uA Reference Reference Voltage 1.225 1.25 1.275 V VREF Accuracy 0oC to 70oC -2 - + 2 % Soft Start ISSC Charge Current V SS = 1.5V 8.0 10 12 uA ISSD Discharge Current V SS = 1.5V 1.3 2 2.7 uA Under voltage lockout (UVLO) VUT Upper Threshold Voltage (V CC) - 6.8 - V VLWT Lower Threshold Voltage (V CC) - 6.5 - V VHT Hysteresis (V CC) TA = 25ºC - 300 - mV Note 1. Specification refers to Typical Application Circuit. Note 2. This device is ESD sensitive. Use of standard ESD handling precautions is required. Note 3. Abnormal condition; Ex: over-current, output over-voltage, under-voltage lockout, soft-start disappear. Note 4. VCC pin should not be used to externally source current. It is not short protected.

Synchronous PWM Controller Anachip Corp „ Typical Application Circuit VIN OCSET VCC PVCC CAP PGND FB NGATE PHASE PDRV PGATE SS/SHDN Vout=5V Lout 22u Cin 470u (50V) VIN=10V~28V(10V~40V) 6.8K SGND VREF 100n 1u(50V) 300n AF9410 (AF4410) (9985) AF9435 (AF4835) (9563) Optional D2C4 0.1u 10n (50V) 47n Cout 680u10n 47n(50V) Optional 6.8 ohm Cboost 0.1u (50V) VOUT= VFB ×(1 + R1 ) VFB = 1.25V R2 = 820 ~ 5.1K „ Typical Performance Characteristics PMOS: AF4835; NMOS: AF4410 Efficiency (Vout=5V)

012345 Iout (A)

Efficiency (%) Vin=12V Vin=30V Vin=20V PMOS: AP9563; NMOS: AP9985 Efficiency (Vout=5V) 012345 Iout (A) Efficiency (%) Vin=40V

Synchronous PWM Controller Anachip Corp „ Typical Performance Characteristics Load Regulation (Vin=12V; Vout=5V) 0.2 0.4 0.6 0.8 1.2 012345 Iout (A) Load Regulation (%) Line Regulation (Vout=5V) 0.2 0.4 0.6 0.8 1.2 1.4 0 1 02 03 04 0 Vin (V) Line Regulation (%) Vin v.s. Icc (No external component) 8.23 8.24 8.25 8.26 8.27 8.28 8.29 8.3 8.31 10 15 20 25 30 35 40 Vin (V) Icc (mA) Vin v.s. Icc (Operation current) 10 15 20 25 30 35 40 Vin (V) Icc (mA) Internal Regulator Voltage (Vin=12V; Vout=5V) 8.1 8.15 8.2 8.25 8.3 8.35 8.4 8.45 8.5 8.55 -25 0 25 50 75 100 Junction Temperature ( oC) Vcc (V) R4 v.s. Current limit (Vin=12V; Vout=5V) 4.5 5.5 6.5 7.5 8.5 23456789 R4 (K) Current limit (A)

Synchronous PWM Controller Anachip Corp „ Virtual Frequency Control Virtual Frequency Control  combines the advantages of constant frequency and constant off-time control in a single mode of operation. This allows fix frequency, precision switching voltage regulator control with fast transient response and the smallest solution size. Switch duty cycle can be adjusted from 0% to 100% on a pulse by pulse basis when responding to transient conditions. Both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. Figure 1 depicts a simplified operation of the Virtual Frequency Control technique: The VFC oscillator generates a pulse of a known duration (VFC_Pulse). The regulator loop responds by returning a complementary feedback pulse (FB_Pulse). The FB_Pulse duration is a result of external conditions such as inductor size, the voltage across the inductor and the duration of the VFC_Pulse. A VFC control loop is then formed whereby the duration of the VFC_Pulse is modified as a result of the FB_Pulse duration. The VFC loop arrives at a state of equilibrium, where the operating frequency remains inherently constant. GATE CONTROL LOGIC VIRTUAL FREQ OSCILLATOR FB Pulse VFC Pulse Vref ERROR COMP VIN Lout Cout Vout Rfb1 Rfb2 Figure 1: Virtual Frequency Control Loop- Synchronous single supply application. VOUT VIN DON < 0.1, VOUT VIN×10000 / 5.9 - 0.01VIN Virtual frequency control is a technique that provides stable, constant frequency of operation for pulse controlled architectures such as constant off-time/on-time. This is all done internal to the IC with minimal number of components and without the need for connections to external terminals such as input and/or output. No external compensation is required, thus providing a low cost, high performance fix frequency solution for switching voltage regulators. Virtual Frequency Control is a trademark of PWRTEK, LLC.

Synchronous PWM with VFC Controller Anachip Corp „ Function Description Synchronous Buck Converter Primary VCORE power is provided by a synchronous, voltage-mode pulse width modulated (PWM) controller. This section has all the features required to build a high efficiency synchronous buck converter, including soft-start, shutdown, and cycle-by-cycle current limit. Referring to the functional block diagram FIG 1, the output voltage of the synchronous converter is set and controlled by the output of the error comparator. The external resistive divider reference voltage, is derived from an internal trimmed-bandgap voltage reference. The inverting input of the error comparator receives its voltage from the FB pin. The internal oscillator uses an on-chip capacitor and trimmed precision current sources to set the virtual oscillation frequency to 200Khz. The virtual frequency oscillator sets the PWM latch. This pulls DRVN low, turning off the low-side N_MOSFET and DRVP is pulled low, turning on the high-side P-MOSFET (once the cross-current control allows it). The triangular voltage ramp at the FB pin is then compared against the reference voltage at the inverting input of the error comparator. When the FB voltage increases above the reference voltage, the comparator output goes high. This pulls DRVP high, turning off the high-side P-MOSFET, and DRVN is pulled high, turning on the low-side N-MOSFET (once the cross-current control allows it). The Virtual Frequency Oscillator then generates a programmed off time to allow the FB voltage to return to the valley voltage of the triangular ramp. At the end of the off time the PWM latch is set and the cycle repeats again. Under Voltage Lockout The under voltage lockout circuit of the AP2011 assures that the high-side P-MOSFET driver outputs remain in the off state whenever the supply voltage drops below set parameters. Lockout occurs if V CC falls below 6.5V. Normal operation resumes once V CC rises above 6.8V. RDS(ON) Current Limiting The current limit threshold is set by connecting an external resistor from the VCC supply to OCSET. The voltage drop across this resistor is due to the 70uA internal sink sets the voltage at the pin. This voltage is compared to the voltage at the PHASE node. This comparison is made only when the high-side drive is high to avoid false current limit triggering due to uncontributing measurements from the MOSFETs off-voltage. When the voltage at PHASE is less than the voltage at OCSET, an overcurrent condition occurs and the soft start cycle is initiated. The synchronous switch turns on and SS/ SHDN starts to sink 2uA. When SS/ SHDN reaches 0.2V, it then starts to source 10uA and a new cycle begins. When the soft start voltage is below 0.9V the cycle is controlled with pulse by pulse current limiting. Soft Start Initially, SS/SHDN sources 10uA of current to charge an external capacitor. The inverting input of the error comparator is clamped to a voltage proportional to the voltage on SS/ SHDN . This limits the on-time of the high-side P-MOSFET, thus leading to a controlled ramp-up of the output voltages.

Synchronous PWM Controller Anachip Corp „ Function Description Hiccup Mode During power up, the SS/ SHDN pin is internally pulled low until V CC reaches the under-voltage lockout level of 6.8V. Once V CC has reached 6.8V, the SS/ SHDN pin is released and begins to source 10uA of current to the external soft-start capacitor. As the soft-start voltage rises, the inverting input of the error comparator is clamped to this voltage. When the error signal reaches the level of the internal 1.25V reference, the output voltage is to have reached its programmed voltage. If an over-current condition has not occurred the soft-start voltage will continue to rise and level off at about 2.4V. An over-current condition occurs when the high-side drive is turned on, but the PHASE node does not reach the voltage level set at the OCSET pin. Once an over-current occurs, the high-side drive is turned off and the low-side drive turns on and the SS/ SHDN pin begins to sink 2uA. The soft-start voltage will begin to decrease as the 2uA of current discharge the external capacitor. When the soft-start voltage reaches 0.2V, the SS/ SHDN pin will begin to source 10uA and begin to charge the external capacitor causing the soft-start voltage to rise again. If the over-current condition is no longer present, normal operation will continue. If the over-current condition is still present, the SS/ SHDN pin will again begin to sink 2uA. This cycle will continue indefinitely until the over-current condition is removed. In order to prevent substrate glitching, a small-signal diode should be placed in close proximity to the chip with cathode connected to PHASE and anode connected to GND. „ Marking Information (Top View) SOP-14L AP2011 YY WW X Logo Part No. ID code: internal Year: "01" =2001 "02" =2002 Xth week: 01~52

Synchronous PWM Controller Anachip Corp „ Package Information Package Type: SOP-14L 0.015x45o 7o(4x) C Detail A D 7o (4x) y e b A2A1 A Pin 1 indent E L 0.010 Detail A Θ Gage Plane A1 0.10 - 0.250 0.0040 - 0.0100 θ 0O - 8O 0 O - 8O