AP0201AT ONSEMI | Alldatasheet

Document overview

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Technical content

Features

  • Up to 2.0 Mp (1920 x 1080) ON Semiconductor Sensor Support
  • 30 fps at 1080 p, 45 fps at 1.2 Mp, 60 fps at 720p (Optimized for Operation with HDR Sensors)
  • Color and Gamma Correction www.onsemi.com VFBGA100, 7x7 CASE 138AH MARKING DIAGRAM XXXXXXXXXXX = Laser Marking See detailed ordering and shipping information on page 2 of this data sheet.

ORDERING INFORMATION

  • Auto Exposure, Auto White Balance, 50/60 Hz Auto Flicker Detection and Avoidance
  • Adaptive Local Tone Mapping (ALTM)
  • Configurable through Low−cost SPI Flash and EEPROM Devices
  • Up to 7 GPIO
  • Fail−Safe IO
  • Multi−Camera Synchronization Support
  • MJPEG Encoding (8−bit)
  • H.264 Encoding (8 and 10 bit intra−frame)
  • Integrated Full−duplex Ethernet MAC
  • Precise Timing Protocol (PTP): IEEE 802.1AS and 1588−2008
  • IEEE 802.1Qav (Annex L Configurable Video Bandwidth)
  • A VB (IEEE1722) and RTP Video Transport Protocol

Figure 2. Example AP0201AT Connectivity NOTE: The AP0201AT example above shows the PHY which is used between the Ethernet switch and the AP0201AT.

Figure 3 shows typical AP0201AT device connections. using capacitors as close as possible to the package. provides the signal descriptions for the AP0201AT.

1.2 V (Regulator OP)

NOTES: 1. This typical configuration shows only one scenario out of multiple possible variations for this device.

  1. ON Semiconductor recommends a 1.5 k /C0087 resistor value for the two−wire serial interface RPULL−UP.
  2. RESET_BAR has an internal pull −up resistor and can be left floating if not used.
  3. The decoupling capacitors for the regulator input and output should have a value of 1.0 /C0109F. The capacitors should be ceramic

and need to have X5R or X7R dielectric.

  1. TRST and RESERVED[0] connect to GND for normal operation, RESERVED[3:2] are floating and RESERVED[1] is connected

to VDDIO_H for normal operation.

  1. ON Semiconductor recommends that 0.1 /C0109F and 1 /C0109F decoupling capacitors for each power supply are mounted as close as

possible to the pin. Actual values and numbers may vary depending on layout and design consideration. Figure 3. Typical Ethernet Configuration

these pins is allowed as well. applications that require this. Figure 4. Using a Crystal Instead of External Oscillator Table 3. PIN DESCRIPTIONS otherwise this signal must be left unconnected. has an internal pull−up resistor. FRAME_SYNC Input Pass through to TRIGGER_OUT. This signal should be connected to GND if not used. This pin has two modes of use for frame sync. One the pass through to TRIGGER_OUT. The other goes to the frame_sync_monitor block. STANDBY Input Standby mode control, active HIGH. EXT_REG Input Select external regulator if tied high. ENLDO Input Regulator enable (VDD_REG domain). SPI_SCLK Output Clock output for interfacing to an external SPI flash or EEPROM memory. 1: Auto−configure. This signal has an internal pull−up resistor. SPI_SDO Output Data out to SPI flash or EEPROM memory.

Table 3. PIN DESCRIPTIONS (continued) SPI_CS_BAR Output Chip select out to SPI flash or EEPROM memory. EXTCLK_OUT Output Clock to external sensor. RESET_BAR_OUT Output Reset signal to external sensor. M_SCLK Output Two−wire serial interface clock (Master). M_SDATA I/O Two−wire serial interface data (Master). FV_IN Input Sensor frame valid input. LV_IN Input Sensor line valid input. PIXCLK_IN Input Sensor pixel clock input. DIN[11:0] Input Sensor pixel data input DIN[11:0]. HiSPiCN Input Differential HiSPi clock (negative). HiSPiCP Input Differential HiSPi clock (positive). HiSPi0N Input Differential HiSPi data, lane 0 (negative). HiSPi0P Input Differential HiSPi data, lane 0 (positive). HiSPi1N Input Differential HiSPi data, lane 1 (negative). HiSPi1P Input Differential HiSPi data, lane 1 (positive). TRIGGER_OUT Output Trigger signal for external sensor. PHY_RESET_BAR Output PHY_RESET_BAR Output. TX_CLK Output Host frame valid output. RX_CLK Output Host line valid output. GND for 100 Mbit applications. TXD[3:0] Output Ethernet port. TX_ERR Output Ethernet port. RXD[3:0] Input Ethernet port. MDC Output Management Data clock for controlling the PHY. MDIO I/O Management Data Input/Output for controlling the PHY. GPIO_[6:1] I/O General purpose digital I/O. TRST Input Must be tied to GND in normal operation. Reserved[0] Input Must be tied to GND in normal operation. VDDIO_S Supply Sensor I/O power supply. VDDIO_H Supply Host I/O power supply. VDDIO_OTPM Supply OTPM power supply. VDD_PHY Supply PHY IO voltage for HiSPi.

VDD_REG Supply Input to on−chip 1.8 V to 1.2 V regulator. LDO_OP Output Output from on chip 1.8 V to 1.2 V regulator. FB_SENSE Input On−chip regulator sense signal. Table 4. PACKAGE PINOUT

  1. Pin K1 and J2 should be left floating.
  2. Pin C2 needs to be tied to V DDIO_H in all applications.

Table 5. KEY SIGNALS WHEN USING THE REGULATOR

power−on reset feature that initiates a reset upon power up. Figure 5. Power−Up and Power−Down Sequence Table 6. POWER−UP AND POWER−DOWN SIGNAL TIMING

  1. When using XTAL the settling time should be taken into account.
  • A hard reset is issued by toggling the RESET_BAR signal.
  • A soft reset is issued by writing commands through the Ethernet interface.
  • An internal power−on reset. Table 7 shows the output states when the part is in various states.

Table 7. OUTPUT STATES

Table 7. OUTPUT STATES (continued)

Driven if used Driven if used Driven if used Driven if used Input/Output. RESET_BAR signal is asserted LOW, as shown in Figure 6. Refer to Table 7 for details. Figure 6. Hard Reset Operation Table 8. HARD RESET

by writing to a register through the Ethernet interface. to LOW state to restart the device.

  1. Assert STANDBY signal HIGH.
  2. De−assert STANDBY signal LOW.

Figure 7. Hard Standby Operation Table 9. HARD STANDBY SIGNAL TIMING Config, Auto Config, and Host Config.

  • If a device is detected, the firmware switches to the Flash−Config mode.
  • If no device is detected, the firmware then samples the SPI_SDI pin state to determine the next mode: ♦ If SPI_SDI is low, then it enters the Host−Config mode. ♦ If SPI_SDI is high, then it enters the Auto−Config mode. In the Flash−Config mode, the firmware interrogates the device to determine if it contains valid configuration records:
  • If no records are detected, then the firmware enters the Host−Config mode.
  • After power is applied and the device is out of reset (either the power on reset, hard or soft reset), it will enter a boot sequence to configure its operating mode. There are essentially three configuration modes: Flash/EEPROM Config, Auto Config, and Host Config. In the Host −Config mode, the firmware performs no configuration, and remains idle waiting for configuration and commands from the host. The System Configuration phase is effectively complete and the AP0201AT will take no actions until the host issues commands.

www.onsemi.com IMAGE FLOW PROCESSOR Image and color processing in the AP0201AT is implemented as an image flow processor (IFP) coded in hardware logic. During normal operation, the embedded microcontroller will automatically adjust the operating parameters. For normal operation of the AP0201AT, streams of raw image data from the attached image sensor are fed into the color pipeline. The AP201AT also has the option to select a number of test patterns to be input instead of sensor data. Defect Correction Image stream processing commences with the defect correction function immediately after data decompanding. To obtain defect free images, the pixels marked defective during sensor readout and the pixels determined defective by the defect correction algorithms are replaced with values derived from the non−defective neighboring pixels. AdaCD (Adaptive Color Difference) The next step in the image stream processing is noise reduction. The AP0201AT uses a noise reduction filter called AdaCD which focuses on removing color noise while preserving edge details. Automotive applications require good performance in extremely low light, even at high temperature conditions. In these stringent conditions the image sensor is prone to higher noise levels, and so efficient noise reduction techniques are required to circumvent this sensor limitation and deliver a high quality image to the user. Black Level Substraction and Digital Gain After noise reduction, the pixel data goes through black level subtraction and multiplication by a programmable digital gain. Independent color channel digital gain can be adjusted with registers. Black level subtraction (to compensate for sensor data pedestal) is a single value applied to all color channels. If the black level subtraction produces a negative result for a particular pixel, the value of this pixel is set to 0. Positional Gain Adjustments (PGA) Lenses tend to produce images whose brightness is significantly attenuated near the edges. There are also other factors causing fixed pattern signal gradients in images captured by image sensors. The cumulative result of all these factors is known as image shading. The AP0201AT has an embedded shading correction module that can be programmed to counter the shading effects on each individual R, Gb, Gr, and B color signal. The Correction Function The correction functions can then be applied to each pixel value to equalize the response across the image as follows: Pcorrected(row, col) /C0043Psensor(row, col) /C0032f(row, col) (eq. 1) where P are the pixel values and f is the color dependent correction functions for each color channel. Adaptive Local Tone Mapping (ALTM) Real world scenes often have very high dynamic range (HDR) that far exceeds the electrical dynamic range of the imager. Dynamic range is defined as the luminance ratio between the brightest and the darkest object in a scene. In recent years many technologies have been developed to capture the full dynamic range of real world scenes. For example, the multiple exposure method is widely adopted for capturing high dynamic range images, which combines a series of low dynamic range images of the same scene taken under different exposure times into a single HDR image. Even though the new digital imaging technology enables the capture of the full dynamic range, low dynamic range display devices are the limiting factor. Today’s typical LCD monitor has contrast ratio around 1,000:1; this contrast ratio is not enough for an HDR image (the contrast ratio for an HDR image is around 250,000:1). Therefore, in order to reproduce HDR images on a low dynamic range display device, the captured high dynamic range must be compressed to the available range of the display device. This is commonly called tone mapping. Tone mapping methods can be classified into global tone mapping and local tone mapping. Global tone mapping methods apply the same mapping function to all pixels. While global tone mapping methods provide computationally simple and easy to use solutions, they often cause loss of contrast and detail. A local tone mapping is thus necessary in addition to global tone mapping for the reproduction of visually more appealing images that also reveal scene details that are important for automotive safety applications. Local tone mapping methods use a spatially variable mapping function determined by the neighborhood of a pixel, which allows it to increase the local contrast and the visibility of some details of the image. Local methods usually yield more pleasing results because they exploit the fact that human vision is more sensitive to local contrast. ON Semiconductor’s ALTM solution significantly improves the performance over global tone mapping. ALTM is directly applied to the Bayer domain to compress the dynamic range from 20 −bit to 12−bit. This allows the regular color pipeline to be used for HDR image rendering. Color Interpolation In the raw data stream fed by the external sensor to the IFP, each pixel is represented by a 20− or 12−bit integer number, which can be considered proportional to the pixel’s response to a one−color light stimulus, red, green, or blue, depending on the pixel’s position under the color filter array. Initial data processing steps, up to and including ALTM, preserve the one−color−per−pixel nature of the data stream, but after ALTM it must be converted to a three −colors−per−pixel stream appropriate for standard color processing. The conversion is done by an edge−sensitive color interpolation module. The module pads the incomplete color information available for each pixel with information extracted from an

can be set through register settings. adjusted through register settings. programmable through variables. the host to program the 33 knee point curve directly. in extreme low light conditions. difference between their luminance and the threshold. sensor and color pipeline to achieve the desired exposure. windows organized as a 5 x 5 grid. Figure 12. 5 x 5 Grid

www.onsemi.com AE Track Driver Other algorithm features include the rejection of fast fluctuations in illumination (time averaging), control of speed of response, and control of the sensitivity to small changes. While the default settings are adequate in most situations, the user can program target brightness, measurement window, and other parameters described above. The driver changes AE parameters (integration time, gains, and so on) to drive scene brightness to the programmable target. To avoid unwanted reaction of AE on small fluctuations of scene brightness or momentary scene changes, the AE track driver uses a temporal filter for luma and a threshold around the AE luma target. The driver changes AE parameters only if the filtered luma is larger than the AE target step and pushes the luma beyond the threshold. Auto White Balance The AP0201AT has a built−in AWB algorithm designed to compensate for the effects of changing spectra of the scene illumination on the quality of the color rendition. The algorithm consists of two major parts: a measurement engine performing statistical analysis of the image and a driver performing the selection of the optimal color correction matrix and IFP digital gain. While default settings of these algorithms are adequate in most situations, the user can reprogram base color correction matrices, place limits on color channel gains, and control the speed of both matrix and gain adjustments. The AP0201AT AWB displays the current AWB position in color temperature, the range of which is defined by programmable settings. The region of interest can be controlled through the combination of an inclusion window and an exclusion window. Exposure and White Balance Control The Sensor Manager firmware component is responsible for controlling the application of ’exposure’ and ’white balance’ within the system. This effectively means that all control of integration times and gains (whether for exposure or white balance) is delegated to the Sensor Manager. The Auto Exposure (AE) and Auto White Balance (AWB) algorithms use services provided by the Sensor Manager to apply exposure and/or white balance changes. Dual Band IRCF Manager firmware component is responsible for controlling the application of ’exposure’ and ’white balance’ within the system. This effectively means that all control of integration times and gains (whether for exposure or white balance) is delegated to the Sensor Manager. The Auto Exposure (AE) and Auto White Balance (AWB) algorithms use services provided by the Sensor Manager to apply exposure and/or white balance changes. Exposure and White Balance Modes The AP0201AT supports auto and manual exposure and white balance modes. In addition, it will operate within synchronized multi−camera systems. In this use case, one camera within the system will be the ’master’, and the others ’slaves’. The master is used to calculate the appropriate exposure and white balance. This is then applied to all slaves concurrently under host control. Auto Mode In Auto Exposure mode the AE algorithm is responsible for calculating the appropriate exposure to keep the desired scene brightness, and for applying the exposure to the underlying hardware. In Auto White Balance mode the AWB algorithm is responsible for calculating the color temperature of the scene and applying the appropriate red and blue gains to compensate. Triggered Auto Mode The Triggered Auto Exposure and Triggered Auto White Balance modes are intended for the multicamera use cases, where a host is controlling the exposure and white balance of a number of cameras. The idea is that one camera is in triggered−auto mode (the master), and the others in hostcontrolled mode (slaves). The master camera must calculate the exposure and gains, the host then copies this to the slaves, and all changes are then applied at the same time. Manual Mode Manual mode is intended to allow simple manual exposure and white balance control by the host. The host needs to set the CAM_AET_EXPOSURE_TIME_MS, CAM_AET_EXPOSURE_GAIN and CAM_AWB_COLOR_TEMPERA TURE controls, the camera will calculate the appropriate integration times and gains. Host Controlled The Host Controlled mode is intended to give the host full control over exposure and gains to allow host to control desired output. FLICKER AVOIDANCE Flicker occurs when the integration time is not an integer multiple of the period of the light intensity. The AP0201AT can be programmed to avoid flicker for 50 or 60 Hertz. For integration times below the light intensity period (10ms for 50Hz environment, 8.33 ms for a 60 Hz environment), flicker cannot be avoided. The AP0201AT supports an indoor AE mode, that will ensure flicker−free operation. FLICKER DETECTION The AP0201AT supports flicker detection, the algorithm is designed only to detect a 50Hz or 60 Hz flicker source. Output Formatting. The pixel output data in AP0201AT will be transmitted as an 8−bit word over the Ethernet interface.

www.onsemi.com Output Video Formats The AP0201AT conforms with the IEEE standard for both MJPEG and H.264 video outputs. For reference, the standard is “IEEE Standard for Layer 2 Transport Protocol for Time −Sensitive Applications in Bridged Local Area Networks” and can be obtained from IEEE. H.264 Format The AP0201AT is compliant with the ITU−T REC. H.264 standard published by the Telecommunication Standardization Sector of the International Telecommunication Union, which is equivalent to ISO/IEC 14496−10. The AP0201AT supports the standard H.264 for video compression which is equivalent to MPEG−4 Part 10, also known as MPEG−4 Advanced Video Coding (A VC). The AP0201A T utilizes an advanced High profiles compliant encoder, constrained to the All−Intra encoding schemes. It supports real time encoding of 4:2:0 video streams, up to Level 5.2, in 8 and 10 bit sample depths. The core only needs to be programmed once per video sequence. Once programmed, the AP0201AT can encode an arbitrary number of video frames, without the need of any further intervention from the host system. H.264 Features The AP0201AT H.264 encoding includes the following features:

  • High 10 intra profile encoding
  • 8− and 10−bit sample depth encoding
  • Level up to 5.2
  • ITU−T H.264 Annex B compliant NAL byte stream output
  • CQP − VBR encoding mode ♦ Rate−Distortion optimized output ♦ Up to 240MBits/s output (CA VLC)
  • CBR encoding mode ♦ HRD CPB compliant CBR NAL output ♦ Sub−frame operation with tunable number of macroblocks basis ♦ Further micro adjustment of quantization per macroblock maximizes the perceived video quality ♦ Both Rate−Distortion metrics and perceived video quality optimized ♦ On−the−fly rate changes are supported ♦ Up to 240 Mbits/s output (CA VLC)
  • Advanced Intra prediction ♦ All four Intra 16x16 prediction modes ♦ All four Intra Chroma prediction modes ♦ All nine Intra 4x4 prediction modes
  • Error resilience ♦ Multiple slices per frame encoding ♦ Deblocking filter in the decoder can be optionally constrained to operate within slice boundaries
  • Optional advanced thresholding of quantized transform coefficients ♦ Eliminates spares and insignificant transform coefficients ♦ Improves the compression efficiency ♦ Near−zero impact to the measured video quality ♦ Zero impact to the perceived, subjective, video quality
  • Run−time tunable operation enables decoder compatibility trade−offs ♦ Full control of allowed Intra prediction modes ♦ Single or multiple slices per frame encoding ♦ Option and tunable deblocking filter operation ♦ CA VLC coding MJPEG FORMAT JPEG Encoder The JPEG compression engine in the AP0201AT is a highly integrated, high−performance solution that provides for low power consumption and programmability of JPEG compression parameters for image quality control. The JPEG encoding block is designed for continuous image flow and is ideal for low power applications. After initial configuration for a target application, it can be controlled easily for instantaneous stop or restart. A flexible configuration and control interface allows for full programmability of various JPEG−specific parameters and tables. JPEG Encoding Highlights
  • Sequential DCT (baseline) ISO/IEC 10918−1 JPEG−compliant
  • YCbCr 4:2:0 format compression
  • JPEG capability at full resolution with JFIF− or RFC2435−compliant header
  • Programmable automatic control of bit rate Stream Breakdown An MJPEG video stream consists of the following sequence of data sections. Each JPEG frame must have the following characteristics:
  • Color Encoding is YcbCr
  • 8 bits per color component, (24 bits/pixel before subsampling)
  • 420 Subsampling
  • Baseline sequential DCT (SOF0) JPEG Header The MJPEG stream can be output with 4 different header settings. Three of them are similar to each other. The first is the standard JPEG header as defined in the original JPEG specification. The second is a JFIF header which is the standard header plus a JFIF segment. The third is a standard header minus the Huffman table. Since, for this design, the Huffman table is constant, some bandwidth can be saved by not including it.

www.onsemi.com The 4th header option is optimized for Ethernet and is referred to as RFC2435. JFIF , Standard and Standard minus Huffman Headers For these three header types, the header segments that will be included are listed below including examples. Note that data values in the examples are in hex. Comments are in decimal.

  • SOI, Start of Image. 2 bytes. ff d8
  • APP0, Application Segment 0. N bytes (only included in JFIF headers): Example JFIF marker: ff e0 00 10 4a 46 49 46 00 01 02 00 00 01 00 01 00 00
  • DHT, Define Huffman Tables, 420 bytes (Not included in standard header without Huffman table) Example: ff c4 01 a2 #DC Table 0 00 01 05 01 01 01 01 01 01 00 00 00 00 00 00 00 #12 codes 00 01 02 03 04 05 06 07 08 09 0a 0b #AC Table 0 00 02 01 03 03 02 04 03 05 05 04 04 00 00 01 7d #162 codes 01 02 03 00 04 11 05 12 21 31 41 06 13 51 61 07 22 71 14 32 81 91 a1 08 23 42 b1 c1 15 52 d1 f0 24 33 62 72 82 09 0a 16 17 18 19 1a 25 26 27 28 29 2a 34 35 36 37 38 39 3a 43 44 45 46 47 48 49 4a 53 54 55 56 57 58 59 5a 63 64 65 66 67 68 69 6a 73 74 75 76 77 78 79 7a 83 84 85 86 87 88 89 8a 92 93 94 95 96 97 98 99 9a a2 a3 a4 a5 a6 a7 a8 a9 aa b2 b3 b4 b5 b6 b7 b8 b9 ba c2 c3 c4 c5 c6 c7 c8 c9 ca d2 d3 d4 d5 d6 d7 d8 d9 da e1 e2 e3 e4 e5 e6 e7 e8 e9 ea f1 f2 f3 f4 f5 f6 f7 f8 f9 fa #DC Table 1 00 03 01 01 01 01 01 01 01 01 01 00 00 00 00 00 #12 codes 00 01 02 03 04 05 06 07 08 09 0a 0b #AC Table 1 00 02 01 02 04 04 03 04 07 05 04 04 00 01 02 77 #162 codes 00 01 02 03 11 04 05 21 31 06 12 41 51 07 61 71 13 22 32 81 08 14 42 91 a1 b1 c1 09 23 33 52 f0 15 62 72 d1 0a 16 24 34 e1 25 f1 17 18 19 1a 26 27 28 29 2a 35 36 37 38 39 3a 43 44 45 46 47 59 49 4a 53 54 55 56 57 58 59 5a 63 64 65 66 67 68 69 6a 73 74 75 76 77 78 79 7a 82 83 84 85 86 87 88 89 8a 92 93 94 95 96 97 98 99 9a a2 a3 a4 a5 a6 a7 a8 a9 aa b2 b3 b4 b5 b6 b7 b8 b9 ba c2 c3

www.onsemi.com #AC Table 1 c4 c5 c6 c7 c8 c9 ca d2 d3 d4 d5 d6 d7 d8 d9 da e2 e3 e4 e5 e6 e7 e8 e9 ea f2 f3 f4 d5 f6 f7 f8 f9 fa

  • DQT, Define Quantization Tables. 134 bytes. Example: ff db 00 84 #8−bit, Table 0 10 0b 0c 0e 0c 0a 10 0e 0d 0e 12 11 10 13 18 28 1a 18 16 16 18 31 23 25 1d 28 3a 33 3d 3c 39 33 38 37 40 48 5c 4e 40 44 57 45 37 38 50 6d 51 57 5f 62 67 68 67 3e 4d 71 79 70 64 78 5c 65 67 63 #8−bit, Table 1 11 12 12 18 15 18 2f 1a 1a 2f 63 42 38 42 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 The quantization table can be adjusted for each frame for more or less compression.
  • DRI, Define Restart Interval. 6 bytes. Example: ff db 00 04 00 78 The segment is optional. The host will determine whether to include Restart markers and at what interval.
  • SOF0, Start of Frame 0. 19 bytes. Example: ff c0 00 11 08 #Sample precision 04 38 #Number of rows = 1080 07 80 #Number of columns = 1920 03 #Number of components 01 21 00 #Component 1: HSF = 2, VSF = 1, Q Table = 0 02 11 01 #Component 2: HSF = 1, VSF = 1, Q Table = 1 03 11 01 #Component 3: HSF = 1, VSF = 1, Q Table = 1
  • SOS, Start of Scan. 14 bytes. Example: ff da 00 0c 03 #Number of components 01 00 #Component 1: DC table 0, AC table 0 02 11 #Component 2: DC table 1, AC table 1 03 11 #Component 3: DC table 1, AC table 1 00 #Start of spectral selection 3f #End of spectral selection 00 #Successive approximation high/low

www.onsemi.com Compressed Data With or Without Restart Markers This is compressed binary data of the frame which can be decoded to display the captured image. The JPEG compression engine can be configured to insert restart marker at programmable intervals. EOI This is the End of Image code. It is only 2 bytes long. ff d9 Huffman Table When standard JPEG headers without Huffman tables is selected, the Huffman table is not included in the data stream. However, the decoder will need to know what the table is to perform the decode. The required Huffman table is: /* Default DHT Segment */ MJPGHDTSEG_STORAGE BYTE MUPGDHTSeg[0x1A0] = { /*JPEG DHT Segment for YCrCb omitted from MJPG data*/ 0xFF 0xC4 0x01 0xA2 0x00 0x00 0x01 0x05 0x01 0x01 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x01 0x00 0x03 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x10 0x00 0x02 0x01 0x03 0x03 0x02 0x04 0x03 0x05 0x05 0x04 0x04 0x00 0x00 0x01 0x7D 0x01 0x02 0x03 0x00 0x04 0x11 0x05 0x12 0x21 0x31 0x41 0x06 0x13 0x51 0x61 0x07 0x22 0x71 0x14 0x32 0x81 0x91 0xA1 0x08 0x23 0x42 0xB1 0xC1 0x15 0x52 0xD1 0xF0 0x24 0x33 0x62 0x72 0x82 0x09 0x0A 0x16 0x17 0x18 0x19 0x1A 0x25 0x26 0x27 0x28 0x29 0x2A 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0x11 0x00 0x02 0x01 0x02 0x04 0x04 0x03 0x04 0x07 0x05 0x04 0x04 0x00 0x01 0x02 0x77 0x00 0x01 0x02 0x03 0x11 0x04 0x05 0x21 0x31 0x06 0x23 0x41 0x51 0x07 0x61 0x71 0x13 0x22 0x32 0x81 0x08 0x14 0x42 0x91 0xA1 0xB1 0xC1 0x09 0x23 0x33 0x52 0xF0 0x15 0x62 0x72 0xD1 0x0A 0x16 0x24 0x34 0xE1 0x25 0xF1 0x17 0x18 0x19 0x1A 0x25 0x27 0x28 0x29 0x2A 0x35 0x36 0x37 0x38 0x39 0x3A 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA

of each frame which contain information about that frame. was captured, e.g. mean values, intensity histograms, etc. address and port are set to 255.255.255.255 and 50010.

  1. Four byte of Timestamp to match with the frame.
  2. Four byte of line number. AP0201AT sends line

requirements. The maximum size supported in 2 GB. access to control and status registers within the AP0200AT. a master controls one or more slave devices.

  • a start or restart condition
  • a slave address/data direction byte
  • a 16−bit register address
  • an acknowledge or a no−acknowledge bit
  • data bytes
  • a stop condition The bus is idle when both S CLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. The S ADDR pin is used to select between two different addresses in case of conflict with another device. If SADDR is LOW, the slave address is 0x90; if S ADDR is HIGH, the slave address is 0xBA. See Table 10. The user can change the slave address by changing a register value.

Table 10. TWO−WIRE INTERFACE ID ADDRESS transition on SDATA while SCLK is HIGH. this is known as a “repeated start” or “restart” condition. low and must be stable while SCLK is HIGH. the two−wire serial interface specification. is LOW and must be stable while SCLK is HIGH. on SDATA while SCLK is HIGH.

www.onsemi.com ETHERNET INTERFACE Overview AP0201A T’s Ethernet mode has complete support for configuring the part and streaming video out. By default IPv4 and IPv6 are enabled. The default MAC address and IP address are in the table below. For a complete set of default settings and configurable variables refer to the AP0201AT Register Reference. AP0201AT supports time precision protocols to synchronize several cameras. Type Default Address MAC 2:00:00:00:00:01 IPv4 192.168.1.5 IPv6 fe80::ff:fe00:0 AP0201A T also supports a UDP−based protocol with ON Semiconductor host commands. Using this protocol all registers and variables are accessible. AP0201A T MAC supports MII, GMII and RMII protocols. Video can be streamed in MJPEG or H.264 format over RTP or A VB (IEEE 1722a) protocols. Registers and variables can be modified using HCI access commands over Ethernet or through the serial interface. For initial settings of these variables, firmware will check NVM before booting up. (Please refer to the network section of the HCI document for a discussion of all Ethernet firmware and hardware variables.)

  • Ethernet hardware ♦ 100 Mb and 1 Gb Ethernet speed ♦ Configurable MAC
  • Ipv4
  • DHCP for dynamic IP address configuration
  • Network QoS and communication integrity check using ON Semiconductor UDP based commands
  • Network status
  • Communication integrity check over ON Semiconductor−UDP
  • Support for patching firmware over Ethernet and serial interface
  • Support for dynamic variable updates
  • Monitoring AP0201AT registers
  • VLAN support: Video Ethernet packets (IEEE1772 or RTP) can be sent with a user−specified VLAN ID.
  • NVRAM ♦ Enabling and Disabling Protocols ♦ Updating variables in boot−time ♦ Setting unique MAC and IP address
  • Persistent Storage of Runtime Configuration (Under Review) Protocol The AP0201AT supports the following Ethernet protocols.
  • IP Protocols: ♦ IPv4 − Fully supported. ICMP, IGMP, ARP, UDP and TCP ♦ IPv6 − Please talk to your design support engineer
  • Command Protocols ♦ UDP − ON Semiconductor UDP−based Host command protocol ♦ Some/IP
  • Streaming Protocol: ♦ A VB (IEEE 1722) – The AP0201AT can be configured to send H.264 or MJPEG video packets over IEEE 1722 protocol or RTP protocol. ♦ IEEE 1722 is a layer 2 transport protocol. The destination MAC address, VLAN number and stream ID are configurable. ♦ RTP − Real−time Transport Protocol: RTP is designed for end−to−end transfer of streaming video. destination ip address, ,received port and MAC address are configurable.
  • Video Compression Protocol: ♦ H.264 – profiles supported: constrained baseline (intra frames only) and high10intra level required: up to 5.0 Both Annex B and RFC6184 formatting are supported. ♦ MJPEG – JPEG compression of YCbCr 4:2:0 images with standard headers or RFC2435 headers.
  • Precision Time Protocol: ♦ IEEE 1588−2008 (PTP) ♦ Delay Mechanism − End−to−End (Multicast) − Peer−to−Peer (Multicast) ♦ PTP Operational Mode − Master − Slave (default) ♦ Best Master Clock (BMC) Algorithm ♦ PTP Supported Messages − Announce message − Sync and Follow_Up message − Delay_Req and Delay_Resp messages − Pdelay_req and Pdelay_Resp_Follow_Up messages − Management message ♦ IEEE 802.1as (gPTP)
  • Configuration Protocols ♦ DHCP4 − IP address, Subnet Mask, Domain Name, and Host Name can be updated via DHCP4 ♦ DHCP6
  • Custom Diagnostic Protocol − ON Semiconductor command protocol can be used to retrieve diagnostic

www.onsemi.com information from the hardware. Refer to the AP0201AT Technical Note that describes the protocol in detail.

  • Hybrid operation mode: While the AP201 is in Ethernet mode, all the configurations including patches can be applied using the serial connection. Nevertheless, the video will stream out over Ethernet. This feature is useful if customer uses a micro−controller and does not want to connect a NVM(flash/eeprom) to the part.
  • Metadata UDP packets: AP201AT sends out 4 metadata UDP packets for every frame. These packets included 4 bytes if timestamp, 4 bytes of line number and sensor specific data.
  • Proxy Service: AP0201AT can open up to 4 UDP sockets over the serial interface. The AP0201AT can then send or receive packets over a user−specified port using these sockets. If proxy service is enabled, AP0201A T does not manipulate packet payload for these sockets and is transparent for these sockets. There are special set of host commands that customer can use over the serial interface to open a socket, send data, receive data and close sockets. For additional information, please refer to the technical note TN−09−333: AP0200AT Ethernet Quick Start Guide. Metadata In Ethernet mode AP0200AT sends out 4 lines of metadata over Ethernet for every frame. Each line is carried in a separate UDP packet. Costumer can specify the destination port and IP address. By default, the destination IP address and port are set to 255.255.255.255 and 50010. The UDP packet’s payload consists of following data bytes: 1. Four byte of Timestamp to match the frame. 2. Four byte of line number. AP0200AT sends line numbers zero and one at the beginning of frame. Line numbers two and three are sent at the end of frame. 3. Metadata itself. Supported PHYs The AP0201AT is compatible with most 100 Mbs MII PHYs. We have specifically tested with the following automotive−qualified PHYs: 1. BroadR Reach BCM89810, and 2. Micrel KMZ8051MNL. The AP0201AT is also compatible with most RMII PHYs (please check with your design support team for details). The AP0201AT also supports 1Gb Ethernet operation and has been tested with the Micrel KSZ9031MNX PHY . The AP0201AT is also compatible with most RMII PHYs. For all RMII, MII, and GMII PHYs not listed here, please check with your support team for details. HOST COMMAND INTERFACE The AP0201AT has a mechanism to write higher level commands, the Host Command Interface (HCI). Once a command has been written through the HCI, it will be executed by on chip firmware and the results are reported back. EEPROM or Flash memory is also available to store commands for later execution. Full details of the Host Command Interface can be found in the AP0201AT Host Command Interface (HCI) Specification document. LICENSE AGREEMENTS Portions of our 1588 support code were leveraged from BSD under the following license: Copyright (c) 2011−2012 George V . Neville−Neil, Steven Kreuzer, Martin Burnicki, Jan Breuer, Gael Mace, Alexandre Van Kempen, Inaqui Delgado, Rick Ratzel, National Instruments. Copyright (c) 2009−2010 George V . Neville−Neil, Steven Kreuzer, Martin Burnicki, Jan Breuer, Gael Mace, Alexandre Van Kempen Copyright (c) 2005 −2008 Kencall Correll, Aidan Williams All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ”AS IS” AND ANY EXPRESS OR IMPLIED W ARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY , OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY , WHETHER IN CONTRACT,

ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. or implied, of the FreeBSD Project. operational sections of this specification is not implied. extended periods may affect reliability. Table 11. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected. Table 12. ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Figure 13. MII I/O Timing Diagram Table 13. MII I/O TIMING CHARACTERISTICS

Figure 14. RMII I/O Timing Diagram Table 14. RMII I/O TIMING CHARACTERISTICS

www.onsemi.com GMII I/O Timing GTX_CLK TXD tsetup_txd thold_txd RX_CLK RXD tsetup_rxd thold_rxd Figure 15. GMII I/O Timing Diagram Table 15. GMII I/O TIMING CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 16. DC ELECTRICAL CHARACTERISTICS

  1. V IL and VIH have min/max limitations specified by absolute ratings.
  2. Excludes pins that have internal PU resistors.

Table 17. INPUT CLOCKS PIXCLK_IN 10 74.25 80 Clock for parallel input bus (from sensor). HISPI_CLK 30 300 Clock for HISPI image data receiver. Table 18. OUTPUT CLOCKS MCLK 10 27 29 Primary clock to sensor. Equals EXTCLK. GTX_CLK 18 74.25/25 80/125 Clock of parallel output bus. If pad voltage is 1.8 V nominal, then max frequency is 80 MHz. If 2.5 V or 3.3 V, then 125 MHz. See electrical specs. SPI_CLK 1 20 SPI clock to nonvolatile external memory. Figure 16. Frame_Sync Diagram Table 19. TRIGGER TIMING

Table 20. STANDBY CURRENT CONSUMPTION Table 21. INRUSH CURRENT Table 22. OPERATING CURRENT CONSUMPTION − SENSOR PARALLEL OUTPUT Table 23. OPERATING CURRENT CONSUMPTION − SENSOR HISPI OUTPUT

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