AP0100CS2L00SPGAD3-GEVK

AP0100CS ONSEMI | Alldatasheet

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AP0100CS/D Rev. 6, 1/16 EN 1 ©Semiconductor Components Industries, LLC 2016, AP0100CS High-Dynamic Range (HDR) Image Signal Processor (ISP) AP0100CS Datasheet, Rev. 6 For the latest product datasheet, please visit www.onsemi.com

• Up to 1.2Mp (1280x960) ON Semiconductor sensor support  45 fps at 1.2Mp, 60 fps at 720p  Optimized for operation with HDR sensors.  Color and gamma correction  Auto exposure, auto white balance, 50/60 Hz auto flicker detection and avoidance  Adaptive Local Tone Mapping (ALTM)  Programmable Spatial Transform Engine (STE).  Pre-rendered Graphical Overlay  Two-wire serial progra mming interface (CCIS)  Interface to low-cost Flash or EEPROM through SPI bus (to configure and load patches, etc.)  High-level host command interface  Standalone operation supported  Up to 5 GPIO F a i l - s a f e I O  Multi-Camera synchronization support  Integrated video encoder for NTSC/PAL with overlay capability and 10-bit I-DAC

Applications

 IP cam and CCTV - HD  Enables CCTV -HD w/ MP sensor Notes: 1. Table 1: Key Performance Parameters Parameter Value Primary camera interfaces Parallel and HiSPi Primary camera input RAW12 Linear/RAW12, RAW14 (HiSPi format only) Companded Output interface Analog composite, up to 16-bit parallel digital output Output format YUV422 8-bit,10-bit, and 10-, 12-bit tone-mapped Bayer Maximum resolution 1280x960 (1.2 Mp) NTSC output 720H x 487V PAL output 720H x 576V Input clock range 6-30 MHz Supply voltage V DDIO_S 1.8 or 2.8 V nominal VDDIO_H 2.5 or 3.3 V nominal VDD_REG 1.8 V nominal VDD 1.2 V nominal VDD_PLL 1.2 V nominal VDD_DAC 1.2V nominal VDDIO_OTPM 2.5 or 3.3 V nominal VDDA_DAC 3.3 V nominal VDD_PHY 2.8 V nominal Operating temp. –30°C to +70°C Power consumption 185 mW

AP0100CS/D Rev. 6, 1/16 EN 2 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP)

Ordering Information

See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documenta- tion, including information on evaluation kits, please visit our web site at www.onsemi.com. Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description AP0100CS2L00SUGA0-DR1 1Mp Co-Processor, 100-ball VFBGA Drypack AP0100CS2L00SPGAD3-GEVK AP0100CS Demo Kit AP0100CS2L00SPGAH-GEVB AP0100CS Head Board

AP0100CS/D Rev. 6, Pub. 1/16 EN 3 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Table of Contents Table of Contents

AP0100CS/D Rev. 6, Pub. 1/16 EN 5 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) System Interfaces Figure 2: Typical Pa rallel Configuration Notes: 1. This typical configuration shows only one scen ario out of multiple possible variations for this device. 2. ON Semiconductor recommends a 1.5k resistor value for the two-wire serial interface RPULL-UP; however, greater values may be used for slower transmission speed. 3. RESET_BAR has an internal pull-up resistor and can be left floating if not used. 4. The decoupling capacitors for the regulator input and output should have a value of 1.0uF. The capacitors should be ceramic and need to have X5R or X7R dielectric. 5. TRST_BAR connects to GND for normal operation. 6. ON Semiconductor recommends that 0.1 F and 1F decoupling capacitors for each power supply are mounted as close as possible to the pin. Actual values and numbers may vary depending on lay- out and design consideration VDDIO_OTPMLDO_OP4VDD_REG4VDDIO_S6 VDDIO _S VDDIO _H Sensor IO power Host IO power M_SCLK M_ SDATA EXTCLK_OUT RESET_BAR_OUT FV_IN LV_IN PIXCLK_ IN DIN [11:0] TRIGGER_OUT VDD_REG ENLDO FB_SENSE LDO_OP VDD_PLL 1.8V ( R egulator IP) VDD 1 . 2 V (R egulator OP) P ower up C ore, P LL. and DAC digital GND _ REG FV_OUT LV_OUT PIXCLK_OUT DOUT[15:0] SCLK SDATA SADDR SPI_CS_BAR SPI_CLK SPI_SDO SPI_SDI TRST_BAR5 VDDIO_OTPM OTPM power VDDIO_H GND GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 EXTCLK XTAL VDDIO_DAC DAC_POS DAC_NEG DAC_REF VDD_DAC EXT_REG DAC analog power VDDA_DAC VDD_PHY FRAME_SYNC

AP0100CS HDR: Image Signal Processor (ISP) System Interfaces AP0100CS/D Rev. 6, Pub. 1/16 EN 6 ©Semiconductor Components Industries, LLC,2016. Figure 3: Typical HiSPi Configuration HiSPi and Parallel Connection When using the HiSPi interface, the user should connect the parallel interface to VDDIO_S. When using the parallel interface, the HiSPi interface and power supply (V DD_PHY) can be left floating. VDDIO_OTPMLDO_OP4VDD_REG4VDDIO_S6 VDDIO _S VDDIO _H Sensor IO power Host IO power M_SCLK M_ SDATA EXTCLK_OUT RESET_BAR_OUT FV_IN LV_IN PIXCLK_ IN DIN [11:0] TRIGGER_OUT VDD_REG ENLDO 1.8V ( R egulator IP) GND _ REG FV_OUT LV_OUT PIXCLK_OUT DOUT[15:0] SCLK SDATA SADDR SPI_CS_BAR SPI_CLK SPI_SDO SPI_SDI TRST_BAR5 VDDIO_OTPM OTPM power VDDIO_H GND GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 EXTCLK XTAL VDDIO_DAC DAC_POS DAC_NEG DAC_REF CLK_N CLK_P DATA0_N DATA0_P DATA1_N DATA1_P FB_SENSE LDO_OP VDD_PLL VDD 1 . 2 V (R egulator OP) P ower up C ore, P LL. and DAC digital VDD_DAC EXT_REG DAC analog power VDDA_DAC VDD_PHY HiSPi voltage VDDIO_PHY Sensor IO power FRAME_SYNC

AP0100CS/D Rev. 6, Pub. 1/16 EN 7 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) System Interfaces Crystal Usage As an alternative to using an external oscillator, a crystal may be connected between EXTCLK and XTAL. Two small loading capacitors and a feedback resistor should be added, as shown in Figure 4. Figure 4: Using a Crystal Inst ead of an External Oscillator Rf represents the feedback resistor, an Rf value of 1M is sufficient for AP0100CS. C1 and C2 are decided according to the crystal or resonator CL specification. In the steady state of oscillation, CL is defined as (C1 x C2)/(C1+C2). In fact, the I/O ports, the bond pad, package pin and PCB traces all contribute the parasitic capacitance to C1 and C2. There- fore, CL can be rewritten to be (C1* x C2*)/(C1*+C2*), where C1*=(C1+Cin, stray) and C2*=(C2+Cout, stray). The stray capacitance for the IO ports, bond pad and package pin are known which means the formulas can be rewritten as C1*=(C1+1.5pF+Cin, PCB) and C2*=(C2+1.3pF+Cout, PCB). Table 3: Pin Descriptions Name Type Description EXTCLK Input Master input clock. This can either be a square-wave generated from an oscillator (in which case the XTAL input must be left unconnected) or direct connection to a crystal. XTAL Output If EXTCLK is connected to one pin of a crystal, the other pin of the crystal is connected to XTAL pin; otherwise this signal must be left unconnected. RESET_BAR Input/PU Master reset signal, active LOW. This signal has an internal pull up. SCLK Input Two-wire serial interface clock (host interface). SDATA I/O Two-wire serial interface data (host interface). SADDR Input Selects device address for the two-wire slave serial interface. When connected to GND the device ID is 0x90. When wired to VDDIO_H, a device ID of 0xBA is selected. FRAME_SYNC Input This signal is used to synchronize to external sources or multiple cameras together. This signal should be connected to GND if not used. STANDBY Input Standby mode control, active HIGH. EXT_REG Input Select external regulator if tied high EXTCLK XTAL AP0100CS Rf=1MΩ

AP0100CS HDR: Image Signal Processor (ISP) System Interfaces AP0100CS/D Rev. 6, Pub. 1/16 EN 8 ©Semiconductor Components Industries, LLC,2016. ENDLO Input Regulator enable (VDD_REG domain) SPI_SCLK Output Clock output for interfacing to an external SPI flash or EEPROM memory. SPI_SDI Input/PU Data in from SPI flash or EEPROM memory. When no SPI device is fitted, this signal is used to determine whether the AP0100CS should auto-configure: 0: Do not auto-configure; Two-wire interface will be used to configure the device (host-config mode) 1: Auto-configure. This signal has an internal pull- up resistor. SPI_SDO Output Data out to SPI flash or EEPROM memory. SPI_CS_BAR Output Chip select out to SPI flash or EEPROM memory. EXT_CLK_OUT Output Clock to external sensor. RESET_BAR_OUT Output Reset signal to external signal. M_SCLK Output Two-wire serial interface clock (Master). M_SDATA I/O Two-wire serial interface clock (Master). FV_IN Input Sensor frame valid input. LV_IN Input Sensor line valid input. PIXCLK_IN Input Sensor pixel clock input. DIN[11:0] Input Sensor pixel data input DIN[11:0] CLK_N Input Differential HiSPi clock (sub-LVDS, negative). CLK_P Input Differential HiSPi clock (sub-LVDS, positive). DATA0_N Input Differential HiSPi data, lane 0 (sub-LVDS, negative). DATA0_P Input Differential HiSPi data, lane 0 (sub-LVDS, positive). DATA1_N Input Differential HiSPi data, lane 1 (sub-LVDS, negative). DATA1_P Input Differential HiSPi data, lane 1 (sub-LVDS, positive). TRIGGER_OUT Output Trigger signal for external sensor. FV_OUT Output Host frame valid output (synchronous to PIXCLK_OUT) LV_OUT Output Host line valid output (synchronous to PIXCLK_OUT) PIXCLK_OUT Output Host pixel clock output. DOUT[15:0] Output Host pixel data output (synchronous to PIXCLK_OUT) DOUT[15:0]. DAC_POS Output Positive video DAC output in differential mode. Video DAC output in single- ended mode. This interface is enabled by default using NTSC/PAL signaling. For applications where composite video output is not required, the video DAC can be placed in a power-down state under software control. DAC_NEG Output Negative video DAC output in differential mode. DAC_REF Output External reference resistor for Video DAC. GPIO [5:1] I/O General purpose digital I/O. TRST_BAR Input Must be tied to GND in normal operation. VDDIO_S Supply Sensor I/O power supply. VDDIO_H Supply Host I/O power supply. VDD_PLL Supply PLL supply. VDD Supply Core supply. VDDIO_OTPM Supply OTPM power supply. VDD_DAC Supply Video DAC digital power VDDA_DAC Supply Video DAC analog power VDD_PHY Supply PHY IO voltage for HiSPi Table 3: Pin Descriptions (Continued) Name Type Description

AP0100CS/D Rev. 6, Pub. 1/16 EN 9 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) System Interfaces GND Supply Ground VDD_REG Supply Input to on-chip 1.8V to 1.2V regulator. LDO_OP Output Output from on chip 1.8V to 1.2V regulator. FB_SENSE Output On-chip regulator sense signal. Table 3: Pin Descriptions (Continued) Name Type Description

AP0100CS/D Rev. 6, Pub. 1/16 EN 10 ©Semiconductor Components Industries, LLC,2016 Part Number: Image Signal Processor (ISP) System Interfaces Table 4: Package Pinout 1 2 3 4 5 6 7 8 9 10 A DOUT[11] DOUT[13] PIXCLK_OUT LV_OUT GPIO_2 TRST_BAR SPI_SDI S ADDR SCLK STANDBY B DOUT[12] DOUT[10] D OUT[14] FV_OUT GPIO_3 GPIO[5] SPI_SCLK S DATA TRIGGER_OUT RESET_BAR_OUT C DOUT[9] DOUT[8] D OUT[15] GPIO[1] GPIO_4 SPI_CS_BAR SPI_SDO V DDIO_H M_S DATA M_SCLK D DOUT[5] DOUT[6] D OUT[7] V DDIO_H V DDIO_HOST V DD FRAME_SYNC V DD FV_IN M CLK_OUT E DOUT[2] DOUT[3] D OUT[4] V DDIO_H GND GND GND LV_IN PIXCLK_IN D IN[11] F DOUT[0] DOUT[1] EXTCLK V DDIO_H GND GND GND V DDIO_S D IN[9] D IN[10] G GND VDD_PLL XTAL V DD VDD VDD GND D IN[6] D IN[7] D IN[8] H VDD_PLL VDD_PLL LDO_OUTPUT V DDIO_OTPM DAC_NEG DAC_REF GNDA_DAC V DD_PHY D IN[4] D IN[5] J EXT_REG RESET_BAR V DD_REG V DD_DAC DAC_POS DATA0_P CLK_P DATA1_N D IN[0] D IN[2] K GND FB_SENSE ENLDO GND V DDA_DAC DATA0_N CLK_N DATA1_P D IN[1] D IN[3]

AP0100CS/D Rev. 6, Pub. 1/16 EN 11 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) On-Chip Regulator On-Chip Regulator The AP0100CS has an on-chip regulator, the output from the regulator is 1.2 V and should only be used to power up the AP0100CS. It is possible to bypass the regulator and provide power to the relevant pins that need 1.2 V. Figure 5 shows how to configure the AP0100CS to bypass the internal regulator. Figure 5: Exte rnal Regulator The following table summarizes the key signals when using/bypassing the regulator. Table 5: Key Signals When Using the Regulator Signal Name Internal Regulator External Regulator VDD_REG 1.8 V Connect to VDDIO_H ENLDO Connect to 1.8 V (V DD_REG) GND FB_SENSE 1.2 V (output) Float LDO_OP 1.2 V (output) Float EXT_REG GND Connect to VDDIO_H VDDIO _S VDDIO _H Sensor IO power Host IO power M_SCLK M_ SDATA EXTCLK_OUT RESET_BAR_OUT FV_IN LV_IN PIXCLK_ IN DIN [11:0] TRIGGER_OUT VDD_REG GND FV_OUT LV_OUT PIXCLK_OUT DOUT[15:0] SCLK SDATA SADDR SPI_CS_BAR SPI_CLK SPI_SDO SPI_SDI TRST_BAR VDDIO_OTPM OTPM power GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 EXTCLK XTAL DAC_POS DAC_NEG DAC_REF CLK_N CLK_P DATA0_N DATA0_P DATA1_N DATA1_P FB_SENSE LDO_OP VDD_PLL VDD External supplied 1.2V VDD_DAC EXT_REG DAC analog power VDDA_DAC VDD_PHY PHY power FRAME_SYNC STANDBY Host IO power Host IO power ENLDO

AP0100CS/D Rev. 6, Pub. 1/16 EN 13 ©Semiconductor Components Industries, LLC,2016 Part Number: Image Signal Processor (ISP) On-Chip Regulator Table 7: Output States Name Hardware States Firmware States NotesReset State Default State Hard Standby Soft Standby Streaming Idle EXTCLK (clock running or stopped) (clock running) (clock running or stopped) (clock running) (clock running) (clock running) Input XTAL n/a n/a n/a n/a n/a n/a Input RESET_BAR (asserted) (negated) (negated ) (negated) (negated) (negated) Input SCLK n/a n/a (clock running or stopped) (clock running or stopped) (clock running or stopped) (clock running or stopped) Input. Must always be driven to a valid logic level SDATA High- impedance High- impedance High- impedance High- impedance Input/Output. A valid logic level should be established by pull-up SADDR n/a n/a n/a n/a n/a n/a Input. Must always be driven to a valid logic level FRAME_SYNC n/a n/a n/a n/a n/a n/a Input. Must always be driven to a valid logic level STANDBY n/a (negated) (asserted) (negated) (negated) (negated) Input. Must always be driven to a valid logic level EXT_REG n/a n/a n/a n/a n/a n/a Input. Must always be driven to a valid logic level E N L D O n / an / an / an / an / an / aI n p ut. Must be tied to VDD_REG or GND SPI_SCLK High- impedance driven, logic 0 driven, logic 0 driven, logic 0 Output SPI_SDI Internal pull- up enabled Internal pull- up enabled Internal pull- up enabled internal pull- up enabled Input. Internal pull-up permanently enabled. SPI_SDO High- impedance driven, logic 0 driven, logic 0 driven, logic 0 Output SPI_CS_BAR High- impedance driven, logic 1 driven, logic 1 driven, logic 1 Output EXT_CLK_OUT driven, logic 0 driven, logic 0 driven, logic 0 driven, logic 0 Output RESET_BAR_O UT driven, logic 0 driven, logic 0 driven, logic 1 driven, logic 1 Output. Firmware will release sensor reset M_SCLK High- impedance High- impedance High- impedance High- impedance Input/Output. A valid logic level should be established by pull-up M_SDATA High- impedance High- impedance High- impedance High- impedance Input/Output. A valid logic level should be established by pull-up FV_IN ,LV_IN, PIXCLK_IN, DIN[11:0] n/a n/a n/a n/a Dependent on interface used n/a Input. Must always be driven to a valid logic level

AP0100CS/D Rev. 6, Pub. 1/16 EN 14 ©Semiconductor Components Industries, LLC,2016 Part Number: Image Signal Processor (ISP) On-Chip Regulator CLK_N Disabled Disabled Dependent on interface used Dependent on interface used Dependent on interface used Dependent on interface used Input. Will be disabled and can be left floating CLK_P DATA0_N DATA0_P DATA1_N DATA1_P FV_OUT, LV_OUT, PIXCLK_OUT, DOUT[15:0] High- impedance Varied Driven if used Driven if us ed Driven if used Driven if used Output. Default state dependent on configuration DAC_POS Varied Varied Driven if used Driven if used Driven if used Driven if used Output. Default state dependent on configuration. Tie to ground if VDAC not usedDAC_NEG DAC_REF n/a n/a n/a n/a n/a n/a Input. Requires reference resistor. Tie to ground if VDAC not used GPIO[5:2] High- impedance Input, then high- impedance Driven if used Driven if used Driven if used Driven if used Input/Output. After reset, these pins are sampled as inputs as part of auto- configuration. GPIO1 High- impedance High- impedance High- impedance High- impedance High- impedance High- impedance TRIGGER_OUT High- impedance High- impedance Driven if used Driven if used Driven if used Driven if used TRST_BAR n/a n/a (negated) (negated) (negated) (negated) Input. Must always be driven to a valid logic level. Table 7: Output States Name Hardware States Firmware States NotesReset State Default State Hard Standby Soft Standby Streaming Idle

AP0100CS/D Rev. 6, Pub. 1/16 EN 15 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) On-Chip Regulator Hard Reset The AP0100CS enters the reset state when the external RESET_BAR signal is asserted LOW, as shown in Figure 7. All the output signals will be in High-Z state. Figure 7: Hard Reset Operation Soft Reset A soft reset sequence to the AP0100 CS can be activated by writing to a register through the two-wire serial interface. Hard Standby Mode The AP0100CS can enter hard standby mode by using external STANDBY signal, as shown in Figure 8. Entering Standby Mode 1. Assert STANDBY signal HIGH. Table 8: Hard Reset Symbol Definition Min Typ Max Unit t1 RESET_BAR pulse width 50 – – EXTCLK cycles t2 Active EXTCLK required after RESET_BAR asserted 10 – – t3 Active EXTCLK required before RESET_BAR de- asserted 10 – – t4 First two-wire serial interface communication after RESET is HIGH 100 – – EXTCLK Reset RESET_BAR Mode Internal Initialization Time SDATA Enter streaming mode All Outputs Data Active Data Active

AP0100CS HDR: Image Signal Processor (ISP) On-Chip Regulator AP0100CS/D Rev. 6, Pub. 1/16 EN 16 ©Semiconductor Components Industries, LLC,2016. Exiting Standby Mode 1. De-assert STANDBY signal LOW. Figure 8: Hard Standby Operation Table 9: Hard Standby Signal Timing Symbol Parameter Min Typ Max Unit t1 Standby entry complete – – 2 Frames Lines t2 Active EXTCLK required after going into STANDBY mode 10 – – EXTCLKs t3 Active EXTCLK required before STANDBY de-asserted 10 – – EXTCLKs EXTCLK STANDBY STANDBY Asserted STANDBY Mode EXTCLK Disabled t2 t3 EXTCLK EnabledMode

AP0100CS HDR: Image Signal Processor (ISP) Multi-Camera Synchronization Support AP0100CS/D Rev. 6, Pub. 1/16 EN 18 ©Semiconductor Components Industries, LLC,2016. Figure 11: Continuous Mode Note: This diagram is not to scale. When two or more cameras have a signal applied to the FRAME_SYNC input at the same time, the respective FV_OUT signals would be synchronized within 5 PIXCLK_OUT cycles. This assumes that all cameras have the same configuration settings and that the exposure time is the same. FRAME_SYNC TRIGGER_OUT FV_OUT

AP0100CS/D Rev. 6, Pub. 1/16 EN 19 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Image Flow Processor Image Flow Processor Image and color processing in the AP0100CS is implemented as an image flow processor (IFP) coded in hardware logic. During normal operation, the embedded microcontroller will automatically adjust the operating parameters. For normal operation of the AP0100CS, streams of raw image data from the attached image sensor are fed into the color pipeline. The user also has the option to select a number of test patterns to be input instead of sensor data. The IFP is broken down into different sections, as outlined in Figure 12. Figure 12: AP0100CS IFP linear or com panded data D efect correction , Noise reduction RX decom panding Black level subtraction, D igital gain control, PGA RAW 12- or 20 - bit Bayer AE, FD and ALTM stats 1 2 - bit ALTM Bayer Co lo r InterpolationALTM Co lo r Co rre ct io n Aperture C orrection Gamma RGB2 YUV AW B stats Co lo r Kill YUV filters ScalerCro p Progressive Test pattern generator STE Interlacer Overlay RAW Bayer ALTM Bayer RGB YCbCr PAL/ NTSC Test patterns PAL/ NTSC Encode DAC Pr ogr essive (YCbCr or Bayer ) CCIR656 ( YCbCr ) NTSC/ PAL ( YCbCr )

AP0100CS HDR: Image Signal Processor (ISP) Test Patterns AP0100CS/D Rev. 6, Pub. 1/16 EN 20 ©Semiconductor Components Industries, LLC,2016. Test Patterns The AP0100CS has a number of test patterns that are available when using the progres- sive, NTSC and PAL modes. The test patterns can be selected by programming variables. To enter test pattern mode, set R0xC88F to 0x02 and issue a Change-Config request; to exit this mode, set R0xC88F to 0x00, and issue a Change-Config request. NTSC and PAL test patterns can only be selected when the device is configured for inter- laced operation. Progressive Test Patterns Figure 13: Progressive Test Patterns Test Pattern Example FLAT FIELD REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x01 // CAM_MODE_TEST_PATTERN_SELECT REG= 0xC890, 0x000FFFFF // CAM_MODE_TEST_PATTERN_RED REG= 0xC894, 0x000FFFFF // CAM_MODE_TEST_PATTERN_GREEN REG= 0xC898, 0x000FFFFF // CAM_MODE_TEST_PATTERN_BLUE Load = Change-Config Changing the values in R0xC890-R0x898 will change the color of the test pattern (will require a Refresh operation). 100% Color Bar REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x02 // CAM_MODE_TEST_PATTERN_SELECT Load = Change-Config Pseudo-Random REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x05 // CAM_MODE_TEST_PATTERN_SELECT Load = Change-Confi g Linear Ramp REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x09 // CAM_MODE_TEST_PATTERN_SELECT Load = Change-Config Fade-to-Gray REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x08 // CAM_MODE_TEST_PATTERN_SELECT Load = Change-Config

AP0100CS/D Rev. 6, Pub. 1/16 EN 21 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Test Patterns NTSC Test Patterns Figure 14: NTSC Test Patterns Test Pattern Example EIA Full Field 7 Color Bars REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x14 // CAM_MODE_TEST_PATTTERN_SELECT Load = Change-Config EIA Full Field 8 Color Bars REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x15 // CAM_MODE_TEST_PATTERN_SELECT Load = Change-Config SMPTE EG 1-1990 REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x16 // CAM_MODE_TEST_PATTERN_SELECT Load = Change-Confi g EIA Full Field 8 Color Bars 100 IRE REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x17 // CAM_MODE_TEST_PATTERN_SELECT Load = Change-Config

AP0100CS HDR: Image Signal Processor (ISP) Test Patterns AP0100CS/D Rev. 6, Pub. 1/16 EN 22 ©Semiconductor Components Industries, LLC,2016. PAL Test Patterns Figure 15: PAL Test Patterns Each NTSC/PAL test pattern consists of seven or eight color bars (white, yellow, cyan, green, magenta, red, blue and optionally black). The Y, Cb and Cr values for each bar are detailed in Table 10. For the NTSC SMPTE test pattern it is also required to generate -I, +Q, -4 black and +4 black. Table 10: NTSC/PAL Test Pattern Values Nominal Range White 100% White 75% Yellow Cyan Green Magent a Red Blue Black -I -Q black black Y 16 to 235 235 180 162 131 112 84 65 35 16 16 16 7 25 Cb 16 to 240 128 128 44 156 72 184 100 212 128 156 171 128 128 Cr 16 to 240 128 128 142 44 58 198 212 114 128 97 148 128 128 Test Pattern Example EBU Full Field 7 Color Bars REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x1E // CAM_MODE_TEST_PATTERN_SELECT Load = Change-Config EBU Full Field 8 Color Bars REG= 0xC88C, 0x02 // CAM_MODE_SELECT REG= 0xC88F, 0x1F // CAM_MODE_TEST_PATTERN_SELECT Load = Change-Config

AP0100CS/D Rev. 6, Pub. 1/16 EN 23 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Test Patterns Figure 16: Test Pattern Defect Correction Image stream processing commences with the defect correction function immediately after data decompanding. To obtain defect free images, the pixels marked defective during sensor readout and the pixels determined defective by the defect correction algorithms are replaced with values derived from the non-defective neighboring pixels. This image processing technique is called defect correction. AdaCD (Adaptive Color Difference) Automotive applications require good performance in extremely low light, even at high temperature conditions. In these stringent conditions the image sensor is prone to higher noise levels, and so efficient noise reduction techniques are required to circum- vent this sensor limitation and deliver a high quality image to the user. The AdaCD Noise Reduction Filter is able to adapt its noise filtering process to local image structure and noise level, removing most objectionable color noise while preserving edge details. Black Level Subtraction and Digital Gain After noise reduction, the pixel data goes through black level subtraction and multiplica- tion of all pixel values by a programmable digital gain. Independent color channel digital gain can be adjusted with registers. Black level subtraction (to compensate for sensor data pedestal) is a single value applied to all color channels. If the black level subtraction produces a negative result for a particular pixel, the value of this pixel is set to 0.

AP0100CS HDR: Image Signal Processor (ISP) Test Patterns AP0100CS/D Rev. 6, Pub. 1/16 EN 24 ©Semiconductor Components Industries, LLC,2016. Positional Gain Adjustments (PGA) Lenses tend to produce images whose brightness is significantly attenuated near the edges. There are also other factors causing fixed pattern signal gradients in images captured by image sensors. The cumulative result of all these factors is known as image shading. The AP0100CS has an embedded shading correction module that can be programmed to counter the shading effects on each individual R, Gb, Gr, and B color signal. The Correction Function The correction functions can then be applied to each pixel value to equalize the response across the image as follows: (EQ 1) where P are the pixel values and f is the color dependent correction functions for each color channel. Pcorrected row, col Psensor row, col f(row, col)=

AP0100CS/D Rev. 6, Pub. 1/16 EN 25 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Test Patterns Adaptive Local Tone Mapping (ALTM) Real world scenes often have very high dynamic range (HDR) that far exceeds the elec- trical dynamic range of the imager. Dynamic range is defined as the luminance ratio between the brightest and the darkest object in a scene. In recent years many technolo- gies have been developed to capture the full dynamic range of real world scenes. For example, the multiple exposure method is widely adopted for capturing high dynamic range images, which combines a series of low dynamic range images of the same scene taken under different exposure times into a single HDR image. Even though the new digital imaging technology enables the capture of the full dynamic range, low dynamic range display devices are the limiting factor. Today’s typical LCD monitor has contrast ratio around 1,000:1; however, it is not typical for an HDR image (the contrast ratio for an HDR image is around 250,000:1). Therefore, in order to repro- duce HDR images on a low dynamic range display device, the captured high dynamic range must be compressed to the available range of the display device. This is commonly called tone mapping. Tone mapping methods can be classified into global tone mapping and local tone mapping. Global tone mapping methods apply the same mapping function to all pixels. While global tone mapping methods provide computationally simple and easy to use solutions, they often cause loss of contrast and detail. A local tone mapping is thus necessary in addition to global tone mapping for the reproduction of visually more appealing images that also reveal scene details that are important for automotive safety and surveillance applications. Local tone mapping methods use a spatially variable mapping function determined by the neighborhood of a pixel, which allows it to increase the local contrast and the visibility of some details of the image. Local methods usually yield more pleasing results because they exploit the fact that human vision is more sensitive to local contrast. ON Semiconductor’s ALTM solution significantly improves the performance over global tone mapping. ALTM is directly applied to the Bayer domain to compress the dynamic range from 20-bit to 12-bit. This allows the regular color pipeline to be used for HDR image rendering. Color Interpolation In the raw data stream fed by the external sensor to the IFP, each pixel is represented by a 20- or 12-bit integer number, which can be considered proportional to the pixel's response to a one-color light stimulus, red, green, or blue, depending on the pixel's posi- tion under the color filter array. Initial data processing steps, up to and including ALTM, preserve the one-color-per-pixel nature of the data stream, but after ALTM it must be converted to a three-colors-per-pixel stream appropriate for standard color processing. The conversion is done by an edge-sensitive color interpolation module. The module pads the incomplete color information available for each pixel with information extracted from an appropriate set of neighboring pixels. The algorithm used to select this set and extract the information seeks the best compromise between preserving edges and filtering out high frequency noise in flat field areas. The edge threshold can be set through register settings.

AP0100CS HDR: Image Signal Processor (ISP) Test Patterns AP0100CS/D Rev. 6, Pub. 1/16 EN 26 ©Semiconductor Components Industries, LLC,2016. Color Correction and Aperture Correction To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are subjected to color correction. The IFP multiplies each vector of three pixel colors by a 3 x 3 color correction matrix. The three components of the resulting color vector are all sums of three 10-bit numbers. The color correction matrix can be either programmed by the user or automatically selected by the auto white balance (AWB) algorithm imple- mented in the IFP. Color correction should ideally produce output colors that are corrected for the spectral sensitivity and color crosstalk characteristics of the image sensor. The optimal values of the color correction matrix elements depend on those sensor characteristics and on the spectrum of light incident on the sensor. The color correction variables can be adjusted through register settings. Traditionally this would have been derived from two sets of CCM, one for Warm light like Tungsten and the other for Daylight (the part would interpolate between the two matrices). This is not an optimal solution for cameras used in a Cool White Fluorescent (CWF) environment. A better solution is to provide three CCMs, which would include a matrix for CWF (interpolation now between three matrices). The AP0100CS offers this feature which will give the user improved color fidelity when under CWF type lighting. To increase image sharpness, a programmable 2D aperture correction (sharpening filter) is applied to color-corrected image data. The gain and threshold for 2D correction can be defined through register settings. Gamma Correction The gamma correction curve is implemented as a piecewise linear function with 33 knee points, taking 12-bit arguments and mapping them to 10-bit output. The abscissas of the knee points are fixed at 0, 8, 16, 24, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 256, 320, 384, 448, 512, 640, 768, 896, 1024, 1280, 1536, 1792, 2048, 2560, 3072, 3584, and 4096. The 10-bit ordinates are programmable through variables. The AP0100CS has the ability to calculate the 33-point knee points based on the tuning of cam_ll_gamma and cam_ll_contrast_gradient_bright. The other method is for the host to program the 33 knee point curve themselves. Also included in this block is a Fade-to Black curve which sets all knee points to zero and causes the image to go black in extreme low light conditions. Color Kill To remove high-or low-light color artifacts, a color kill circuit is included. It affects only pixels whose luminance exceeds a certain preprogrammed threshold. The U and V values of those pixels are attenuated proportionally to the difference between their lumi- nance and the threshold. YUV Color Filter As an optional processing step, noise suppression by one-dimensional low-pass filtering of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.

AP0100CS/D Rev. 6, Pub. 1/16 EN 27 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Camera Control and Auto Functions Camera Control and Auto Functions Auto Exposure The auto exposure algorithm optimizes scene exposure to minimize clipping and satu- ration in critical areas of the image. This is achieved by controlling exposure time and analog gains of the external sensor as well as digital gains applied to the image. Auto exposure is implemented by a firmware algorithm that is running on the embedded microcontroller that analyzes image statistics collected by the exposure measurement engine, makes a decision, and programs the sensor and color pipeline to achieve the desired exposure. The measurement engine subdivides the image into 25 windows organized as a 5 x 5 grid. Figure 17: 5 x 5 Grid AE Track Driver Other algorithm features include the rejection of fast fluctuations in illumination (time averaging), control of speed of response, and control of the sensitivity to small changes. While the default settings are adequate in most situations, the user can program target brightness, measurement window, and other parameters described above. The driver changes AE parameters (integration time, gains, and so on) to drive scene brightness to the programmable target. To avoid unwanted reaction of AE on small fluctuations of scene brightness or momen- tary scene changes, the AE track driver uses a temporal filter for luma and a threshold around the AE luma target. The driver changes AE parameters only if the filtered luma is larger than the AE target step and pushes the luma beyond the threshold.

AP0100CS HDR: Image Signal Processor (ISP) Camera Control and Auto Functions AP0100CS/D Rev. 6, Pub. 1/16 EN 28 ©Semiconductor Components Industries, LLC,2016. Auto White Balance The AP0100CS has a built-in AWB algorithm designed to compensate for the effects of changing spectra of the scene illumination on the quality of the color rendition. The algorithm consists of two major parts: a measurement engine performing statistical analysis of the image and a driver performing the selection of the optimal color correc- tion matrix and IFP digital gain. While default settings of these algorithms are adequate in most situations, the user can reprogram base color correction matrices, place limits on color channel gains, and control the speed of both matrix and gain adjustments. The AP0100 CSAWB displays the current AWB position in color temperature, the range of which will be defined when programming the CCM matrixes. The region of interest can be controlled through the combination of an inclusion window and an exclusion window. Exposure and White Balance Control The Sensor Manager firmware component is responsible for controlling the application of 'exposure' and 'white balance' within the system. This effectively means that all control of integration times and gains (whether for exposure or white balance) is dele- gated to the Sensor Manager. The Auto Exposure (AE) and Auto White Balance (AWB) algorithms use services provided by the Sensor Manager to apply exposure and/or white balance changes. Dual Band IRCF For some applications a day/night filter would be switched in/out, this option is an additional cost to the camera system. The AP0100CS supports the use of dual band IRCF, which removes the need for the switching day/night filter. Tuning support is provided for this usage case. Refer to the AP0100CS developer guide for details. Exposure and White Balance Modes The AP0100CS supports auto and manual exposure and white balance modes. In addi- tion, it will operate within synchronized multi-camera systems. In this use case, one camera within the system will be the 'master', and the others 'slaves'. The master is used to calculate the appropriate exposure and white balance. This is then applied to all slaves concurrently under host control. Auto Mode In Auto Exposure mode the AE algorithm is responsible for calculating the appropriate exposure to keep the desired scene brightness, and for applying the exposure to the underlying hardware. In Auto White Balance mode the AWB algorithm is responsible for calculating the color temperature of the scene and applying the appropriate red and blue gains to compensate. Triggered Auto Mode The Triggered Auto Exposure and Triggered Auto White Balance modes are intended for the multi-camera use cases, where a host is controlling the exposure and white balance of a number of cameras. The idea is that one camera is in triggered-auto mode (the master), and the others in host-controlled mode (slaves). The master camera must calculate the exposure and gains, the host then copies this to the slaves, and all changes are then applied at the same time.

AP0100CS/D Rev. 6, Pub. 1/16 EN 29 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Flicker Avoidance Manual Mode Manual mode is intended to allow simple manual exposure and white balance control by the host. The host needs to set the CAM_AET_EXPOSURE_TIME_MS, CAM_AET_EX- POSURE_GAIN and CAM_AWB_COLOR_TEMPERATURE controls, the camera will calculate the appropriate integration times and gains. Host Controlled The Host Controlled mode is intended to give the host full control over exposure and gains Flicker Avoidance Flicker occurs when the integration time is not an integer multiple of the period of the light intensity. The AP0100CS can be programmed to avoid flicker for 50 or 60 Hertz. For integration times below the light intensity period (10ms for 50Hz environment), flicker cannot be avoided. The AP0100CS supports an indoor AE mode, that will ensure flicker- free operation. Flicker Detection The AP0100CS supports flicker detection, the algorithm is designed only to detect a 50Hz or 60Hz flicker source. Output Formatting The pixel output data in AP0100CS will be transmitted as an 8/10 bit word over one or two clocks. Uncompressed YCbCr Data Ordering The AP0100CS supports swapping YCbCr mode, as illustrated in Table 11. The data ordering for the YCbCr output modes for AP0100CS are shown in Table 12: Table 11: YCbCr Output Data Ordering Mode Data Sequence Default (no swap) Cbi Yi Cri Yi+1 Swapped CrCb Cri Yi Cbi Yi+1 Swapped YC Yi Cbi Yi+1 Cri Swapped CrCb, YC Yi Cri Yi+1 Cbi Table 12: YCbCr Output Modes (c am_port_parallel_msb_align=0x1) Mode Byte Pixel i Pixel i+1 Notes YCbCr_422_8_8 Odd (DOUT [15:8]) Cbi Cri Data range of 0-255 (Y=16-235 and C=16-240) Even (DOUT [15:8]) Yi Yi+1 YCbCr_422_10_10 Odd (DOUT [15:6]) Cbi Cri Data range of 0-1023 (Y=64-940 and C=64- 960) Even (DOUT [15:6]) Yi Yi+1 YCbCr_422_16 Single (D OUT [15:0]) Cbi_Yi Cri_Yi+1 Data range of 0-255 (Y=16-235 and C=16-240)

AP0100CS HDR: Image Signal Processor (ISP) Output Formatting AP0100CS/D Rev. 6, Pub. 1/16 EN 30 ©Semiconductor Components Industries, LLC,2016. Note: Odd means first cycle; even means second cycle. Figure 18: 8- bit YCbCr Output (YCbCr_422_8_8) Notes: 1. Cb Y Cr Y by default. 2. cam_port_paralle l_msb_align=0x0 Table 13: YCbCr Output Modes (c am_port_parallel_msb_align=0x0) Mode Byte Pixel i Pixel i+1 ""Notes" YCbCr_422_8_8 Odd (DOUT[7 :0]) Cbi Cri Data range of 0-255 (Y=16-235 and C=16-240) Even (DOUT [7:0] Yi Yi+1 YCbCr_422_10_10 Odd (DOUT [9:0]) Cbi Cri Data range of 0-1023 (Y=64-940 and C=64-960)" Even (DOUT [9:0]) Yi Yi+1 YCbCr_422_16 Single (D OUT [15:0]) Cbi_Yi Cri_Yi+1 Data range of 0-255 (Y=16-235 and C=16-240) Active Video Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr YC b YC r Image ImageHBl ank HBl ank HBl ank Vertical Blanking YC b YC r Vblank Image Vblank YC b YC r Image YC b YC r YC b YC r YC b YC r YC b YC r Image ImageHBlank HBlank HBlank Cr Cr Cr Line Valid Frame Valid Pixel Clock Data[15:8] Data[7:0] Line Valid Frame Valid Pixel Clock Data[15:8] Data[7:0] Line Valid Frame Valid Pixel Clock Data[15:8] Data[7:0] Porch – 0-255 cycles Line Valid Frame Valid Pixel Clock Data[15:8] Data[7:0] Porch – 0-255 cycles Porch – 0-255 cycles Porch – 0-255 cycles

AP0100CS/D Rev. 6, Pub. 1/16 EN 31 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Output Formatting Figure 19: 10-bit YCbCr Output (YCbCr_422_10_10) Notes: 1. Cb Y Cr Y by default. 2. cam_port_paralle l_msb_align=0x1 Active Video Y Cb Y Cr Y C b Y C r Y Cb Y Cr YC bY C r Image ImageHBlank HBl ank HBl ank Vertical Blanking YC b YC r Vblank Image Vblank YC b Y C r Image Y Cb Y Cr Y Cb Y C r Y Cb Y Cr YC bY C r Image ImageHBlank HBl ank HBl ank Cr Cr Cr Line Valid Frame Valid Pixel Clock Data[5:0] Data[15:6] Line Valid Frame Valid Pixel Clock Data[5:0] Data[15:6] Line Valid Frame Valid Pixel Clock Data[5:0] Data[15:6] Line Valid Frame Valid Pixel Clock Data[5:0] Data[15:6] Porch – 0-255 cycles Porch – 0-255 cycles Porch – 0-255 cycles Porch – 0-255 cycles

AP0100CS HDR: Image Signal Processor (ISP) Output Formatting AP0100CS/D Rev. 6, Pub. 1/16 EN 32 ©Semiconductor Components Industries, LLC,2016. Figure 20: 16-bit YCbCr Output (YCbCr_422_16) Active Video Cb Cr Cb C r Cb Cr Cb C r Cb Cr Cb Cr Cb Cr Cb C r Image ImageHBlank HBl ank HBlank Vertical Blanking CbCr CbCr Vblank Image Vblank CbCr CbCr Image Image ImageHBlank HBl ank HBlank Cr Cr YYYY YYYY YYYY YYYYY Cb Cr Cb Cr Cb Cr Cb C r Cb Cr Cb C r Cb Cr Cb C rCr YY Y Y YYYY YYYY YYYYY YYYY YYYYY Line Valid Frame Valid Pixel Clock Data[7:0] Data[15:8] Line Valid Frame Valid Pixel Clock Data[7:0] Data[15:8] Line Valid Frame Valid Pixel Clock Data[7:0] Data[15:8] Line Valid Frame Valid Pixel Clock Data[7:0] Data[15:0] Porch – 0-255 cycles Porch – 0-255 cycles Porch – 0-255 cycles Porch – 0-255 cycles

AP0100CS/D Rev. 6, Pub. 1/16 EN 33 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Output Formatting Figure 21: Typical CCIR656 Output Data[7:0] Line Valid Frame Valid Field 1 C bYC rY C bYC rY80 1080 1080 1010 80 1080 10 80 10 80 10 Cb Y Cr YFF 00 00 8080 FF 00 00 9D FF 00 00 80 Cb Y Cr Y 80 10 80 10FF 00 00 9D SAV Image EAV SAV Image EAV HBlank HBlank BlankingBlanking Blanking HBlank Data[7:0] Line Valid Frame Valid C bYC rY C bYC rY80 1080 1080 1010 80 1080 10 80 10 80 10 80 10 80 10FF 00 00 8080 FF 00 00 B6 FF 00 00 AB 80 10 80 10 80 10 80 10FF 00 00 B6 SAV Image EAV Blank SAV Blank VBlank EAV blank HBlank HBlank BlankingBlanking Blanking HBlank Pixel Clock Pixel Clock Data[7:0] Line Valid Frame Valid C bYC rY C bYC rY80 1080 1080 1010 80 1080 10 80 10 80 10 Cb Y Cr YFF 00 00 C780 FF 00 00 DA FF 00 00 C7 Cb Y Cr Y 80 10 80 10FF 00 00 DA SAV Image EAV SAV Image EAV HBlank HBlank BlankingBlanking Blanking HBlank Data[7:0] Line Valid Frame Valid C bYC rY C bYC rY80 1080 1080 1010 80 1080 10 80 10 80 10 80 10 80 10FF 00 00 C780 FF 00 00 F1 FF 00 00 EC 80 10 80 10 80 10 80 10FF 00 00 F1 SAV Image EAV Blank SAV Blank VBlank EAV blank HBlank HBlank BlankingBlanking Blanking HBlank Pixel Clock Pixel Clock Field 2 Data[15:8] 00 Data[15:8] 00 Data[15:8] 00 Data[15:8] 00

AP0100CS HDR: Image Signal Processor (ISP) Output Formatting AP0100CS/D Rev. 6, Pub. 1/16 EN 34 ©Semiconductor Components Industries, LLC,2016. Figure 22: Typical CVBS Output (NTSC/PAL) Line Valid In Frame Valid In Field 1 / 3 Pre-Equalisation Pulses Post-Equalising PulsesSerration Pulses Video 1 2 3 4 5 6 7 8 9 Line Valid In Frame Valid In Field 2 / 4 Pre-Equalisation Pulses Post-Equalising PulsesSerration Pulses Video 1 2 3 4 5 6 7 8 9 Line Valid to First Field Latency ~= STE Latency + 1 Field

AP0100CS/D Rev. 6, Pub. 1/16 EN 35 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Bayer Modes Bayer Modes Bayer output modes are only available in progressive output mode before STE. The data ordering for the ALTM Bayer output modes for AP0100CS are shown in Table 14. Table 14 and Table 15 show LSB aligned data; it is possible using register setting to obtain MSB aligned data. The data ordering for the Bayer output modes for AP0100CS are shown in Table 15. Note: Bayer_12 can be selected by setting cam_mo de_select = 0x1 and requesting a Change-Config operation. Sensor Embedded Data The AP0100CS is capable of passing sensor embedded data in Bayer output mode only. The AP0100CS Statistics are available through the serial interface. Refer to the developer guide for details. Table 14: ALTM Bayer Output Modes Mode Byte

2 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ALTM_Bayer_10 Single 0 0 0 0 0 0 D9 D98 D7 D6 D5 D4 D3 D2 D1 D0 A L T M _ B a y e r _ 1 2 S i n g l e 0000 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 Table 15: Bayer Output Modes Mode Byte D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Notes Bayer_1 Singl e

0000 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 R A W B a y e r

AP0100CS HDR: Image Signal Processor (ISP) Spatial Transform Engine (STE) AP0100CS/D Rev. 6, Pub. 1/16 EN 36 ©Semiconductor Components Industries, LLC,2016. Spatial Transform Engine (STE) A spatial transform is defined as a transform in which some pixels are in different posi- tions within the input and output pictures. Examples include zoom, lens distortion correction, turn, and rotate. STE is a fully programmable engine which can perform spatial transforms and eliminates the need for an expensive DSP for image correction. Lens Distortion Correction Automotive backup cameras typically feature a wide FOV lens so that a single camera mounted above the center of the rear bumper can present the driver with a view of all potential obstacles immediately behind the full width of the vehicle. Lenses with a wide field of view typically exhibit at least a noticeable amount of barrel distortion. Barrel distortion is caused by a reduction in object magnification the further away from the optical axis. For the image to appear natural to the driver, the AP0100CS corrects this barrel distor- tion and reprocesses the image so that the resulting distortion is much smaller. This is called distortion correction. Distortion correction is the ability to digitally correct the lens barrel distortion and to provide a natural view of objects. In addition, with barrel distortion one can adjust the perspective view to enhance the visibility by virtually elevating the point of viewing objects. Pan, Tilt, Zoom and Rotate Using the STE it is possible to implement image transformations like Pan, Tilt, Zoom and Rotate. Figure 23: Uncorrected Image

AP0100CS/D Rev. 6, Pub. 1/16 EN 39 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Overlay Capability Figure 27: Overlay Data Flow Note: These images are not actually rendered, but show conceptual objects and object blending. Off-screen buffer Overlay buffers: 4KB each Decompress Blend and Overlay NVM Bitmaps - compressed

AP0100CS/D Rev. 6, Pub. 1/16 EN 43 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Slave Two-Wire Serial Interface (CCIS) Slave Two-Wire Serial Interface (CCIS) The two-wire slave serial interface bus enables read/write access to control and status registers within the AP0100CS. The interface protocol uses a master/slave model in which a master controls one or more slave devices. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements, as follows:  a start or restart condition  a slave address/da ta direction byte  a 16-bit register address  an acknowledge or a no-acknowledge bit d a t a b y t e s  a stop condition The bus is idle when both S CLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. The SADDR pin is used to select between two different addresses in case of conflict with another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave address is 0xBA. See Table 16 below. The user can change the slave address by changing a register value.Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each S CLK clock period. SDATA can change when SCLK is low and must be stable while SCLK is HIGH. Table 16: Two-Wire Interface ID Address Switching SADDR Two-Wire Interface Address ID 00 x 9 0 10 x B A

AP0100CS HDR: Image Signal Processor (ISP) Protocol AP0100CS/D Rev. 6, Pub. 1/16 EN 44 ©Semiconductor Components Industries, LLC,2016. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default slave addresses used by the AP0100CS are 0x90 (write address) and 0x91 (read address). Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can be selected by asserting the S ADDR input signal. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. The protocol used is outside the scope of the two-wire serial interface specification. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl- edge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA low during the SCLK clock period following a data transfer. A no-acknowledge bit is used to termi- nate a read sequence. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Typical Operation A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0” indicates a WRITE and a “1” indicates a READ. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master will then transfer the 16-bit data, as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, just as in the write request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. The master generates an acknowledge bit after each 8- bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.

AP0100CS/D Rev. 6, Pub. 1/16 EN 47 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Protocol Sequential WRITE, Start at Random Location This sequence (Figure 37) starts in the same way as the single WRITE to random location (Figure 36). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until “L” bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 37: Sequential WRITE, Start at Random Location Slave Address 0S A Reg Address[15:8] Write Da ta A Reg Addr ess[7 :0] A Write Data Previous Re g Addre ss, N Reg Address, M M+1 M+2 M+1 M+3 A AA Write Data Write Data M+L -2 M+L -1 M+L A A P Write Da ta (15:8 ) Write Da ta (7:0) Write Da ta (15:8 ) A Write Da ta (7:0)A AA A Write Da ta A Write Da ta (15:8) A Write Da ta (7:0) A Write Da taWrite Da ta (15:8) A Write Da ta (7:0)

AP0100CS HDR: Image Signal Processor (ISP) Protocol AP0100CS/D Rev. 6, Pub. 1/16 EN 48 ©Semiconductor Components Industries, LLC,2016. Device Configuration After power is applied and the device is out of reset (either the power on reset, hard or soft reset), it will enter a boot sequence to configure its operating mode. There are essen- tially three configuration modes: Flash/EEPROM Config, Auto Config, and Host Config. The AP0100CS firmware supports a System Configuration phase at start-up. This consists of three sub-phases of execution: Flash detection, then one of: a. Flash Config b. Auto Config c. Host Config The System Configuration phase is entered immediately following power-up or reset. Then the firmware performs Flash Detection. Flash Detection attempts to detect the presence of an SPI Flash or EEPROM device:  If no device is detected, the firmware then samples the SPI_SDI pin state to determine the next mode: – If SPI_SDI is low, then it enters the Host-Config mode. – If SPI_SDI is high, then it enters the Auto-Config mode.  If a device is detected, the firmware switches to the Flash-Config mode. In the Flash-Config mode, the firmware interrogates the device to determine if it contains valid configuration records:  If no records are detected, then the firmware enters the Auto-Config mode.  If records are detected, the firmware processes them. By default, when all Flash records are processed the firmware switches to the Host-Config mode. However, the records encoded into the Flash can optionally be used to instruct the firmware to proceed to auto-config, or to start streaming (via a Change-Config). In the Host-Config mode, the firmware performs no configuration, and remains idle waiting for configuration and commands from the host. The System Configuration phase is effectively complete and the AP0100CS will take no actions until the host issues commands. The Auto-Config mode uses the GPIO [5..2] pins to configure the operation of the device, such as video format and pedestal (see Table 18, “GPIO Bit Descriptions in Auto-Config,” on page 49). After Auto-Config completes the firmware switches to the Change-Config mode.

AP0100CS/D Rev. 6, Pub. 1/16 EN 49 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Protocol Supported SPI Devices Table 17 lists supported EEPROM/Flash devices. Devices not compatible will require a firmware patch. Contact ON Semiconductor for additional support. Notes: 1. Has been obsoleted. Table 17: SPI Flash Devices Manufacturer Device Type Size Autodetected ManuID Atmel AT26DF081A Flash 1Mbyte Yes 0x1f4501 Atmel AT25DF161 Flash 2Mbyte Yes 0x1f4602 Sanyo1 LE25FW806 Flash 1Mbyte Yes 0x622662 ST M25P05A Flash 64kbyte Yes 0x202010 ST M25P16 Flash 2Mbyte Yes 0x202015 ST M95040 EEPROM 512byte No 0x20ffff ST M95020 EEPROM 256byte No 0x20ffff ST M95010 EEPROM 128byte No 0x20ffff ST M95M01 EEPROM 128kbyte No 0x20ffff Microchip M25AA080 EEPRO M 1kbyte No 0x29ffff Microchip M25LC080 EEPROM 1kbyte No 0x29ffff Table 18: GPIO Bit Descriptions in Auto-Config GPIO[5] GPIO[4] GPIO[3] GPIO[2] Low (“0”) Normal Normal NTSC No pedestal High (“1”) Vertical Flip Ho rizontal mirror PAL Pedestal

AP0100CS HDR: Image Signal Processor (ISP) Host Command Interface AP0100CS/D Rev. 6, Pub. 1/16 EN 50 ©Semiconductor Components Industries, LLC,2016. Host Command Interface The AP0100CS has a mechanism to write higher level commands, the Host Command Interface (HCI). Once a command has been written through the HCI, it will be executed by on chip firmware and the results are reported back. EEPROM or Flash memory is also available to store commands for later execution. Figure 38: Interface Structure Command Flow The host issues a command by writing (through the two wire interface) to the Command Register. All commands are encoded with bit 15 set, which automatically generates the ‘host command’ (doorbell) interrupt to the microprocessor. Assuming initial conditions, the host first writes the command parameters (if any) to the Parameters Pool (in the Command Handler’s shared-variable page), then writes the command to Command Register. The firmware’s interrupt handler is invoked, which immediately copies the Command Register contents. The interrupt handler then signals the Command Handler task to process the command. Host Command to FW Response from FW 15 0bit 0 command registerAddr 0x40 Addr 0xFC00 Addr 0xFC0E Addr 0xFC02 Addr 0xFC04 Addr 0xFC06 Addr 0xFC08 Addr 0xFC0A Addr 0xFC0C door bell 15 0bit Parameter 0 Parameter 7 cmd_handler_params_pool_0 cmd_handler_params_pool_1 cmd_handler_params_pool_2 cmd_handler_params_pool_3 cmd_handler_params_pool_4 cmd_handler_params_pool_5 cmd_handler_params_pool_6 cmd_handler_params_pool_7

AP0100CS/D Rev. 6, Pub. 1/16 EN 51 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Host Command Interface If the host wishes to determine the outcome of the command, it must poll the Command Register waiting for the doorbell bit to become cleared. This indicates that the firmware completed processing the command. The contents of the Command Register indicate the command’s result status. If the command generated response parameters, the host can now retrieve these from the Parameters Pool. The host must not write to the Parameters Pool, nor issue another command, until the previous command completes. This is true even if the host does not care about the result of the previous command. It is strongly recommended that the host tests that the door- bell bit is clear before issuing a command. Synchronous Command Flow The typical ‘flow’ for synchronous commands is: 1. The host issues a ‘request’ command to perform an operation. 2. The registered command handler is invo ked, validates the command parameters, then performs the operation. The handler returns the command result status to indi- cate the result of the operation. 3. The host retrieves the command result va lue, and any associated command response parameters. Asynchronous Command Flow The typical ‘flow’ for asynchronous commands is: 1. The host issues a ‘request’ command to start an operation. 2. The registered command handler is invo ked, validates and copies the command parameters, then signals a separate task to perform the operation. The handler returns the ENOERR return value to indicate the command was acceptable and is in progress. 3. The host retrieves the command return value – if it is not ENOERR the host knows that the command was not accepted and is not in progress. 4. Subsequently, the host issu es an appropriate ‘get status’ command to both poll whether the command has completed, and if so, retrieve any associated response parameters. 5. The registered command handler is invoke d, determines the state of the command (via shared variables with the processing task), and returns either ‘EBUSY’ to indicate the command is still in progress, or it returns the result status of the command. 6. The host must re-issue the ‘get status’ command until it does not receive the EBUSY response. Asynchronous commands exist to allow the Host to issue multiple commands to the various subsystems without having to wait for each command to complete. This prevents the host command interface from being blocked by a long-running command. Therefore, each asynchronous command has a “Get Status” (or similar) command to allow the Host to determine when the asynchronous command completes.

AP0100CS HDR: Image Signal Processor (ISP) Start-up Host Command Lock-out AP0100CS/D Rev. 6, Pub. 1/16 EN 52 ©Semiconductor Components Industries, LLC,2016. Start-up Host Command Lock-out The AP0100CS firmware implements an internal Host Command ‘lock’. At start-up, the firmware obtains this lock, which prevents the Host from successfully issuing a host command. All host commands will be rejected with EBUSY until the lock is freed. The firmware releases the Host Command lock when it completes its start-up configura- tion processing. The time to do this is dependent upon the configuration mechanism. It is recommended that the Host poll the device with the System Manager Get State command until ENOERR is returned. Once the host can send serial commands it should perform the following sequence. 1. POLL command_register[15] until it clears (This is called the doorbell bit). 2. Continuously issue the SYSMGR_GET_STATE command (0x8101) until the result sta- tus is not EBUSY Below is some pseudocode that a host could use to implement the above sequence: def systemWaitReadyFollowingReset(numRetries=10): """API function: waits for the system to be ready following reset (or powerup) - first wait for the doorbell bit to clear - this indicates that the device can accept host commands. - then wait until the system has completed its configuration phase; the system is ready when the SYSMGR_GET_STATE command does not return EBUSY. - note the time for the system to be ready is dependent upon the active system configuration mode. - numRetries is the number of retries before timing-out - returns result status code """ # Wait for doorbell bit to clear (indicates device can receive host commands) retries = numRetries while (0 != retries): if (reg.COMMAND_REGISTER.DOORBELL.uncached_value == 0): break # ready to receive commands retries -= 1 if (0 == retries): # device failed to respond in time return printError(ResultStatus.EIO, 'systemWaitReadyFollowingReset failed (doorbell failed to clear)') # Wait for the System Manager to complete the System Configuration phase retries = numRetries while (0 != retries): res, currentState = sysmgrGetState() if (ResultStatus.ENOERR == res): break # we're done if (ResultStatus.EBUSY != res): return printError(res, 'systemWaitReadyFollowingReset failed (sysmgrGetState failed)') retries -= 1 if (0 == retries): # device failed to respond in time return printError(ResultStatus.EAGAIN, 'systemWaitReadyFollowingReset failed (device busy)') return res

AP0100CS/D Rev. 6, Pub. 1/16 EN 53 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Multitasking Multitasking The AP0100CS firmware is multitasking; therefore note that it is possible for an inter- nally requested command to be in-progress when the Host issues a command. In these circumstances, the Host command is immediately rejected with EBUSY. The Host should reissue the command after a short interval. Host Commands Overview The AP0100CS supports a number of functional modules or processing subsystems. Each module or subsystem exposes commands to the host to control and configure its operation. Command Parameters Command parameters are written to the Parameters Pool shared-variables by the host prior to invoking the command. Similarly, any Command Response parameters are also written back to the Parameters Pool by the firmware. Result Status Codes Table 19 shows the result status codes that are written by the Command Handler to the Host Command register, in response to a command. Note: Any unrecognized host comman ds will be immediately rejected by the Command Handler, with result status code ENOSYS. Table 19: Result Status Codes Value Mnemonic Typical Interpretation – each command may re-interpret 0x00 ENOERR No error – command was successful 0x01 ENOENT No such entity 0x02 EINTR Operation interrupted 0x03 EIO I/O failure 0x04 E2BIG Too big 0x05 EBADF Bad file/handle 0x06 EAGAIN Would-block, try again 0x07 ENOMEM Not enough memory/resource 0x08 EACCES Permission denied 0x09 EBUSY Entity busy, cannot support operation 0x0A EEXIST Entity exists 0x0B ENODEV Device not found 0x0C EINVAL Invalid argument 0x0D ENOSPC no space/resource to complete 0x0E ERANGE parameter out-of-range 0x0F ENOSYS operation not supported 0x10 EALREADY already requested/exists

AP0100CS HDR: Image Signal Processor (ISP) Summary of Host Commands AP0100CS/D Rev. 6, Pub. 1/16 EN 54 ©Semiconductor Components Industries, LLC,2016. Summary of Host Commands Table 20 on page 54 through Table 31 on page 56 show summaries of the host commands. The commands are divided into the following sections:  System Manager O v e r l a y G P I O  Flash Manager S T E  Sequencer  Patch Loader M i s c e l l a n e o u s  Calibration Stats Following is a summary of the Host Interface commands. The description gives a quick orientation. The “Type” column shows if it is an asynchronous or synchronous command. For a complete list of all commands including parameters, consult the Host Command Interface Specification document. Table 20: System Manager Host Command System Manager Host Command Value Type Description Set State 0x8100 Asynchronous Request the system enter a new state Get State 0x8101 Synchronous Get the current state of the system Config Power Management 0x8102 Synchronous Configures the power state of the system Table 21: Overlay Host Commands Overlay Host Command Value Type Description Enable Overlay 0x8200 Synchronous Enable or disable the overlay subsystem Get Overlay State 0x8201 Synchronous Retrieves the state of the overlay subsystem Set Calibration 0x8202 Synchronous Set the calibration offset Set Bitmap Property 0x8203 Synchronous Set a property of a bitmap Get Bitmap Property 0x8204 Synchronous Get a property of a bitmap Set String Property 0x8205 Synchronous Set a property of a character string Load Buffer 0x8206 Asynchronous Load an overlay buffer with a bitmap (from Flash) Load Status 0x8207 Synchronous Retrieve status of an active load buffer operation Write Buffer 0x8208 Synchronous Write directly to an overlay buffer Read Buffer 0x8209 Synchronous Read directly from an overlay buffer Enable Layer 0x820A Synchronous Enable or disable an overlay layer Get Layer Status 0x820B Synchronous Retrieve the status of an overlay layer Set String 0x820C Synchronous Set the character string Get String 0x820D Synchronous Get the current character string Load String 0x 820E Asynchronous Load a character string (from Flash)

AP0100CS/D Rev. 6, Pub. 1/16 EN 55 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Summary of Host Commands Table 22: STE Manager Host Commands STE Manager Host Command Value Type Description Config 0x8310 Synchronous Configure using the default NTSC or PAL configuration stored in ROM Load Config 0x8311 Asynchronous Load a configuration from SPI NVM to the configuration cache Load Status 0x8312 Synchronous Get status of a Load Config request Write Config 0x8313 Synchronous Write a configuration (via CCIS) to the configuration cache Table 23: GPIO Host Commands GPIO Host Command Value Type Description Set GPIO Property 0x8400 Synchronous Set a property of one or more GPIO pins Get GPIO Property 0x8401 Synchronous Re trieve a property of a GPIO pin Set GPIO State 0x8402 Synchronous Set the state of a GPO pin or pins Get GPIO State 0x8403 Synchronous Ge t the state of a GPI pin or pins Set GPI Association 0x8404 Synchronous Associate a GPI pin state with a Command Sequence stored in SPI NVM Get GPI Association 0x8405 Synchronous Retrieve a GPIO pin association Table 24: Flash Ma nager Host Command Flash Mgr Host Command Value Type Description Get Lock 0x8500 Asynchronous Reques t the Flash Manager access lock Lock Status 0x8501 Synchronous Retrieve the status of the access lock request Release Lock 0x8502 Synchronous Rele ase the Flash Manager access lock Config 0x8503 Synchronous Configure the Fl ash Manager and underlying SPI NVM subsystem Read 0x8504 Asynchronous Re ad data from the SPI NVM Write 0x8505 Asynchronous Write data to the SPI NVM Erase Block 0x8506 Asynchronous Erase a block of data from the SPI NVM Erase Device 0x8507 Asynchronous Erase the SPI NVM device Query Device 0x8508 Asynchronous Query device-specific information Status 0x8509 Synchronous Obtain status of current asynchronous operation Config Device 0x850A Synchronous Configure the attached SPI NVM device Table 25: Sequencer Host Command Sequencer Host Command Value Type Description Refresh 0x8606 Asynchronous Refresh the automatic image processing algorithm configuration Refresh Status 0x8607 Synchronous Retrieve the status of the last Refresh operation Table 26: Patch Loader Host Command Patch Loader Host Command Value Type Description Load Patch 0x8700 Asynchronous Load a patch from SPI NVM and automatically apply Status 0x8701 Synchronous Get status of an active Load Patch or Apply Patch request

AP0100CS HDR: Image Signal Processor (ISP) Summary of Host Commands AP0100CS/D Rev. 6, Pub. 1/16 EN 56 ©Semiconductor Components Industries, LLC,2016. Apply Patch 0x8702 Asynchronous Apply a patch (already located in Patch RAM) Reserve RAM 0x8706 Synchronous Reserve RAM to contain a patch Table 27: Miscellaneous Host Command Miscellaneous Host Command Value Type Description Invoke Command Seq 0x8900 Synchronous Invoke a sequence of commands stored in SPI NVM Config Command Seq Processor 0x8901 Synchronous Configures the Command Sequence processor Wait for Event 0x8902 Synchronous Wait for a system event to be signalled Table 28: Calibration Stats Host Commands Calibration Stats Host Command Value Type Description Calib Stats Control 0x8B00 Asynchronous Start statistics gathering Calib Stats Read 0x8B01 Synchronous Read the results back Table 29: Event Monitor Host Command Event Monitor Host Command Value Type Description Event Monitor Set Association 0x8C00 Synchronous Associate an system event with a Command Sequence stored in NVM Event Monitor Get Association 0x8C01 Synchronous Retrieve an event association Table 30: CCI Manager Host Commands CCI Manager Host Command Value Type Description Get Lock 0x8D00 Asynchronous Request the CCI Manager access lock Lock Status 0x8D01 Synchronous Retrieve the status of the access lock request Release Lock 0x8D02 Synchronous Release the CCI Manager access lock Config 0x8D03 Synchronous Configure the CCI Manager and underlying CCI subsystem Set Device 0x8D04 Synchronous Set the target CCI device address Read 0x8D05 Asynchronous Read one or more bytes from a 16-bit address Write 0x8D06 Asynchronous Write one or more bytes to a 16-bit address Write Bitfield 0x8D07 Asynchronous Read-modify-write 16-bit data to a 16-bit address CCI Status 0x8D08 Synchronous Obtain status of current asynchronous operation Table 31: Sensor Ma nager Host Commands Sensor Manager Host Command Value Type Description Discover Sensor 0x8E00 Synchronous Discover sensor Initialize Sensor 0x8E01 Synchronous Initialize attached sensor Table 26: Patch Loader Host Command Patch Loader Host Command Value Type Description

AP0100CS HDR: Image Signal Processor (ISP) Usage Modes AP0100CS/D Rev. 6, Pub. 1/16 EN 58 ©Semiconductor Components Industries, LLC,2016. In this configuration all settings are communicated to the AP0100CS and sensor through the microcontroller. Figure 42: Host Mode 8/16bit μC two-wireSystem Bus AP0100CS + image sensor

AP0100CS/D Rev. 6, Pub. 1/16 EN 59 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Usage Modes Caution Stresses greater than those listed in Table 32 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabil- ity. Table 32: Absolute Maximum Ratings Parameter Rating Unit Min Max Digital power (1.8V) -0.3 4.95 V Host I/O power (2.5V,3.3V) 2.25 5.4 V Sensor I/O power (1.8V, 2.8V) 1.7 5.4 V Digital DAC power 1.1 2.5 V PLL power 1.1 2.5 V Digital core power 1.1 2.5 V OTPM power (2.5V, 3.3V) 2.25 5.4 V DC Input Voltage -0.3 V DDIO_*+0.3 V DC Output Voltage -0.3 V DDIO_*+0.3 V Storage temperature -50 150 °C

AP0100CS HDR: Image Signal Processor (ISP) Usage Modes AP0100CS/D Rev. 6, Pub. 1/16 EN 60 ©Semiconductor Components Industries, LLC,2016. Table 33: Electrical Characteristics and Operating Conditions Parameter Condition Min Typ Max Unit Supply input to on-chip regulator (VDD_REG) 1.62 1.8 1.98 V Host IO voltage (VDDIO_H) 2.25 2.5/3.3 3.6 V Sensor IO voltage (VDDIO_S) 1.7 1.8/2.8 3.1 V Core voltage (VDD)1 . 0 8 1 . 2 1 . 3 2 V PLL voltage (VDD_PLL) 1.08 1.2 1.32 V DAC digital voltage (VDD_DAC) 1.08 1.2 1.32 V DAC analog voltage (VDDA_DAC) 3 3.3 3.6 V HiSPi PHY votlage (VDD_PHY) 2.3 2.8 3.1 V OTPM power supply (VDDIO_OTPM) 2.25 2.5/3.3 3.6 V Functional operating temperature (ambient - TA) -30 70 °C Storage temperature -55 150 °C

AP0100CS/D Rev. 6, Pub. 1/16 EN 61 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Usage Modes Notes: 1. V IH/VIL restrictions apply. 2. This is applicable only a when th e PLL is bypassed. When the PLL is being used then the user should ensure that VIH/VIL is met. Notes: 1. VIL and VIH have min/max limita tions specified by absolute ratings. 2. Excludes pins that have internal PU resistors. Table 34: AC Electrical Characteristics Default Setup Conditions: fEXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V, VDDA_DAC=3.3V, VDD_DAC=1.2V; TA = 25°C unless otherwise stated Symbol Parameter Conditions Min Typ Max Unit Notes fEXTCLK External clock frequency 6 30 MHz 1 tR External input clock rise time 10%-90% V DDIO_H – 2 5 ns 2 tF External input clock fall time 90%-10% V DDIO_H – 2 5 ns 2 DEXTCLK External input clock duty cycle 40 50 60 % tJITTER External input clock jitter – 500 – ps fPIXCLK Pixel clock frequency (one-clock/pixel) 6 74.125 MHz Pixel clock frequency (two-clocks/pixel) 6 84 tRPIXCLK Pixel clock rise time (10-90%) C LOAD=35pf – 2 5 ns tFPIXCLK Pixel clock fall time (10-90%) C LOAD=35pf – 2 5 ns tPD PIXCLK to data valid – 1 5 ns tPFH PIXCLK to FV HIGH – 1 5 ns tPLH PIXCLK to LV HIGH – 1 5 ns tPFL PIXCLK to FV LOW – 1 5 ns tPLL PIXCLK to LV LOW – 1 5 ns Table 35: DC Electric al Characteristics Symbol Parameter Condition Min Max Unit Notes VIH Input HIGH voltage V DDIO_H or VDDIO_S * 0.8 – V 1 VIL Input LOW voltage – V DDIO_H or VDDIO_S * 0.2 V 1 IIN Input leakage current V IN= 0V or VIN = VDDIO_H or VDDIO_S 10 A 2 VOH Output HIGH voltage V DDIO_H or VDDIO_S* 0.80 – V VOL Output LOW voltage – V DDIO_H or VDDIO_S * 0.2 V Table 36: Video DAC Elec trical Characteristics Default Setup Conditions: fEXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V, VDDA_DAC=3.3V, VDD_DAC=1.2V; TA = 25°C unless otherwise stated Parameter Symbol Min Typ Max Unit Comments DC Accuracy Differential Nonlinearity DNL ±1 LSB Integral Nonlinearity INL ±3 LSB Load Capacitance CLOAD 10 pF At maximum output current

AP0100CS HDR: Image Signal Processor (ISP) Usage Modes AP0100CS/D Rev. 6, Pub. 1/16 EN 62 ©Semiconductor Components Industries, LLC,2016. Figure 43: Frame_Sync (Int erlaced Operation) Diagram Offset Error OER ±1 % FS For differental output only Gain Error DGER ±2 % FS Absolute Gain Error GER ±5 % FS Table 37: Frame_Sync (Inter laced Operation) Parameters Parameter Name Conditions Min Typ Max Unit T_FRAME_SYNC T_FRAME_SYNC 3 EXTCLK cycles T_RESYNC T_RESYNC NTSC 100 ms T_RESYNC T_RESYNC PAL 120 ms Table 36: Video DAC Elec trical Characteristics Default Setup Conditions: fEXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V, VDDA_DAC=3.3V, VDD_DAC=1.2V; TA = 25°C unless otherwise stated Parameter Symbol Min Typ Max Unit Comments

AP0100CS/D Rev. 6, Pub. 1/16 EN 63 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Usage Modes Figure 44: Frame_Sync (Pro gressive Operation) Diagram Table 38: Tr igger Timing Parameter Name Conditions Min Typ Max Unit FRAME_SYNC to FV_OUT t FRMSYNC_FVH 8 lines+ exposure time + sensor delay – – Lines FRAME_SYNC to TRIGGER_OUT tTRIGGER_PROP – – 9 ns tFRAME_SYNC t FRAMESYNC 3 – – EXTCLK cycles

AP0100CS HDR: Image Signal Processor (ISP) Usage Modes AP0100CS/D Rev. 6, Pub. 1/16 EN 64 ©Semiconductor Components Industries, LLC,2016. NTSC Signal Parameters Notes: 1. Black and white levels are referenced to the blanking level. 2. NTSC convention standardized by the IRE (1 IRE = 7.14mV). 3 . D A C r e f=3 . 7 4 k, load = 37.5 Table 39: NTSC Signal Parameters Default Setup Conditions: fEXTCLK= 27 MHz, VDD_REG = 1.8V, VDD_IO_S = 1.8V, VDDA_DAC= 3.3V, VDDIO_OTPM=2.5V, VDD_PHY = 2.5V Parameter Min Typ Max Units Notes Line Frequency 15734.25 15734.27 15734.28 Hz Field Frequency 59.94 59.94 59.94 Hz Sync Rise Time 111 148 222 ns Sync Fall Time 111 148 222 ns Sync Width 4.60 4.74 4.80 s S y n c L e v e l 3 94 04 1 I R E 2 Burst Level 36 40 44 IRE 2 Sync to Setup (with pedestal off) 9.2 9.5 10.3 s Sync to Burst Start 4.71 5.3 5.71 s Front Porch 1.27 1.7 2.22 s Black Level 5 7.5 10 IRE 1, 2, 3 White Level 90 100 110 IRE 1, 2, 3

AP0100CS/D Rev. 6, Pub. 1/16 EN 65 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Usage Modes Figure 45: Video Timing Table 40: Video Timing: Specific ation from Rec. ITU-R BT.470 Signal NTSC

27 MHz

27 MHz Units

A H Period 63.556 64.00 s B Hsync to burst 4.71 to 5.71 5.60 ± 0.10 s C burst 2.23 to 3.11 2.25 ± 0.23 s D Hsync to Signal 9.20 to 10.30 10.20 ± 0.30 s E Video Signal 2.655 ±0.20 52 +0, -0.3 s G Hsync Period 4.70 ± 0.10 4.70 ± 0.20 s H Sync rising/falling edge 0.25 0.20 ±0.10 s H F A H DE B C G J K

AP0100CS HDR: Image Signal Processor (ISP) Usage Modes AP0100CS/D Rev. 6, Pub. 1/16 EN 66 ©Semiconductor Components Industries, LLC,2016. Figure 46: Equalizing Pulse Table 41: Equalizing Pulse: Specification from Rec. ITU-R BT.470 Signal NTSC I H/2 Period 31.778 32.00 s J Pulse width 2.30 ± 0.10 2.35 ± 0.10 s K Pulse rising/falling edge 0.25 0.25 ± 0.05 s L Signal to pulse 1.50 ± 0.10 3.0 ± 2.0 s L J I K K

AP0100CS/D Rev. 6, Pub. 1/16 EN 67 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Usage Modes Figure 47: V Pulse Table 42: V Pulse: Specification from Rec. ITU-R BT.470 Signal NTSC M H/2 Period 31.778 32.00 s N Pulse width 27.10 (nominal) 27.30 ± 0.10 s O V pulse interval 4.70 ± 0.10 4.70 ± 0.10 s P Pulse rising/falling edge 0.25 0.25 ± 0.05 s Table 43: Standby Current Consumption Default Setup Conditions: fEXTCLK = 27 MHz, VDD_REG=1.8V; VDDIO_H not included in measurement VDDIO_S= 1.8V, VDDA_DAC=3.3V, VDDIO_OTPM=2.5V, VDD_PHY=2.5V, TA = 70°C unless otherwise stated Parameter Condition Typ Max Unit Total standby current when asserting the STANDBY signal 3.2 mA 6.9 mW Total standby current fEXTCLK = 27 MHz 3.5 mA 7.6 mW N M O P P

AP0100CS HDR: Image Signal Processor (ISP) Usage Modes AP0100CS/D Rev. 6, Pub. 1/16 EN 68 ©Semiconductor Components Industries, LLC,2016. Notes: 1. R_DAC_POS=75 , R_DAC_NEG=37.5, R_DAC_REF= 3.74k Table 44: Operating Current Consumption Default Setup Conditions: fEXTCLK = 27 MHz, VDD_REG=1.8V; VDDIO_H not included in measurement VDDIO_S= 1.8V, VDDA_DAC=3.3V, VDDIO_OTPM=2.5V, VDD_PHY=2.5V, TA = 70°C unless otherwise stated Symbol Conditions Min Typ Max Unit VDD_REG 1.62 1.8 1.98 V VDDIO_H=2.5V 2.25 2.5 2.75 V VDDIO_H=3.3V 3 3.3 3.6 V VDDIO_S=1.8V 1.7 1.8 1.9 V VDDIO_S=2.8V 2.5 2.8 3.1 V VDDIO_OTPM=2.5V 2.25 2.5 2.75 V VDDIO_OTPM=3.3V 3 3.3 3.6 V VDDA_DAC 3 3.3 3.6 V VDD_PHY 2.3 2.8 3.1 V IDD_REG NTSC HiSPi 12-bit 63.7 mA NTSC HiSPi 14-bit 63.6 mA NTSC 64.1 mA PAL 59.5 mA I DDIO_S NTSC HiSPi 12-bit 3.2 mA NTSC HiSPi 14-bit 3.2 mA NTSC 3.3 mA PAL 3.3 mA I DDIO_OTPM NTSC HiSPi 12-bit 0.1 mA NTSC HiSPi 14-bit 0.1 mA NTSC 0.1 mA PAL 0.1 mA IDDA_DAC NTSC HiSPi 12-bit 1, 2 19.54 mA NTSC HiSPi 14-bit 1, 2 19.54 mA NTSC 1, 2 19.54 mA PAL 1, 2 19.54 mA I DD_PHY NTSC HiSPi 12-bit 0.3 mA NTSC HiSPi 14-bit 0.3 mA NTSC 0.0 mA PAL 0.0 mA Total power consumption NTSC HiSPi 12-bit 185.66 mW NTSC HiSPi 14-bit 185.56 mW NTSC 185.56 mW PAL 177.46 mW

AP0100CS/D Rev. 6, Pub. 1/16 EN 69 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Usage Modes Table 45: Inrush Current Supply Voltage Max Current (mA) AVDD 1.8 240 VDDIO_H 2.5/3.3 260 VDDIO_S 1.8 15 VDDIO_S 2.8 55 VDDA_DAC 3.3 270 VDDIO_OTPM 2.5/3.3 180

AP0100CS HDR: Image Signal Processor (ISP) Two-Wire Serial Register Interface AP0100CS/D Rev. 6, Pub. 1/16 EN 70 ©Semiconductor Components Industries, LLC,2016. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 48 and Table 46. Figure 48: Slave Two Wire Seri al Bus Timing Parameters (CCIS) 2. A device must internally provide a ho ld time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 3. The maximum t HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 4. Cb = total capacitance of one bus line in pF. The electrical characteristics of the master two-wire serial register interface (M_S CLK, M_SDATA) are shown in Figure 49 and Table 47. Table 46: Slave Two-Wire Serial Bus Characteristics (CCIS) Default Setup Conditions: fEXTCLK = 27 MHz; VDDIO_H = VDD_OTPM = 2.8V; VDD_REG = VDDIO_S = 1.8V; VDDA_DAC= 3.3V; VDD_DAC = 1.2V; TA = 25°C unless otherwise stated Parameter Symbol Standard-Mode Fast-Mode UnitMin Max Min Max SCLK Clock Frequency f SCL 0 100 0 400 KHz Hold time (repeated) START condition. After this period, the first clock pulse is generated t HD;STA 4.0 - 0.6 - s LOW period of the SCLK clock t LOW 4.7 - 1.3 - s HIGH period of the SCLK clock t HIGH 4.0 - 0.6 - s Set-up time for a repeated START condition t SU;STA 4.7 - 0.6 - s Data hold time t HD;DAT 02 3.45 3 00 . 9 3 s Data set-up time t SU;DAT 250 - 100 - ns Rise time of both SDATA and SCLK signals (10-90%) t r - 1000 20 + 0.1Cb 4 300 ns Fall time of both SDATA and SCLK signals (10-90%) t f - 300 20 + 0.1Cb 4 300 ns Set-up time for STOP condition t SU;STO 4.0 - 0.6 - s Bus free time between a STOP and START condition tBUF 4.7 - 1.3 - s Capacitive load for each bus line Cb - 400 - 400 pF Serial interface input pin capacitance C IN_SI - 3.3 - 3.3 pF SDATA max load capacitance C LOAD_SD - 30 - 30 pF SDATA pull-up resistor R SD 1.5 4.7 1.5 4.7 K  S Sr tSU;STOtSU;STAtHD;STA tHIGH tLOW tSU;DAT tHD;DAT tf SDATA SCLK P S tBUFtr tftr tHD;STA

AP0100CS/D Rev. 6, Pub. 1/16 EN 71 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Two-Wire Serial Register Interface Figure 49: Master Two Wire Seri al Bus Timing Parameters (CCIM) 2. A device must internally provide a hold time of at least 300 ns for the M_SDATA signal to bridge the undefined region of the falling edge of M_SCLK. 3. The maximum t HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the M_SCLK signal. 4. Cb = total capacitance of one bus line in pF. Table 47: Master Two- Wire Serial Bus Characteristics (CCIM) Default Setup Conditions: fEXTCLK = 27 MHz; VDDIO_H = VDD_OTPM = 2.8V; VDD_REG = VDDIO_S = 1.8V; VDDA_DAC= 3.3V; VDD_DAC = 1.2V; TA = 25°C unless otherwise stated Parameter Symbol Standard-Mode Fast-Mode UnitMin Max Min Max M_SCLK Clock Frequency f SCL 0 100 0 400 KHz Hold time (repeated) START condition. After this period, the first clock pulse is generated t HD;STA 4.0 - 0.6 - s LOW period of the M_SCLK clock t LOW 4.7 - 1.2 - s HIGH period of the M_SCLK clock t HIGH 4.0 - 0.6 - s Set-up time for a repeated START condition t SU;STA 4.7 - 0.6 - s Data hold time t HD;DAT 02 3.45 3 00 . 9 3 s Data set-up time t SU;DAT 250 - 100 - ns Rise time of both M_SDATA and M_SCLK time (10-90%) t r - 1000 20 + 0.1Cb 4 300 ns Fall time of both M_SDATA and M_SCLK time (10-90%) t f - 300 20 + 0.1Cb 4 300 ns Set-up time for STOP condition t SU;STO 4.0 - 0.6 - s Bus free time between a STOP and START condition t BUF 4.7 - 1.3 - s Capacitive load for each bus line Cb - 400 - 400 pF Serial interface input pin capacitance C IN_SI - 3.3 - 3.3 pF M_SDATA max load capacitance C LOAD_SD - 30 - 30 pF M_SDATA pull-up resistor R SD 1.5 4.7 1.5 4.7 K  S Sr tSU;STOtSU;STAtHD;STA tHIGH tLOW tSU;DAT tHD;DAT tf SDATA SCLK P S tBUFtr tftr tHD;STA

AP0100CS/D Rev. 6, Pub. 1/16 EN 72 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Package Diagram Package Diagram Figure 50: Package Diagram VFBGA100 7x7 CASE 138AH ISSUE O DATE 30 DEC 2014

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