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Semiconductor Components Industries, LLC, 2004 July, 2004 − Rev. 5
1 Publication Order Number:
EF (Emitter Follower) OUTPUT Structure Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering CONTENTS OF APPLICATION NOTE Introduction − DC Termination Analysis Vt R t R t R t R t R t R tVt1 Vt2 External Internal Near (Standard Pair) Far (Standard Pair) Far (Standard Pair) VEE R t R t R t R t R tVt1 Vt2 VEE Vto (Open) VEE (Shorted) VTT Near (Standard Pair) VTT VTT R E VEE Section 2. Parallel Termination − External and Internal Section 1. Unterminated Lines RR RR Section 3. Thevenin Equivalent/Parallel Termination R R Section 4. Series (Back) Termination VBB VBB Driver Receiver *All Media D1 D2 D1 D2 Section 5. Diode Termination RR R R R VCC VBB Section 6. Capacitive Coupling R E R E R E R E R E R E R E R E APPLICATION NOTE http://onsemi.com
correctly as shown in Figure 1.
8 Internal Output
Figure 1. Typical ECL Output with Emitter Follower Output Structure, a current bias for the Emitter Follower output structure. edge (tr or tf) between state levels. jitter operation of the device. Figure 2. State Levels VOH , VOL ,
http://onsemi.com Output Open, Short, and Safe DC Current Left open, an output will only swing a few millivolts due to parasitic “minimum current” leakage paths. Shorted to VEE , a maximum current will develop, limited only by the output transistor 8 impedance, and may cause damage to the output. Worst case short circuit current risks destruction of the devices. ISC VOH R INT = 500 mA! (eq. 1) Where: V OH = 4.0 V V CC = 5.0 V V EE = 0.0 V R int =8 The continuous safe output current, Iout (continuous), maximum limit is 50 mA under all spec operating conditions. The continuous safe repetitive surge, I out (surge), maximum current limit is 100 mA for 10 milliseconds per second duty cycle, provided the device’s total thermal limits are observed. Output current polarity will always be sinking into the termination scheme during proper operation. Static Analysis of Termination Resistor R E The output continuous safe current limit, Iout (cont), determines RE minimum DC termination scheme resistance to VEE although this will not provide a practical AC signal termination as shown in Table A: Minimum RE Values. R E VOH Imax (eq. 2) Table A. Minimum RE Values Line VOH R E(min) PECL 4.0 V 80 LVPECL 2.4 V 48 LVEP PECL 1.6 V 32 A DC terminating resistor minimum, RE (min), of 80, while sufficiently limiting the output load current to VEE , may generate insufficient PECL output LOW and HIGH state transitions. The R E maximum is effectively determined by the application load capacitance, CL, since an RC network is formed by RE and CL which limits the signal fall time, discharging the line to the LOW state voltage level. A sufficiently high value R E or CL can cause the signal fall time to the VOL level to violate specification limits. Designed RE or C L values may selectively eliminate undesirable noise. Dynamic Analysis of Termination Resistor RE The dynamic function of the termination resistor, RE is to develop the voltage change, V , during a high−to−low or low−to−high transition and present this to the transmission medium such as coax, twisted pair, microstrip or stripline. The V signal propagates to the receiver and is either reflected, dissipated, or a combination. Since the reflection coefficient at the load is of opposite polarity to that of the source, a reflection will travel back and forth over the transmission changing polarity after each reflection until critically damped by line impedance. Thus, steps may appear in the signal V at the receiving gate input due to impedance mismatch and consequent partial reflections. When R E is too large, steps appear in the trailing edge of the propagating signal, V, at the input to the receiving gate, slowing the edge speed and increasing the net propagation delay. A reasonable negative−going signal swing at the input of the receiving gate results when the value of R E is selected to produce an initial step of 75% of the expected V , or a 600 mV step for an 800 mV signal at the driving gate. For a RSECL expected V swing of 400, a 300 mV initial step is desired. Hence for a 600 mV initial step: (V OH VEE ) (R t Z0 ) *Z 0 /C01210.6 I(init) * Z0 0.6 (eq. 3) The value for RE is found in Table B: Recommended Values of RE in Dynamic Functional Application. This table lists recommended RE values for the various ECL devices by Family Series according to the equation above. The table assumes operation with various data sheet V OH values and various VCC values driving a Z0 = 50 line. Lowering the value of RE will increase the voltage change, V , launched into the transmission media. Raising the value of RE will decrease the voltage change, V , launched into the transmission media. Table B. Recommended Nominal Values of RE in Dynamic Functional Application Series |VCC −VEE | R E ( NB 2.5 140 NB 3.3 250 10/100LVEP 2.5 50 10/100EP , 100LVEL 3.3 120 10/100EL, 10/100E 5.0 235
configuration is also referred to as a stub or an open line. Figure 3. Unterminated Transmission Line Stub A large positive reflection occurs resulting in overshoot.
- Minimizing Interconnect Line Lengths (Section 1)
- Parallel Termination (Sections 2 and 3)
- Series Termination (Section 4)
- Diode Termination (Section 5)
will not cause saturation problems at the receiving input. 0.03 inch for most practical applications.
- Method of choice for best circuit performance
- Particularly excellent for driving distributed loads
- Undistorted waveform along the full length of the line
- Decreased power consumption. Far DC Current Return − VTT A parallel terminated line is one in which the receiving end is signal terminated internally or externally (usually to a voltage V TT ) through a resistor (Rt) with a value equal to the line characteristic impedance (Figure 4). This line also carries the biasing current for the drivers output far from the driver. Output current and power dissipation is decreased due to use of a V TT termination supply. The VTT supply must sustain the emitter follower output transistor in its active operating region under all operating conditions. A minimum continuous current occurs for the most negative V OL , therefore the VTT supply must remain more negative than the worst case VOLmin and always sink current. Standard VTT is 2.0 V below VCC supply. A parallel resistor, Rt, matching the controlled impedance transmission line, Z0, connects the signal to the VTT supply. The Parallel Termination to VTT is shown in Figure 4. The termination resistors may be internal or external and either ganged into a Combo pin or offered as Singulated pins. Some devices may have each internal resistors independently pinned out, allowing further termination versatility.
Figure 4. Parallel Termination to VTT − Differential and Single−Ended with Combo or Singulated Vt Pins (Far Return)
Figure 12. Thevenin Equivalent Parallel Termination loading of each line must be preserved. may be obtained from the following relationships.
http://onsemi.com Because the resistor divider network of R1 and R2 is used to generate VTT , the variation in VTT will be intimately tied to the variation in VCC . Differentiating the equation for VTT with respect to VCC yields: VTT VCC (R 1 R2 )VCC (eq. 24) For the nominal case, this equation reduces to: VTT 0.6VCC (eq. 25) If V CC = 5% = 0.25 V , then V TT = 0.15 V . As mentioned previously, the real potential for problems will be if the VOL level can potentially put the output emitter follower out of the active operating region and into cutoff. Because of the relationship between the V CC and VTT levels, the only cutoff risk condition occurs at VCCmin , the lowest value of VCC . Applying the equation for IOLmin under this −5% V CC condition yields: IOLmin (V OLmin VTT ) R t (eq. 26) IOLmin (4.75 1.85) 2.85 50 1.0 mA (eq. 27) The results of this cutoff risk analysis show there is no potential for the output emitter follower to be in cutoff. This would indicate a Thevenin equivalent termination scheme is more robust to variation in VCC . Since the designer has the flexibility of choosing the VTT level via the selection of the R1 and R2 resistors, the following procedure can be used. At −5% minimal variation case for VCC : V CC = 4.75 V V TT = VCC − 2.0 V = 2.75 V R2 = 119 R1 = 86 Thus: IOHmax = 23 mA IOLmin = 3.0 mA At +5% minimal variation case for VCC : V CC = 5.25 V V TT = 3.05 V Thus: IOHmax = 28 mA IOLmin = 5.2 mA Although the output currents are slightly higher than nominal, the elimination of emitter follower cutoff risk is well justified. When the equivalent termination resistance matches the line impedance, no reflection occurs because all the energy in the signal is dissipated by the termination. Hence, in comparing properly terminated schemes parallel and Thevenin, a primary consideration is the power supply requirements. As mentioned earlier, the parallel V TT scheme requires an extra power supply; however, the Thevenin termination dissipates 10 times more DC power. Fortunately, this extra power dissipation cannot be seen on the die; therefore, either technique results in similar die junction temperatures.
http://onsemi.com SECTION 6. CAPACITIVE COUPLING RR R R R VCC VBB Although not strictly a termination, AC or capacitive coupling is often used to provide features in conjunction with proper termination. Such capabilities as hot swapping capability, DC isolation to a receiver, and level shifting are possible with capacitive coupling. Data stream characteristics may impose restriction on both termination and capacitive coupling. AC coupled signals have the line DC blocked and will require a DC restoration voltage, V BIAS , for the receiver input. Data in unencoded Non−Return−to−Zero (NRZ) format will require DC restoration prior to AC coupling into a ECL receiver input. A sinusoidal waveform clock signal may be cap coupled for conversion to a square wave with 50% duty cycle and sharp rise and fall edges. The capacitor used to couple the signal must have a impedance rating of < 50 over the frequency range of the input signal. Because large capacitors appear somewhat inductive at high frequencies, it may be necessary to use a small capacitor in parallel with a larger one to achieve satisfactory operation. A coupling capacitor and the signal load impedance form an RC network which will boundary the duration of a pulse. Values for the R (load and leakage total resistance) and C (coupling capacitor) should be selected to provide a time constant, T C , of at least 10x the pulse width. Data streams may require larger TC values to retain logic levels. Hot Swapping The desire often arises to remove or install a receiver or daughter card without powering down the driver or motherboard. This is termed “Hot Swapping”. Powered Driver and an Unpowered Receiver Damage Risk Hot swapping presents a potential risk to an unpowered or powered down ECL device receiver and driver in either the Negative or Positive mode when driven by a typical signal level. When a receiver PECL receiver V CC is off or powered down, the VCC Power Supply typically appears as a low impedance source at 0.0 V capable of sinking considerable current. Typical driver signal levels present voltages that forward bias the input ESD protection diode structure and the input base collector junction. Potentially lethal current paths may develop through forwarded junctions to V CC . There is also a risk for a powered down or off NECL or LVNECL receiver and driver. A VEE supply will typically appear as a low impedance path to 0.0 V (GND). Typical negative levels present signal voltages that will forward bias the input ESD protection diode structure and the input base collector junction to this low impedance path. Potentially lethal current paths may develop through the forwarded junctions and V EE to 0.0 V . Powered down receiver risk may be managed in several ways. 1. Physical Sequencing − the supplies for VEE (Ground) and VCC (Power) may be physically connected prior to signal lines by altering the daughter board edge connection geometry, making V EE and VCC connectors protrude and engage or sequence first. VEE connectors could even be sequenced prior to VCC . This insures the supplies are powered prior to input signal voltages. 2. Switching − a relay (or analog switch) could be used to open or close the supply lines insuring the power supply line is opened when powered off. 3. Cap Coupling − DC isolation of potentially damaging current. 4. Series R − an additional series impedance matching resistor, R S, will act as power splitter with an existing parallel termination resistor, RT, to accomplish some current limiting to help manage the risk. This will also attenuate the amplitude 50%, easily tolerated by most high gain, high input sensitivity devices. Using V BB Pin for VBIAS Some devices provide a convenient VBB pin for use as a VBIAS reference supply to rebias a DC level. A DC rebias level must be at the common mode voltage of the input signal to properly preserve a 50% output duty cycle (see AND8066). A package V BB pin may provide an internally generated DC switching reference voltage for the device inputs, and is available only to the package input pins. Do not port one package V BB pin directly to another device without current amplification. When used, decouple VBB to VCC (or V TT ) via a 0.01 to 0.001F capacitor to suppress noise injection. Limit current to less than 0.5 mA (Absolute Maximum Rating source or sink) as shown in Figure 21. When not used, V BB should be left open.
Figure 23. Differential and Single−Ended AC V ppmin = 300 mV to Vppmax = 1000 mV . altering the values of R1, R1′, R2, and R2′.