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GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124/F150/F250 (0.35 µm) by Microcontroller Division Applications INTRODUCTION Microcontrollers for embedded applications tend to integrate more and more peripherals as well as larger memories. Providing the right products with the right features such as Flash, em- ulated EEPROM and a wide range of peripherals at the right cost is always a challenge. That is why it is mandatory to shrink the microcontroller die size regularly as soon as the technology will allow it. This major step applies to the ST92F120. The purpose of this document is to present the differences between the ST92F120 microcon- troller in 0.50 micron technology versus the ST92F124/F150/F250 in 0.35 micron technology. It provides some guidelines for upgrading applications for both its software and hardware as- pects. In the first part of this document, the differences between the ST92F120 and ST92F124/F150/ F250 devices are listed. In the second part, the modifications required for the application hard- ware and software are described.
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
1 UPGRADING FROM THE ST92F120 TO THE ST92F124/F150/F250
1.1 PINOUT
– Analog input channels were remapped according to the table below. Table 1. Analog Input Channel Mapping cause SCI1 was replaced by SCI-A. and TX1 and RX1 (CAN1) on dedicated pins.
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
1.3 SCHMITT TRIGGERS
– Differences on the VIL and VIH. See Table 2. Table 2. Input Level Schmitt Trigger DC Electrical Characteristics for design guide lines not tested in production.
1.4 MEMORY ORGANIZATION
1.4.1 External memory
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
1.4.2 Flash Sector Organization
Table 5 and Table 6. Table 3. and Table 4 show the previous organization. Table 3. Memory Structure for 128K Flash ST92F120 Flash Device Table 4. Memory Structure for 60K Flash ST92F120 Flash Device Table 5. Memory Structure for 128K ST92F124/F150/F250 Flash device
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124... Table 6. Memory Structure for 64K ST92F124/F150/F250 Flash device F0 as an 8-Kbyte user bootloader area, or sectors F0 and F1 as a 16-Kbyte area.
1.4.3 Flash & E3PROM Control Register Location
In the application, these register locations are usually defined in the linker script file.
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
1.5 RESET AND CLOCK CONTROL UNIT (RCCU)
1.5.1 Oscillator
1.5.2 PLL
Running mode, and oscillates at a low frequency which is typically about 50 kHz. provided, allowing the ST9 to perform some rescue operations. Refer to the ST92F124/F150/F250 datasheet for more details. Figure 1. ST92F120 Internal O scillator Figure 2. ST92F124/F150/F250 Internal O scillator
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
1.6 INTERNAL VOLTAGE REGULATOR
In the ST92F124/F150/F250, the core operates at 3.3V, while the I/Os still operate at 5V. In order to supply the 3.3V power to the core, an internal regulator has been added. Actually, this voltage regulator consists of 2 regulators: – a main voltage regulator (VR), – a low power voltage regulator (LPVR). The main voltage regulator (VR) supplies the current required by the device in all operating modes. The voltage regulator (VR) is stabilized by adding an external capacitor (300 nF min- imum) on one of the two Vreg pins. These Vreg pins are not able to drive other external de- vices, and are only used for regulating the internal core power supply. The low power voltage regulator (LPVR) generates a non-stabilized voltage of approximately VDD/2, with minimum internal static dissipation. The output current is limited, so it is not suffi- cient for full device operation mode. It provides reduced power consumption when the chip is in Low Power mode (Wait For Interrupt, Low Power Wait For Interrupt, Stop or Halt modes). When the VR is active, the LPVR is automatically deactivated.
1.7 EXTENDED FUNCTION TIMER
The hardware modifications in the Extended Function Timer of the ST92F124/F150/F250 as compared to the ST92F120 only concern the interrupt generation functions. But some specific information has been added to the documentation concerning Forced Compare mode and One Pulse mode. This information may be found in the updated ST92F124/F150/F250 Da- tasheet.
1.7.1 Input Capture/Output Compare
On the ST92F124/F150/F250, the IC1 and IC2 (OC1 and OC2) interrupts can be enabled sep- arately. This is done using 4 new bits in the CR3 register: – IC1IE=CR3[7]: Input Capture 1 Interrupt Enable. If reset, Input Capture 1 interrupt is inhibit- ed. When set, an interrupt is generated if the ICF1 flag is set. – OC1IE=CR3[6]: Output Compare 1 Interrupt Enable. When reset, Output Compare 1 inter- rupt is inhibited. When set, an interrupt is generated if the OCF2 flag is set. – IC2IE=CR3[5]: Input Capture 2 Interrupt Enable. When reset, Input Capture 2 interrupt is in- hibited. When set, an interrupt is generated if the ICF2 flag is set. – OC2IE=CR3[4]: Output Compare 2 Interrupt Enable. When reset, Output Compare 2 Inter- rupt is inhibited. When set, an interrupt is generated if the OCF2 flag is set. Note: The IC1IE and IC2IE (OC1IE and OC2IE) interrupts are not significant if the ICIE (OCIE) is set. In order to be taken into account, the ICIE (OCIE) must be reset.
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
1.7.2 PWM Mode
The OCF1 bit cannot be set by hardware in PWM mode, but the OCF2 bit is set every time the counter matches the value in the OC2R register. This can generate an interrupt if the OCIE is set or if the OCIE is reset and OC2IE is set. This interrupt will help any application where pulse widths or periods need to be changed interactively.
1.8 A/D CONVERTER (ADC)
A new A/D converter with the following main features has been added: – 16 channels, – 10-bit resolution, – 4 MHz maximum frequency (ADC clock), – 8 ADC clock cycles for sampling time, – 20 ADC clock cycle for conversion time, – Zero input reading 0x0000, – Full scale reading 0xFFC0, – Absolute accuracy is ± 4 LSBs. This new A/D converter has the same architecture as the previous one. It still supports the an- alog watchdog feature, but now it uses only 2 of the 16 channels. These 2 channels are con- tiguous and channel addresses can be selected by software. With the previous solution using two ADC cells, four analog watchdog channels were available but at fixed channel addresses, channels 6 and 7. Refer to the updated ST92F124/F150/F250 Datasheet for the description of the new A/D Con- verter.
1.9 I²C
1.10 I²C IERRP BIT RESET
On the ST92F124/F150/F250 I²C, the IERRP (I2CISR) bit can be reset by software even if one of the following flags is set: – SCLF, ADDTX, AF, STOPF, ARLO and BERR in the I2CSR2 register – SB bit in the I2CSR1 Register It is not true for the ST92F120 I²C: the IERRP bit cannot be reset by software if one these flags is set. For this reason, on the ST92F120, the corresponding interrupt routine (entered fol- lowing a first event) is re-entered immediately if another event occurred during the first routine execution.
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
1.10.1 START EVENT REQUEST
A difference between the ST92F120 and the ST92F124/F150/F250 I²C exists on the START bit generation mechanism. To generate a START event, the application code sets the START and ACK bits in the I2CCR register: – I2CCCR |= I2Cm_START + I2Cm_ACK; Without the compiler optimization option selected, it is translated in assembler the following way: – or R240,#12 – ld r0,R240 – ld R240,r0 The OR instruction sets the Start bit. On the ST92F124/F150/F250, the second load instruc- tion execution results in a second START event request. This second START event occurs after the next byte transmission. With any of the compiler optimization options selected, the assembler code does not request a second START event: – or R240,#12
1.11 NEW PERIPHERALS
– Up to 2 CAN (Controller Area Network) cells have been added. Specifications are available in the updated ST92F124/F150/F250 Datasheet. – Up to 2 SCIs are available: the SCI-M (Multi-protocol SCI) is the same as on the ST92F120, but the SCI-A (Asynchronous SCI) is new. The specifications for this new peripheral are available in the updated ST92F124/F150/F250 Datasheet.
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
2 HARDWARE & SOFTWARE MODIFICATIONS TO THE APPLICATION BOARD
2.1 PINOUT
– Due to its remapping, CLOCK2 can not be used in the same application. – SCI1 can only be used in asynchronous mode (SCI-A). – The modifications of the analog input channels mapping can be easily handled by software.
2.2 INTERNAL VOLTAGE REGULATOR
Due to the presence of the internal voltage regulator, external capacitors are required on the Vreg pins in order to provide the core with a stabilized power supply. In the ST92F124/F150/ F250, the core operates at 3.3V, while the I/Os still operate at 5V. The minimum recom- mended value is 600 nF or 2*300 nF and the distance between the Vreg pins and the capac- itors must be kept to a minimum. No other modifications need to be made to the hardware application board.
2.3 FLASH & EEPROM CONTROL REGISTERS AND MEMORY ORGANIZATION
To save 1 DPR, the symbol address definitions that correspond to the Flash and EEPROM control registers can be modified. This is generally done in the linker script file. The 4 registers, FCR, ECR, and FESR[0:1], have been defined at 0x221000, 0x221001, 0x221002 and 0x221003, respectively. The 128-Kbyte Flash sector reorganization also affects the linker script file. It must be modi- fied in compliance with the new sector organization. Refer to Section 1.4.2 for the description of the new Flash sector organization.
2.4 RESET AND CLOCK CONTROL UNIT
2.4.1 Oscillator
2.4.1.1 Crystal Oscillator
Even if the compatibility with the ST92F120 board design is maintained, it is no longer recom- mended to insert a 1MOhm resistor in parallel with the external crystal oscillator on a ST92F124/F150/F250 application board.
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
2.4.1.2 Leakages
2.4.1.3 External clock
apply the external clock on the OSCOUT input. – the external resistor between OSCOUT and VDD is not required. Figure 3. ST92F120 Crystal Oscillator Figure 4. ST92F150 Crystal Oscillator
1 MΩ *
when using low drive crystals. Figure 5. ST92F120 External Clock Figure 6. ST92F150 External Clock
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
2.4.2 PLL
2.4.2.1 Standard Mode
The reset value of the PLLCONF register (p55, R246) will start the application in the same way as in the ST92F120. To use free running mode in the conditions described in Section 1.5, the PLLCONF[7] bit must be set.
2.4.2.2 Safety Clock Mode
Using the ST92F120, if the clock signal disappears, the ST9 core and peripheral clock is stopped, nothing can be done to configure the application in a safe state. The ST92F124/F150/F250 design introduces the safety clock signal, the application can be configured in a safe state. When the clock signal disappears (for instance due to a broken or disconnected resonator), the PLL unlock event occurs. The safer way to manage this event is to enable the INTD0 external interrupt and to assign it to the RCCU by setting the INT_SEL bit in the CLKCTL register. The associated interrupt routine checks the interrupt source (refer to the 7.3.6 Interrupt Gen- eration Chapter of the ST92F124/F150/F250 datasheet), and configures the application in a safe state. Note: The peripheral clock is not stopped and any external signal generated by the microcon- troller (for instance PWM, serial communication...) must be stopped during the first instruc- tions executed by the interrupt routine.
2.5 EXTENDED FUNCTION TIMER
2.5.1 Input Capture / Output Compare
In order to generate a Timer Interrupt, a program developed for the ST92F120 may need to be updated in certain cases: – If Timer Interrupts IC1 and IC2 (OC1 and OC2) are both used, ICIE (OCIE) of register CR1 has to be set. The value of the IC1IE and IC2IE (OC1IE and OC2IE) in the CR3 register is not significant. So, the program does not have to be modified in this case. – If only one Interrupt is needed, ICIE (OCIE) must be reset and IC1IE or IC2IE (OC1IE or OC2IE) must be set depending on the interrupt used. – If none of the Timer Interrupts are used, ICIE, IC1IE and IC2IE (OCIE, OC1IE and OC2IE) they must all be reset.
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
2.5.2 PWM Mode
– To disable it, reset OCIE AND OC2IE. – The start conversion channel is now defined by bits CLR1[7:4] (Pg63, R252). two channels must be contiguous. – The ADC clock is selected with CLR2[7:5] (Pg63, R253). – Interrupt registers have not been modified.
2.7 I²C
2.7.1 IERRP BIT RESET
set), a software loop must be implemented. end until all flags are reset. exits from the interrupt routine. Table 7. DiHR Table 8. DiLR
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
2.7.2 START Event Request
To avoid any unwanted double START event, use any of the compiler otpimization options, in the Makefile. For instance: CFLAGS = -m$(MODEL) -I$(INCDIR) -O3 -c -g -Wa,-alhd=$*.lis
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
3 UPGRADING AND RECONFIGURING YOUR ST9 HDS2V2 EMULATOR
3.1 INTRODUCTION
This section contains information about how to upgrade your emulator’s firmware or recon- figure it to support a ST92F150 probe. Once you have reconfigured your emulator to support a ST92F150 probe you can configure it back to support an other probe (for example a ST92F120 probe) following the same procedure and choosing the suitable probe.
3.2 PREREQUISITES TO UPGRADING AND/OR RECONFIGURING YOUR EMULATOR
The following ST9 HDS2V2 emulators and emulation probes support upgrades and/or recon- figuration with new probe hardware: – ST92F150-EMU2 – ST92F120-EMU2 – ST90158-EMU2 and ST90158-EMU2B – ST92141-EMU2 – ST92163-EMU2 Before trying to perform the upgrade/reconfiguration of your emulator, you must ensure that ALL of the following conditions are met: – The monitor version of your ST9-HDS2V2 emulator is higher than or equal to 2.00. [You can see which monitor version your emulator has in the Target field of the About ST9+ Visual Debug window, which you open by selecting Help>About.. from the ST9+ Visual Debug’s main menu.] – If your PC is running on the Windows ® NT ® operating system, you must have the admin- istrator privileges. – You must have installed the ST9+ V6.1.1 (or later) Toolchain on the host PC connected to your ST9 HDS2V2 emulator.
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
3.3 HOW TO UPGRADE/RECONFIGURE YOUR ST9 HDS2V2 EMULATOR
The procedure tells you how to upgrade/reconfigure your ST9 HDS2V2 emulator. Be sure you meet all the prerequisites before starting, otherwise you could damage your emulator by per- forming this procedure. 1.Ensure that your ST9 HDS2V2 emulator is connected via the parallel port to your host PC running either Windows ® 95, 98, 2000 or NT ®. If you are reconfiguring your emulator to be used with a new probe, the new probe must be physically connected to the HDS2V2 main board using the three flex cables. 3.Click the Browse button to browse to folder where you installed the ST9+ V6.1.1 Toolchain. browse to the ..\\downloader\\ subfolder. 4.Locate the ..\\downloader\\<ST9xxxx-EMU2>\\ directory corresponding to the name of the emulator you want to upgrade/configure. For example, if you want to reconfigure your ST92F120 emulator to be used with the ST92F150-EMU2 emulation probe, browse to the ..\\downloader\\<ST92F150-EMU2>\\ directory. 5.Then select the directory corresponding to the version you wish to install (for example, the V1.01 version is found in ..\\downloader\\<ST92F150-EMU2>\\v1.01\\) and select the file <setup_st9xxxx.bat> (for example, setup_st92f150.bat). 6.Click on Open. 7.Click OK in the Run window. The update will begin. You have simply to follow the instruc- tions displayed on your PC’s screen. WARNING : Do not stop the emulator, or the program while the update is in progress! Your emulator may be damaged!
GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124... “THE PRESENT NOTE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH A NOTE AND/OR THE USE MADE BY CUSTOMERS OF THE INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.” Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com