AN966 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 21
Technical content
whose amplitude is 5-10 times higher than the resulting DC value. sation of the power system’s energy capability. ate. A traditional input stage with capacitive filter has a low PF (0.5-0.7) and high harmonic contents. market and the emerging ones that are supposed to require a low-cost Power Factor Correction. field of application considerably. Figure 1. Internal Block Diagram of the L6561.
By using switching techniques, a Power Factor Corrector (PFC) preregulator, located between the recti- fier bridge and the filter capacitor, allows drawing from the mains a quasi-sinusoidal current, in-phase with the line voltage. The PF becomes very close to 1 (more than 0.99 is possible) and the aforesaid drawbacks are eliminated. Theoretically, any switching topology can be used to achieve a high PF but, in practice, the boost topol- ogy has become the most popular because of the advantages it offers: 1) mainly, the circuit requires the fewest external parts, thus it is the cheapest. Additionally: 2) the boost inductor located between the bridge and the switch causes the input di/dt to be low, thus minimizing the noise generated at the input and, therefore, the requirements on the input EMI filter; 3) the switch is source-grounded, therefore is easy to drive. However, boost topology requires the DC output voltage to be higher than the maximum expected line peak voltage (400VDC is a typical value for 220V or wide range mains applications). Besides, there is no isolation between input and output, thus any line voltage surge will be passed on to the output. Two methods of controlling a PFC preregulator are currently widely used: the fixed frequency average current mode PWM and the Transition Mode (TM) PWM (fixed ON-time, variable frequency). The first method needs a complex control that requires a sophisticated controller IC (ST’s L4981A, with the vari- ant of the frequency modulation offered by the L4981B) and a considerable component count. The sec- ond one requires a simpler control (implemented by ST’s L6561), much fewer external parts and is therefore much less expensive. With the first method the boost inductor works in continuous conduction mode, while TM makes the in- ductor work on the boundary between continuous and discontinuous mode, by definition. For a given throughput power, TM operation then involves higher peak currents. This, also consistently with cost considerations, suggests its use in a lower power range (typically below 150W), while the former is rec- ommended for higher power levels. L6561 PFC controller Integrated Circuit The L6561, whose internal block diagram is shown in fig. 1, is an IC intended to control PFC preregula- tors by using the Transition Mode technique. The device is available in Minidip and SO8 packages. The most significant features of the L6561 concern the following points: — undervoltage lockout with hysteresis; — true micropower start-up current (50µA typ., 90µA guaranteed) for simple start-up circuits (just one re- sistor) with very low power dissipation; — internal reference with 1% precision guaranteed (@ Tj=25 °C); — disable function to shut down the device and reduce its current consumption; — two-level overvoltage protection; — internal starter and Zero Current Detection circuit for TM operation; — multiplier with extended dynamics for wide range mains applications, with excellent THD; — on-chip RC filter on the current sense pin; — high capability totem pole output for MOSFET or IGBT drive. The IC is optimised for controlling PFC preregulators based on boost topology in electronic lamp bal- lasts, AC-DC adapters and low power (<150 W) SMPS. However, its excellent performance along with the extremely reduced external parts count allows also the use in unconventional topologies/applica- tions. Low power off-line AC-DC converters (using isolated flyback topology) with or without Power Fac- tor Correction are the most noticeable examples. Device Blocks Description SUPPLY BLOCK As shown in fig. 1, a linear voltage regulator supplied by Vcc generates an internal 7V rail used to supply the whole integrated circuit, except for the output stage which is supplied directly from Vcc. In addition, a bandgap circuit generates the precise internal reference (2.5V±1% @ 25°C) used by the control loop to ensure a good regulation. In fig.2 is shown the undervoltage lockout (UVLO) comparator with hysteresis used to enable the chip as long as the Vcc voltage is high enough to ensure a reliable operation. AN966 APPLICATION NOTE
preregulator output DC voltage constant. must be constant over a line half-cycle to achieve high PF. mediately. Hence a fast OVP detector, based on a different concept, is necessary. where it is sensed. In case, a two-step procedure can occur. Figure 2. Internal Supply Block.
re-enabled as the E/A output goes back into its linear region. Fig. 4 illustrates the combined action of dynamic and static OVP. As the circuit is running, the signal for ZCD is obtained with an auxiliary winding on the boost inductor. gate of the MOSFET, producing also the signal for arming the ZCD circuit. taken into account at design time. vice operation, the pull-down on the pin must be released. comparator, which sets the MOSFET peak current cycle by cycle. Figure 5. Zero Current Detection, Triggering and Disable Block.
each line half-cycle (see "Boost Inductor"). pated inside the external MOSFET. tinuous current mode and that is why this system is called a Transition Mode PFC. jected. These drawbacks limit the use of the TM PFC to lower power range applications. will be just the input current (Irms), the maximum peak mains voltage and the thermal data of the diodes. Figure 10. Inductor Current waveform and
quency inductor current ripple (twice the average line current, see fig. 9). The worst conditions will occur on the peak of the minimum rated input voltage. The maximum high frequency voltage ripple is usually imposed between 1% and 10% of the minimum rated input voltage. This is expressed by a coefficient r (typically, r = 0.01 to 0.1): C in = I rms 2π ⋅ ƒsw ⋅ r ⋅ Virms (min) High values of Cin alleviate the burden to the EMI filter but cause the power factor and the harmonic con- tents of the mains current to worsen, especially at high line and light load. On the other hand, low values of C in improve power factor and reduce mains current distortion but require heavier EMI filtering and increase power dissipation in the input bridge. It is up to the designer to find the right trade-off in their application. Output Capacitor The output bulk capacitor (Co) selection depends on the DC output voltage, the admitted overvoltage, the output power and the desired voltage ripple. The 100 to 120Hz (twice the mains frequency) voltage ripple (ΔVO = 1/2 ripple peak-to-peak value) is a function of the capacitor impedance and the peak capacitor current (IC(2f)pk = Io): (2π ⋅ 2f ⋅ CO ) 2 + ESR With a low ESR capacitor the capacitive reactance is dominant, therefore: C O ≥ IO 4π ⋅ f ⋅ ΔVO = PO 4π ⋅ f ⋅ VO ⋅ ΔVO ΔVo is usually selected in the range of 1 to 5% of the output voltage. Although ESR usually does not affect the output ripple, it has to be taken into account for power losses calculation. The total RMS capacitor ripple current, including mains frequency and switching frequency components, is: 9π ⋅ I rms ⋅ Virms Vo − I o If the application has to guarantee a specified hold-up time, the selection criterion of the capacitance will change: Co has to deliver the output power for a certain time (tHold) with a specified maximum dropout voltage: C O = 2 ⋅ PO ⋅ tHold V o_min − V op_min where Vo_min is the minimum output voltage value (which takes load regulation and output ripple into account) and Vop_min is the minimum output operating voltage before the ’power fail’ detection from the downstream system supplied by the PFC. Boost Inductor Designing the boost inductor involves several parameters and different approaches can be used. First, the inductance value must be defined. The inductance (L) is usually determined so that the mini- mum switching frequency is greater than the maximum frequency of the internal starter, to ensure a cor- rect TM operation. Assuming unity PF, it is possible to write: Ton = L ⋅ ILpk ⋅ sin(θ) √2 ⋅ Virms ⋅ sin(θ) = L ⋅ ILpk √2 ⋅ Virms Toff = L ⋅ ILpk ⋅ sin(θ) AN966 APPLICATION NOTE
being Ton and Toff the ON-time and the OFF-time of the power MOSFET respectively, ILpk the maxi- mum peak inductor current in a line cycle and θ the instantaneous line phase (θ∈ (0, π)). Note that the ON-time is constant over a line cycle. As previously said, ILpk is twice the line-frequency peak current, which is related to the input power and the line voltage: Virms Substituting this relationship in the expressions of Ton and Toff, after some algebra it is possible to find the instantaneous switching frequency along a line cycle: fsw (θ) = 1 Ton + Toff = 1 2 ⋅ L ⋅ Pi ⋅ V irms ⋅ (VO − √2 ⋅ Virms ⋅ sin(θ)) VO The switching frequency will be minimum at the top of the sinusoid (θ = π/2 ⇒ sin(θ) =1 ), maximum at the zero crossings of the line voltage (θ = 0 or π ⇒ sin(θ) = 0) where Toff = 0. The absolute minimum frequency ƒsw(min) can occur at either the maximum or the minimum mains volt- age, thus the inductor value is defined by: L = V 2 ⋅ ƒsw (min) ⋅ Pi ⋅ VO where Virms can be either Virms(min) or Virms(max), whichever gives the lower value for L. The minimum suggested value for ƒsw(min) is 15 kHz, not to interfere with the internal starter (see ZCD and triggering block description) . Once defined the value of L, the real design of the inductor can start. As to the magnetic material and the geometry, the need of isolation due to the high voltage, and the operating frequency range make the standard high frequency ferrite (gapped core-set with bobbin) the usual choice in PFC applications. Among the various types offered by manufacturers the most suitable one will be selected with technical and economic considerations. The next step is to estimate the core size. To get the approximated value of the minimum core size, it is possible to use the following practical formula: Volume ≥ 4K ⋅ L ⋅ Irms where Volume is expressed in cm3, L in mH and the specific energy constant K depends on the ratio of the gap length (lgap) and the effective magnetic length (le) of the ferrite core: K ≅ 14 ⋅ 10 ⋅ le lgap The ratio le/lgap is fixed by the designer. Then the winding must be specified. The turn number and the wire cross-section are the quantities to be defined. The (maximum) instantaneous energy inside the boost inductor (1/2 ⋅ L ⋅ ILpk2) can be expressed in terms of energy stored in the magnetic field, given by the maximum energy density times the effective core volume Ve: 2 ⋅ L ⋅ ILpk = 1 2 ⋅ ΔH ⋅ ΔB ⋅ Ve ≈ 1 2 ⋅ ΔH ⋅ ΔB ⋅ Ae ⋅ Ie, where: Ae is the effective area of the core cross-section, ΔH is the swing of the magnetic field strength and ΔB is the swing of the magnetic flux density. To prevent the core from saturating because of its high permeability and allow an adequate ΔH, it is nec- essary to introduce an air gap. Despite the gap length lgap is few per cent of le, the permeability of ferrite is so high (for power ferrites, typically µr = 2500) that it is possible to assume all the magnetic field concentrated in the air gap with good approximation (ΔH ≈ ΔHgap). For instance, with 1% of lgap/le (which is the minimum suggested value) the er- ror caused by this assumption is about 4%. The error will be smaller if the lgap/le ratio is larger. AN966 APPLICATION NOTE
As a result, neglecting fringing flux in the air gap region, the energy balance can be re-written as: L ⋅ ILpk ≈ ΔH gap ⋅ ΔB ⋅ Ae ⋅ Igap The flux density ΔB is the same throughout the core and the air gap and is related to the field strength inside the air gap by the well-known relationship: ΔB = µ0 ⋅ ΔHgap . Then, considering Ampere’s law (applied to the air gap region only): Igap ⋅ ΔH gap ≈ N ⋅ ILpk , from the energy balance equation it is possible to obtain: L ≈ µ0 ⋅ N ⋅ Ae Igap µο ⋅ Ae where N is the turn number of the winding. As N is defined, it is recommended to check for the saturation of the core (see Pin 4 description). If the check shows a result too close to the rated limit, an increase of lgap and a new calculation will be neces- sary. The wire gauge selection is based on limiting the copper losses at an acceptable value: PCU = 4 3 ⋅ Irms ⋅ RCU ; due to the high frequency ripple the effective wire resistance RCU is increased by skin and proximity ef- fects. For this reason Litz wire or multi-wire solutions are recommended. Finally, the space occupied by the winding will be evaluated and, if it does not fit the winding area of the bobbin, a bigger core set will be considered and the winding calculation repeated. It is now necessary to add an auxiliary winding to the inductor, in order for the ZCD pin to recognize when the current through the inductor has gone to zero. It is anyway a low cost thin wire winding and the turns number is the only parameter to be defined (see Pin 5 description). POWER MOSFET The choice of the MOSFET concerns mainly its RDSon , which depends on the output power, since the breakdown voltage is fixed just by the output voltage, plus the overvoltage admitted and a safety margin. The MOSFET’s power dissipation depends on conduction and switching losses. The conduction losses are given by: PON = IQrms ⋅ RDSon where: 6 − 4 √2 9π ⋅ Virms VO The switching losses due to current-voltage cross occur only at turn-off because of the TM operation: PCROSS = VO ⋅ Irms ⋅ tfall ⋅ ƒsw, AN966 APPLICATION NOTE
where tfall is the crossover time at turn-off. At turn-on the loss is due to the discharge of the total drain capacitance inside the MOSFET itself. In general, these losses are given by: PCAP = 3.3 ⋅ Coss ⋅ VDRAIN 1.5 + 1 2 ⋅ Cd ⋅ VDRAIN 2 ⋅ ƒsw , where Coss is the internal drain capacitance of the MOSFET (@ VDS = 25V), Cd is the total external drain parasitic capacitance and VDRAIN is the drain voltage at MOSFET turn-on. In practice it is possible to give only a rough estimate of the total switching losses because both ƒsw and VDRAIN change along a given line half-cycle. VDRAIN , in particular, is affected not only by the sinusoidal change of the input volt- age but also by the drop due to the resonance of the boost inductor with the total drain capacitance (see fig. 12). This causes, at low mains voltage, V DRAIN to be zero during a significant portion of each line half-cycle. It is possible to show that "Zero-Voltage-Switching" occurs as long as the instantaneous line voltage is less than half the output voltage. BOOST DIODE The boost freewheeling diode will be a fast recovery one. The value of its DC and RMS current, useful for losses computation, are respectively: I Do = Io 9π ⋅ Virms VO The conduction losses can be estimated as follows: PDON = Vto ⋅ IDo + Rd ⋅ IDrms where Vto (threshold voltage) and Rd (differential resistance) are parameters of the diode. The breakdown voltage is fixed with the same criterion as the MOSFET. L6561 Biasing Circuitry (pin by pin) Please, refer to the schematic circuit shown in fig. 13. Pin 1 (INV) leads both to the inverting input of the E/A and to the OVP circuit. A resistive divider will be connected between the regulated output voltage of the boost and the pin. The internal reference on the non-inverting input of the E/A is 2.5V and the OVP alarm level current is 40µA. R11+ R12 and R13 will be then selected as follow: R11 + R12 R13 = V O 2.5V − 1 R11 + R12 = Δ V OVP 40 µA , Pin 2 (COMP) is the output of the E/A and also one of the two inputs of the multiplier. A feedback com- pensation network, placed between this pin and INV (1), reduces the bandwidth so to avoid the attempt of the system to control the output voltage ripple (100-120Hz). In the simplest case, this compensation is just a capacitor, which provides a low frequency pole as well as a high DC gain. A simple criterion to define the capacitance value, is to to provide ~60dB attenuation at 100Hz: C23 = 10 2 π ⋅ R7 Please refer to [1] for more information on how to compensate the E/A. AN966 APPLICATION NOTE
tified mains to get a sinusoidal voltage reference. peated beginning with a lower VMULTpkx value. nal circuit ensures that the PWM latch cannot be set until the signal on pin 4 has disappeared. Figure 11. Multiplier characteristics family
powered on (especially at low line) or powered off. auxiliary winding of the boost inductor through a limiting resistor. and considering the maximum voltage (the absolute value) across the auxiliary winding. power dissipation at turn-on. This pin incorporates also a disable function. 150µA generator pulls up the pin. Figure 12. Optimum MOSFET Turn-on
resistor connected between the gate and the source of the external MOSFET used to this purpose. ally, one resistor connected to the rectified mains) and to the self-supply circuit. load, especially in wide range mains applications. rises to a value depending on the operating conditions but never exceeding 4.5mA. The device keeps on working as long as the supply voltage is over the UVLO threshold (10.3V max). harm as long as the current is below the maximum rating. results of the board evaluation are presented. as to critical components, is an important step. Table 1. Wide Range PFC Target Specification. R DSON because of power dissipation. The inductance value (L) is as high as 0.7 mH, which leads to a minimum switching frequency of 35kHz.
Assuming an lgap/le ratio of 2.5% the minimum core size estimate gives a minimum volume of 2.6 cm3. Considering the E series, the E25 (2.99 cm3 effective volume) has been selected. To reduce copper losses, a multiple wire (20 x 0.1mm) has been adopted. The resistance of the winding is about 0.75Ω at 35 kHz , so the maximum copper losses are about 1W. OUTPUT FILTER CAPACITOR (C6): The specification on the output voltage ripple determines the capacitance value. Assuming 50 Hz minimum line frequency, a 47µF/450V capacitor has been selected. This gives an out- put ripple ΔVo = ±7 V. MULTIPLIER SETTING (R1, R2, R3) AND SENSE RESISTOR (R9, R10): The multiplier divider is selected so to exploit about 80% of its linear dynamics (V MULTpkx = 2.5V) as per the procedure described in pin 3 description. The sense resistor is then determined. As to R9 and R10, metal film resistors are suitable because of the high peak current flowing in it. OUTPUT DIVIDER (R11, R12, R13): R11 + R12 is selected so to achieve the desired overvoltage trip level (ΔVOVP = 60V), while R13 is cho- sen so to get the specified output regulated voltage. ERROR AMPLIFIER COMPENSATION The error amplifier has been compensated so as to get a type 2 amplifier that provides a pole at the ori- gin and a zero-pole pair. As compared to a type1 amplifier (compensated with a single capacitor) this compensation offers a higher phase margin under all operating conditions and is therefore recom- mended when the PFC pre-regulator powers a DC-DC converter. However, the twice-mains-frequency gain will be higher because of the zero, which causes a higher ripple at the output of the E/A and, as a result, a higher 3rd harmonic (and a higher THD) of the current drawn from the mains. THD REDUCER In the PCB there is provision for a network (see schematic of figure 13, in the dotted box) able to reduce the crossover distortion of the PFC input current, that is the small flat region appearing at the zero cross- ings of the mains voltage. The effect of this circuit is to force the ON-time of the power switch to increase nearby the zero-crossings. As a result, the energy inside the boost inductor will be greater and the dead- time during which there is no energy transfer is reduced. The circuit fine-tuning has to be made experi- mentally. NTC The NTC has been moved from the input to the output, in series with the boost diode. In this way, though still doing its job of inrush current limiter, it will undergo the output current instead of the input current, as in the typical position, with a considerable power dissipation reduction. The extra voltage on mosfet’s drain while the boost diode is conducting is negligible. The schematic circuit of fig. 13 shows the values of all the parts used. In fig. 14 the printed circuit board and the component layout of the demonstration board are shown. AN966 APPLICATION NOTE
Figure 18. Power Factor Corrected Lamp Ballast using the L6569 driver.
24 Vdc / 2A
Figure 17. Wide Range 50W PFC, Flyback Topology.
Figure 19. Vmains=277 Vac, Vo=320V, Po=140W buck-boost topology [1] "Control loop modelling of L6561-based TM PFC" (AN1089).
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia-Brazil-Canada-China-Finland-France-Germany- Hong Kong-India-Israel-Italy-Japan-Malaysia-Malta-Morocco-Singapore- Spain- Sweden-Switzerland-United Kingdom-United States. http://www.st.com AN966 APPLICATION NOTE