AN7183

NXP Semiconductors

Digital Video Encoder EURO-DENC 1996 Jul 08

Manufacturer: NXP Semiconductors

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SAA7182 PHILIPS | Alldatasheet

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Preliminary speciﬁcation Supersedes data of 1995 Sep 19 File under Integrated Circuits, IC22

1996 Jul 08

SAA7182; SAA7183 Digital Video Encoder (EURO-DENC)

1996 Jul 08 2

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183

FEATURES

CMOS 5 V device
Digital PAL/NTSC/SECAM encoder
System pixel frequency 13.5 MHz
Accepts MPEG decoded data on 8-bit wide input port. Input data format Cb, Y, Cr etc. or Y and Cb, Cr on 16 lines ( “CCIR 656”)
Three DACs for CVBS, Y and C operating at 27 MHz with 10-bit resolution
Three DACs for RGB operating at 27 MHz with 9-bit resolution, RGB sync on CVBS and Y
CVBS, Y, C and RGB output simultaneously
Closed captioning and teletext encoding including sequencer and filter
On-chip YUV to RGB matrix
Fast I2C-bus control port (400 kHz)
Encoder can be master or slave
Programmable horizontal and vertical input synchronization phase
Programmable horizontal sync output phase
Internal Colour Bar Generator (CBG)
Overlay with Look-Up Tables (LUTs) 8× 3 bytes
Macrovision Pay-per-View protection system as option, also used for RGB output This applies to SAA7183 only. The device is protected by USA patent numbers 461603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductor sales office for more information
Controlled rise/fall times of output syncs and blanking
Down-mode of DACs
PLCC84 package. GENERAL DESCRIPTION The SAA7182; SAA7183 encodes digital YUV video data to an NTSC, PAL, SECAM CVBS or S-Video signal and also RGB. The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4:2:2 multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip Digital-to-Analog Converters (DACs). The circuit is compatible to the DIG-TV2 chip family. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT V DDA analog supply voltage 4.75 5.0 5.25 V VDDD digital supply voltage 4.75 5.0 5.25 V IDDA analog supply current − 90 110 mA IDDD digital supply current − 220 250 mA Vi input signal voltage levels TTL compatible Vo(p-p) analog output signal voltages Y, C, CVBS and RGB without load (peak-to-peak value) − 2 − V R L load resistance 80 −−Ω ILE LF integral linearity error −−± 2 LSB DLE LF differential linearity error −−± 1 LSB Tamb operating ambient temperature 0 − +70 °C

1996 Jul 08 3

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183

ORDERING INFORMATION

SAA7182WP PLCC84 plastic leaded chip carrier; 84 leads SOT189-2 SAA7183WP PLCC84 plastic leaded chip carrier; 84 leads SOT189-2 Fig.1 Block diagram. handbook, full pagewidth I2C-BUS INTERFACE DATA MANAGER SECAM PROCESSOR ENCODER SYNC CLOCK OUTPUT INTERFACE D A RGB PROCESSOR D A 18 4 8 3 4 50 35 36 20 47 45 44 48 75 68 64, 70, 72, 74 DP0 to DP7 MP7 to MP0 KEY TTX OVL2 to OVL0 3, 15, 24, 30, 39, 42, 51, 79, 81 5, 14, 22, 29, 38, 41, 49, 80, 82 2, 23, 40, 43, 46, 56, 59, 62, 65, 66 78 77 53 63 54, 57, 60 RESET SDA SCL RTCI CDIR RCV1 RCV2 TTXRQ CREF XTALO XTALI LLC VrefH2 Y/C/CVBS VDDA4 to VDDA7 SA CVBS Y CHROMA VSSA VrefL2 VrefL1 RED GREEN BLUE I2C-bus control I2C-bus control I2C-bus control I2C-bus control I2C-bus control I2C-bus control I2C-bus control DbDr VSSD1 to VSSD9 VDDD1 to VDDD9 VDDA1 to VDDA3 n.c. SP AP VrefH1 IRGB internal control bus clock and timing 8 8 YY CCbCr Y CbCr 10 to 13 16 to 19 25 to 28 31 to 34 6 to 8 SAA7182 SAA7183 MGB696

1996 Jul 08 4

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 PINNING SYMBOL PIN DESCRIPTION RESET 1 Reset input, active LOW. After reset is applied, all digital I/Os are in input mode. The I2C-bus receiver waits for the START condition. n.c. 2 not connected V SSD1 3 digital ground 1 SA 4 The I 2C-bus slave address select pin. LOW: slave address = 88H, HIGH = 8CH. VDDD1 5 digital supply voltage 1 OVL2 6 3-bit overlay data input. This is the index for the internal look-up table.OVL1 7 OVL0 8 KEY 9 Key input for OVL. When HIGH it selects OVL input. DP0 10 Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode is used.DP1 11 DP2 12 DP3 13 V DDD2 14 digital supply voltage 2 VSSD2 15 digital ground 2 DP4 16 Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode is used.DP5 17 DP6 18 DP7 19 TTXRQ 20 Teletext request output, indicating when the bitstream is valid. TTX 21 Teletext bitstream input. V DDD3 22 digital supply voltage 3 n.c. 23 not connected V SSD3 24 digital ground 3 MP7 25 Upper 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr data, or input for Y data only, if 16 line input mode is used.MP6 26 MP5 27 MP4 28 V DDD4 29 digital supply voltage 4 VSSD4 30 digital ground 4 MP3 31 Lower 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr data, or input for Y data only, if 16 line input mode is used.MP2 32 MP1 33 MP0 34 RCV1 35 Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal. RCV2 36 Raster Control 2 for video port. This pin provides an HS pulse of programmable length or receives an HS pulse. RTCI 37 Real Time Control Input. If the LLC clock is provided by an SAA7111 orSAA7151B , RTCI should be connected to the RTCO pin of the respective decoder to improve the signal quality.

1996 Jul 08 5

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 VDDD5 38 digital supply voltage 5 VSSD5 39 digital ground 5 n.c. 40 not connected V DDD6 41 digital supply voltage 6 VSSD6 42 digital ground 6 n.c. 43 not connected XTALI 44 Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected to ground. XTALO 45 Crystal oscillator output (to crystal). n.c. 46 not connected CREF 47 Clock Reference signal. This is the clock qualiﬁer for DIG-TV2 compatible signals. LLC 48 Line-Locked Clock. This is the 27 MHz master clock for the encoder. The I/O direction is set by the CDIR pin. V DDD7 49 digital supply voltage 7 CDIR 50 Clock direction. If the CDIR input is HIGH, the circuit receives a clock and optional CREF signal, otherwise if CDIR is LOW CREF and LLC are generated by the internal crystal oscillator. V SSD7 51 digital ground 7 VrefL1 52 Lower reference voltage 1 input for the RGB DACs, connect to VSSA . VrefH1 53 Upper reference voltage 1 input for the RGB DACs, connect via 100 nF capacitor to VSSA. VDDA1 54 Analog supply voltage 1 for the RGB DACs. BLUE 55 Analog output of the BLUE component. n.c. 56 not connected V DDA2 57 Analog supply voltage 2 for the RGB DACs. GREEN 58 Analog output of the GREEN component. n.c. 59 not connected V DDA3 60 Analog supply voltage 3 for the RGB DACs. RED 61 Analog output of the RED component. n.c. 62 not connected I RGB 63 Current input for RGB ampliﬁers, connected via 15 kΩ resistor to VDDA . VDDA4 64 Analog supply voltage 4 for the Y/C/CVBS DACs. n.c. 65 not connected n.c. 66 not connected V SSA 67 Analog ground for the DACs. IY/C/CVBS 68 Current input for the Y/C/CVBS ampliﬁers, connected via 15 kΩ resistor to VDDA . CHROMA 69 Analog output of the chrominance signal. V DDA5 70 Analog supply voltage 5 for the Y/C/CVBS DACs. Y 71 Analog output of the luminance signal. V DDA6 72 Analog supply voltage 6 for the Y/C/CVBS DACs. CVBS 73 Analog output of the CVBS signal. SYMBOL PIN DESCRIPTION

1996 Jul 08 6

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 VDDA7 74 Analog supply voltage 6 for the Y/C/CVBS DACs. VrefH2 75 Upper reference voltage 2 input for the Y/C/CVBS DACs, connected via 100 nF capacitor to VSSA. VrefL2 76 Lower reference voltage 2 input for the Y/C/CVBS DACs, connect to VSSA . AP 77 Test pin. Connected to digital ground for normal operation. SP 78 Test pin. Connected to digital ground for normal operation. V SSD8 79 digital ground 8 VDDD8 80 digital supply voltage 8 VSSD9 81 digital ground 9 VDDD9 82 digital supply voltage 9 SCL 83 I 2C-bus serial clock input. SDA 84 I 2C-bus serial data input/output. SYMBOL PIN DESCRIPTION

1996 Jul 08 7

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Fig.2 Pin configuration. handbook, full pagewidth SAA7182 SAA7183 MGB697 12DP2 DP3 VDDD2 VSSD2 DP4 DP5 DP6 DP7 TTXRQ TTX VDDD3 n.c. VSSD3 MP7 MP6 MP5 MP4 VDDD4 VSSD4 MP3 MP2 VDDA7 CVBS VDDA6 Y VDDA5 CHROMA IY/C/CVBS VSSA n.c. n.c. VDDA4 IRGB n.c. RED VDDA3 n.c. GREEN VDDA2 n.c. BLUE VDDA1 MP1 MP0 RCV1 RCV2 RTCI VDDD5 VSSD5 n.c. VDDD6 VSSD6 n.c. XTALI XTALO n.c. CREF LLC VDDD7 CDIR VSSD7 VrefL1 VrefH1 DP1 DP0 KEY OVL0 OVL1 OVL2 VDDD1 SA VSSD1 n.c. RESET SDA SCL VDDD9 VSSD9 VDDD8 VSSD8 SP AP VrefL2 VrefH2

1996 Jul 08 8

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 FUNCTIONAL DESCRIPTION The digital video encoder (EURO-DENC) encodes digital luminance and colour difference signals into analog CVBS and simultaneously S-Video signals. NTSC-M, PAL B/G and SECAM standards and sub-standards are supported. Both interlaced and non-interlaced operation is possible for all standards. In addition to RED, GREEN and BLUE converted components, the dematrixed YUV input is available on three separate analog outputs. The basic encoder function consists of subcarrier generation and colour modulation also insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of RS-170-A and “CCIR 624”. For ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. For total filter transfer characteristics see Figs 3, 4, 5, 6, 7 and 8. The DACs for Y, C and CVBS are realized with full 10-bit resolution, DACs for RGB are with 9-bit resolution. The MPEG port (MP) accept 8 lines multiplexed Cb-Y-Cr data. The 8-bit multiplexed Cb-Y-Cr formats are “CCIR 656” (D1 format) compatible, but the SAV, EAV etc. codes are not decoded. Alternatively, 8-bits Y on MP port and 8-bit multiplexed Cb, Cr on DP port can be chosen as input. A crystal-stable master clock (LLC) of 27 MHz, which is twice the CCIR line-locked pixel clock of 13.5 MHz, needs to be supplied externally. Optionally, a crystal oscillator input/output pair of pins and an on-chip clock driver is provided. It is also possible to connect a Philips Digital Video Decoder (SAA7111 or SAA7151B) in conjunction with a CREF clock qualifier to EURO-DENC. Via RTCI pin connected to RTCO of a decoder, information concerning actual subcarrier, PAL-ID (see “data sheet SAA7111”) definite subcarrier phase can be inserted. The EURO-DENC synthesizes all necessary internal signals, colour subcarrier frequency, and synchronization signals, from that clock. The encoder is always timing master for the MPEG port (MP), but it can additionally be configured as slave with respect to the RCV trigger inputs. European teletext encoding is supported if an appropriate teletext bitstream is applied to the TTX pin. The IC also contains Closed Caption and Extended Data Services Encoding (Line 21), and supports anti-taping signal generation in accordance with Macrovision; it also supports overlay via KEY and three control bits by a 24× 8 LUT. A number of possibilities are provided for setting of different video parameters such as: Black and blanking level control Colour subcarrier frequency Variable burst amplitude etc. During reset ( RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the I 2C-bus interface to abort any running bus transfer and sets register 3A to 03H, register 61 to 06H and registers 6BH and 6EH to 00H. All other control registers are not influenced by a reset. Data manager In the data manager, real time arbitration on the data stream to be encoded is performed. Depending on the polarity of pin KEY, the MP input (or MP/DP input) or OVL input are selected to be encoded to CVBS and Y/C signals, and output as RGB. KEY controls OVL entries of a programmable LUT for encoded signals and for RGB output. The common KEY switching signal can be disabled by software for the signals to be encoded (Y, C and CVBS), such that OVL will appear on RGB outputs, but not on Y, C and CVBS. OVL input under control of KEY can be also used to insert decoded teletext information or other on-screen data. Optionally, the OVL colour LUTs located in this block, can be read out in a pre-defined sequence (8 steps per active video line), achieving, for example, a colour bar test pattern generator without need for an external data source. The colour bar function is only under software control.

1996 Jul 08 9

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Encoder VIDEO PATH The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals. Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). After having been inserted a fixed synchronization level, in accordance with standard composite synchronization schemes, and blanking level, programmable also in a certain range to allow for manipulations with Macrovision anti-taping, additional insertion of AGC super-white pulses, programmable in height, is supported. In order to enable easy analog post filtering, luminance is interpolated from 13.5 MHz data rate to 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. For transfer characteristic of the luminance interpolation filter see Figs 5 and 6. Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 MHz data rate to 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y/C output. For transfer characteristics of the chrominance interpolation filter see Figs 3 and 4. The amplitude of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. The numeric ratio between Y and C outputs is in accordance with set standards. T ELETEXT INSERTION AND ENCODING Pin TTX receives a teletext bitstream sampled at the LLC clock, each teletext bit is carried by four or three LLC samples. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines selectable independently for both fields. The internal insertion window for text is set to 360 teletext bits including clock run-in bits. For protocol and timing see Fig.17. C LOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of Closed Caption or Extended Data Service, delivered by the control interface, can be encoded (Line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number where data is to be encoded in, can be modified in a certain range. Data clock frequency is in accordance with definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode Closed Caption Data for 50 Hz field frequencies at 32 times horizontal line frequency. A NTI-TAPING (SAA7183 ONLY ) For more information contact your nearest Philips Semiconductors sales office. RGB processor This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, Cb, Cr signals are dematrixed, 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. For transfer curves of luminance and colour difference components of RGB see Figs 7 and 8. SECAM processor SECAM specific pre-processing is achieved in this block by a pre-emphasis of colour difference signals (for gain and phase see Figs 9 and 10. A baseband frequency modulator with a reference frequency shifted from 4.286 MHz to DC carries out SECAM modulation in accordance with appropriate standard or optionally wide clipping limits. After the HF pre-emphasis, also applied on a DC reference carrier (anti-Cloche filter; see Figs 11 and 12), line-by-line sequential carriers with black reference of 4.25 MHz (Db) and 4.40625 MHz (Dr) are generated using specified values for FSC programming bytes. Alternating phase reset in accordance with SECAM standard is carried out automatically. During vertical blanking the so-called bottle pulses are not provided.

1996 Jul 08 10

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Output interface/DACs In the output interface encoded both Y and C signals are converted from digital-to-analog in 10-bit resolution. Y and C signals are also combined to a 10-bit CVBS signal. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitudes at the input of the DAC for CVBS is reduced by 15⁄16 with respect to Y and C DACs to make maximum use of conversion ranges. RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 9-bit resolution. Outputs of the DACs can be set together in two groups via software control to minimum output voltage for either purpose. Synchronization Synchronization of the EURO-DENC is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to RCV1 can be influenced by programming the polarity and on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. If the horizontal phase is not be influenced by RCV1, a horizontal pulse needs to be supplied at the RCV2 pin. Timing and trigger behaviour can also be influenced for RCV2. If there are missing pulses at RCV1 and/or RCV2, the time base of EURO-DENC runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (such with wrong phase) must occur. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the IC can output:

A Vertical Sync signal (VS) with 3 or 2.5 lines duration, or
An ODD/EVEN signal which is LOW in odd fields, or
A field sequence signal (FSEQ) which is HIGH in the first of 4 respectively 8 respectively 12 fields. On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The polarity of both RCV1 and RCV2 is selectable by software control. Field length is in accordance with 50 Hz or 60 Hz standards, including non-interlaced options; start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line, if the standard blanking option SBLBN is not set. I 2C-bus interface The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte. Two I 2C-bus slave addresses are selected: 88H: LOW at pin 4 8CH: HIGH at pin 4. Input levels and formats EURO-DENC expects digital Y, Cb, Cr data with levels (digital codes) in accordance with “CCIR 601”. For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. For RGB outputs fixed amplification in accordance with “CCIR 601” is provided. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation.

1996 Jul 08 11

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Table 1 “CCIR 601” signal component levels Notes 1. Transformation: 2. Representation of R, G and B at the output is 9 bits at 27 MHz. Table 2 8-bit multiplexed format (similar to “CCIR 601”) Table 3 16-bit multiplexed format (DTV2 format) COLOUR SIGNALS (1) YC b C r R (2) G (2) B (2) White 235 128 128 235 235 235 Yellow 210 16 146 235 235 16 Cyan 170 166 16 16 235 235 Green 145 54 34 16 235 16 Magenta 106 202 222 235 16 235 Red 81 90 240 235 16 16 Blue 41 240 110 16 16 235 Black 16 128 128 16 16 16 TIME 0 1 2 2 4 5 6 7 Sample Cb

0 Y0 Cr0 Y1 Cb 2 Y2 Cr2 Y3

Luminance pixel number 0 1 2 3 Colour pixel number 0 2 TIME 0 1 2 3 4 5 6 7 Sample Y line Y 0 Y1 Y2 Y3 Sample UV line Cb 0 Cr0 Cb 2 Cr2 Luminance pixel number 0 1 2 3 Colour pixel number 0 2

1996 Jul 08 12

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183Bit allocation map Table 4 Slave Receiver (Slave Address 88H or 8CH) REGISTER FUNCTION SUB ADDRESS DATA BYTE D7 D6 D5 D4 D3 D2 D1 D0 Null 00 00000000 Null 39 00000000 Input port control 3A CBENB DISKEY 0 0 0 FMT16 Y2C UV2C OVL LUT Y0 42 OVLY07 OVLY06 OVLY05 OVLY04 OVLY03 OVLY02 OVLY01 OVLY00 OVL LUT U0 43 OVLU07 OVLU06 OVLU05 OVLU04 OVLU03 OVLU02 OVLU01 OVLU00 OVL LUT V0 44 OVLV07 OVLV06 OVLV05 OVLV04 OVLV03 OVLV02 OVLV01 OVLV00 OVL LUT Y7 57 OVLY77 OVLY76 OVLY75 OVLY74 OVLY73 OVLY72 OVLY71 OVLY70 OVL LUT U7 58 OVLU77 OVLU76 OVLU75 OVLU74 OVLU73 OVLU72 OVLU71 OVLU70 OVL LUT V7 59 OVLV77 OVLV76 OVLV75 OVLV74 OVLV73 OVLV72 OVLV71 OVLV70 Chrominance phase 5A CHPS7 CHPS6 CHPS5 CHPS4 CHPS3 CHPS2 CHPS1 CHPS0 Gain U 5B GAINU7 GAINU6 GAINU5 GAINU4 GAINU3 GAINU2 GAINU1 GAINU0 Gain V 5C GAINV7 GAINV6 GAINV5 GAINV4 GAINV3 GAINV2 GAINV1 GAINV0 Gain U MSB, black level 5D GAINU8 0 BLCKL5 BLCKL4 BLCKL3 BLCKL2 BLCKL1 BLCKL0 Gain V MSB, blanking level, decoder type 5E GAINV8 DECTYP BLNNL5 BLNNL4 BLNNL3 BLNNL2 BLNNL1 BLNNL0 Blanking level VBI 5F 0 0 BLNVB5 BLNVB4 BLNVB3 BLNVB2 BLNVB1 BLNVB0 Null 60 00000000 Standard control 61 DOWNB DOWNA INPI YGS SECAM SCBW PAL FISE Burst amplitude 62 RTCE BSTA6 BSTA5 BSTA4 BSTA3 BSTA2 BSTA1 BSTA0 Subcarrier 0 63 FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00 Subcarrier 1 64 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 Subcarrier 2 65 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 Subcarrier 3 66 FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24 Line 21 odd 0 67 L21O07 L21O06 L21O05 L21O04 L21O03 L21O02 L21O01 L21O00 Line 21 odd 1 68 L21O17 L21O16 L21O15 L21O14 L21O13 L21O12 L21O11 L21O10 Line 21 even 0 69 L21E07 L21E06 L21E05 L21E04 L21E03 L21E02 L21E01 L21E00 Line 21 even 1 6A L21E17 L21E16 L21E15 L21E14 L21E13 L21E12 L21E11 L21E10

1996 Jul 08 13

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 RCV port control 6B SRCV11 SRCV10 TRCV2 ORCV1 PRCV1 CBLF ORCV2 PRCV2 Trigger control 6C HTRIG7 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 HTRIG0 Trigger control 6D HTRIG10 HTRIG9 HTRIG8 VTRIG4 VTRIG3 VTRIG2 VTRIG1 VTRIG0 Multi control 6E SBLBN 0 PHRES1 PHRES0 0 0 FLC1 FLC0 Closed caption/teletext control 6F CCEN1 CCEN0 TTXEN SCCLN4 SCCLN3 SCCLN2 SCCLN1 SCCLN0 RCV2 output start 70 RCV2S7 RCV2S6 RCV2S5 RCV2S4 RCV2S3 RCV2S2 RCV2S1 RCV2S0 RCV2 output end 71 RCV2E7 RCV2E6 RCV2E5 RCV2E4 RCV2E3 RCV2E2 RCV2E1 RCV2E0 MSBs RCV2 output 72 0 RCV2E10 RCV2E9 RCV2E8 0 RCV2S10 RCV2S9 RCV2S8 TTX request H start 73 TTXHS7 TTXHS6 TTXHS5 TTXHS4 TTXHS3 TTXHS2 TTXHS1 TTXHS0 TTX request H end 74 TTXHE7 TTXHE6 TTXHE5 TTXHE4 TTXHE3 TTXHE2 TTXHE1 TTXHE0 MSBs TTX request H 75 0 TTXHE10 TTXHE9 TTXHE8 0 TTXHS10 TTXHS9 TTXHS8 TTX odd request V S 76 TTXOVS7 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVS3 TTXOVS2 TTXOVS1 TTXOVS0 TTX odd request V E 77 TTXOVE7 TTXOVE6 TTXOVE5 TTXOVE4 TTXOVE3 TTXOVE2 TTXOVE1 TTXOVE0 TTX even request V S 78 TTXEVS7 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVS3 TTXEVS2 TTXEVS1 TTXEVS0 TTX even request V E 79 TTXEVE7 TTXEVE6 TTXEVE5 TTXEVE4 TTXEVE3 TTXEVE2 TTXEVE1 TTXEVE0 First active line 7A FAL7 FAL6 FAL5 FAL4 FAL3 FAL2 FAL1 FAL0 Last active line 7B LAL7 LAL6 LAL5 LAL4 LAL3 LAL2 LAL1 LAL0 MSBs vertical 7C 0 LAL8 0 FAL8 TTXEVE8 TTXOVE8 TTXEVS8 TTXOVS8 Null 7D 00000000 Null 7E 00000000 Null 7F 00000000 REGISTER FUNCTION SUB ADDRESS DATA BYTE D7 D6 D5 D4 D3 D2 D1 D0

1996 Jul 08 14

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 I2C-bus format Table 5 I2C-bus address; see Table 6 Table 6 Explanation of Table 5 Notes 1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. Slave Receiver Table 7 Subaddress 3A PART DESCRIPTION S START condition Slave address 1000100X o r 1000110X (note 1) ACK acknowledge, generated by the slave Subaddress (note 2) subaddress byte DATA data byte P STOP condition DATA BYTE LOGIC LEVEL DESCRIPTION UV2C 0 Cb/Cr data are two’s complement. 1 Cb/Cr data are straight binary. Default after reset. Y2C 0 Y data are two’s complement. 1 Y data are straight binary. Default after reset. FMT16 0 Selects Cb, Y, Cr, Y on 8 lines on MP port ( “CCIR 656” compatible). Default after reset. 1 Selects Cb, Cr on DP port and Y on MP port. DISKEY 0 OVL keying enabled for Y, C and CVBS outputs. Default after reset. 1 OVL keying disabled for Y, C and CVBS outputs. CBENB 0 Data from input ports are encoded. Default after reset. 1 Colour bar with programmable colours (entries of OVL_LUTs) is encoded. The LUTs are read in upward order from index 0 to index 7.

1996 Jul 08 15

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Table 8 Subaddress 42 to 59 Notes 1. Contents of OVL look-up tables. All 8 entries are 8-bits. Data representation is in accordance with“CCIR 601” (Y, Cb, Cr), but two’s complement, e.g. for a100⁄100 (upper number) or100⁄75 (lower number) colour bar. 2. For normal colour bar with CBENB = logic 1. Table 9 Subaddress 5A Note 1. Phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256 degrees. COLOUR DATA BYTE (note 1) INDEX (note 2) OVLY OVLU OVLV White 107 (6BH) 0 (00H) 0 (00H) 0 107 (6BH) 0 (00H) 0 (00H) Yellow 82 (52H) 144 (90H) 18 (12H) 1 34 (22H) 172 (ACH) 14 (0EH) Cyan 42 (2AH) 38 (26H) 144 (90H) 2 03 (03H) 29 (1DH) 172 (ACH) Green 17 (11H) 182 (B6H) 162 (A2H) 3 240 (F0H) 200 (C8H) 185 (B9H) Magenta 234 (EAH) 74 (4AH) 94 (5EH) 4 212 (D4H) 56 (38H) 71 (47H) Red 209 (D1H) 218 (DAH) 112 (70H) 5 193 (C1H) 227 (E3H) 84 (54H) Blue 169 (A9H) 112 (70H) 238 (EEH) 6 163 (A3H) 84 (54H) 242 (F2H) Black 144 (90H) 0 (00H) 0 (00H) 7 144 (90H) 0 (00H) 0 (00H) DATA BYTE (1) VALUE RESULT CHPS 68H PAL-B/G and data from input ports 92H PAL-B/G and data from look-up table 82H NTSC-M and data from input ports A4H NTSC-M and data from look-up table

1996 Jul 08 16

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Table 10Subaddress 5B and 5D Notes 1. GAINU = −2.17× nominal to +2.16× nominal. 2. GAINU = −2.05× nominal to +2.04× nominal. Table 11Subaddress 5C and 5E Notes 1. GAINV = −1.55× nominal to +1.55× nominal. 2. GAINV = −1.46× nominal to +1.46× nominal. Table 12Subaddress 5D Notes 1. Output black level/IRE = BLCKL× 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal. 2. Output black level/IRE = BLCKL× 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal. DATA BYTE DESCRIPTION CONDITIONS REMARKS GAINU variable gain for Cb signal; input representation accordance with “CCIR 601” white-to-black = 92.5 IRE(1) GAINU = 0 output subcarrier of U contribution = 0 GAINU = 118 (76H) output subcarrier of U contribution = nominal white-to-black = 100 IRE(2) GAINU = 0 output subcarrier of U contribution = 0 GAINU = 125 (7DH) output subcarrier of U contribution = nominal nominal GAINU for SECAM encoding value = 106 (6AH) DATA BYTE DESCRIPTION CONDITIONS REMARKS GAINV variable gain for Cr signal; input representation accordance with “CCIR 601” white-to-black = 92.5 IRE(1) GAINV = 0 output subcarrier of V contribution = 0 GAINV = 165 (A5H) output subcarrier of V contribution = nominal white-to-black = 100 IRE(2) GAINV = 0 output subcarrier of V contribution = 0 GAINV = 175 (AFH) output subcarrier of V contribution = nominal nominal GAINV for SECAM encoding value =−129 (17FH) DATA BYTE DESCRIPTION CONDITIONS REMARKS BLCKL variable black level; input representation accordance with “CCIR 601” white-to-sync = 140 IRE(1) BLCKL = 0 output black level = 24 IRE BLCKL = 63 (3FH) output black level = 49 IRE white-to-sync = 143 IRE(2) BLCKL = 0 output black level = 24 IRE BLCKL = 63 (3FH) output black level = 50 IRE

1996 Jul 08 17

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Table 13Subaddress 5E Notes 1. Output black level/IRE = BLNNL× 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal. 2. Output black level/IRE = BLNNL× 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal. Table 14Subaddress 5F Table 15Subaddress 61: DATA BYTE DESCRIPTION CONDITIONS REMARKS BLNNL variable blanking level white-to-sync = 140 IRE (1) BLNNL = 0 output blanking level = 17 IRE BLNNL = 63 (3FH) output blanking level = 42 IRE white-to-sync = 143 IRE(2) BLNNL = 0 output blanking level = 17 IRE BLNNL = 63 (3FH) output blanking level = 43 IRE DECTYP RTCI logic 0 real time control input from SAA7151B logic 1 real time control input from SAA7111 DATA BYTE DESCRIPTION BLNVB variable blanking level during vertical blanking interval is typically identical to value of BLNNL DATA BYTE LOGIC LEVEL DESCRIPTION FISE 0 864 total pixel clocks per line; default after reset 1 858 total pixel clocks per line PAL 0 NTSC encoding (non-alternating V component)

1 PAL encoding (alternating V component); default after reset

SCBW 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); wide clipping for SECAM 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); default after reset SECAM 0 no SECAM encoding; default after reset

1 SECAM encoding activated

YGS 0 luminance gain for white − black 100 IRE; default after reset 1 luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black INPI 0 PAL switch phase is nominal; default after reset

1 PAL switch phase is inverted compared to nominal

DOWNA 0 DACs for CVBS, Y and C in normal operational mode; default after reset

1 DACs for CVBS, Y and C forced to lowest output voltage

DOWNB 0 DACs for R, G and B in normal operational mode; default after reset

1 DACs for R, G and B forced to lowest output voltage

1996 Jul 08 18

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Table 16Subaddress 62A Table 17Subaddress 62B Notes 1. Recommended value: BSTA = 102 (66H). 2. Recommended value: BSTA = 72 (48H). 3. Recommended value: BSTA = 106 (6AH). 4. Recommended value: BSTA = 75 (4BH). Table 18Subaddress 63 to 66 (four bytes to program subcarrier frequency) Note 1. Examples: a) NTSC-M: f fsc= 227.5, fllc= 1716→ FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc= 283.7516, fllc= 1728→ FSC = 705268427 (2A098ACBH). c) SECAM: ffsc= 274.304, fllc= 1728→ FSC = 681786290 (28A33BB2H). DATA BYTE LOGIC LEVEL DESCRIPTION RTCE 0 no real time control of generated subcarrier frequency 1 real time control of generated subcarrier frequency through SAA7151B or SAA7111 (timing see Fig.16) DATA BYTE DESCRIPTION CONDITIONS REMARKS BSTA amplitude of colour burst; input representation in accordance with “CCIR 601” white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding BSTA = 0 to 1.25× nominal (1) white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 1.76× nominal(2) white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.20× nominal(3) white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 1.67× nominal(4) ﬁxed burst amplitude with SECAM encoding DATA BYTE DESCRIPTION CONDITIONS REMARKS FSC0 to FSC3 ffsc= subcarrier frequency (in multiples of line frequency); f llc= clock frequency (in multiples of line frequency) see note 1 FSC3 = most signiﬁcant byte FSC0 = least signiﬁcant byteFSC round ffsc fllc

1996 Jul 08 19

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Table 19Subaddress 67 to 6A Note 1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the deﬁnition of Line 21 encoding format. Table 20Subaddress 6B DATA BYTE (1) DESCRIPTION L21O0 ﬁrst byte of captioning data, odd ﬁeld L21O1 second byte of captioning data, odd ﬁeld L21E0 ﬁrst byte of extended data, even ﬁeld L21E1 second byte of extended data, even ﬁeld DATA BYTE LOGIC LEVEL DESCRIPTION PRCV2 0 polarity of RCV2 as output is active HIGH, rising edge is taken when input; default after reset 1 polarity of RCV2 as output is active LOW, falling edge is taken when input ORCV2 0 pin RCV2 is switched to input; default after reset 1 pin RCV2 is switched to output CBLF 0 if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference Pulse that is deﬁned by RCV2S and RCV2E, also during vertical blanking Interval); default after reset if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default after reset 1 if ORCV2 = HIGH, pin RCV2 provides a ‘Composite-Blanking-Not’ signal, for example a reference pulse that is deﬁned by RCV2S and RCV2E, excluding Vertical Blanking Interval, which is deﬁned by FAL and LAL (PRCV2 must be LOW) if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal PRCV1 0 polarity of RCV1 as output is active HIGH, rising edge is taken when input, respectively; default after reset 1 polarity of RCV1 as output is active LOW, falling edge is taken when input, respectively ORCV1 0 pin RCV1 is switched to input; default after reset 1 pin RCV1 is switched to output TRCV2 0 horizontal synchronization is taken from RCV1 port; default after reset 1 horizontal synchronization is taken from RCV2 port SRCV1 − deﬁnes signal type on pin RCV1; see Table 21

1996 Jul 08 20

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Table 21Logic levels and function of SRCV1 Table 22Subaddress 6C, 6D Table 23Subaddress 6D Table 24Subaddress 6E Table 25Logic levels and function of PHRES DATA BYTE AS OUTPUT AS INPUT FUNCTION SRCV11 SRCV10 0 0 VS VS vertical sync each ﬁeld; default after reset 0 1 FS FS frame sync (odd/even) 1 0 FSEQ FSEQ ﬁeld sequence, vertical sync every fourth ﬁeld (PAL = SECAM = 0), eighth ﬁeld (PAL = 1) or twelfth ﬁeld (SECAM = 1) 1 1 not applicable not applicable − DATA BYTE DESCRIPTION HTRIG sets the horizontal trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed increasing HTRIG decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 049H (054H) DATA BYTE LOGIC LEVEL DESCRIPTION VTRIG − sets the vertical trigger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines variation range of VTRIG=0t o3 1 (1FH) DATA BYTE LOGIC LEVEL DESCRIPTION SBLBN 0 vertical blanking is deﬁned by programming of FAL and LAL; default after reset 1 vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz) PHRES − selects the phase reset mode of the colour subcarrier generator; see Table 25 FLC − ﬁeld length control; see Table 26 DATA BYTE FUNCTION PHRES1 PHRES0 0 0 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset 0 1 reset every two lines or SECAM-speciﬁc if bit SECAM = 1 1 0 reset every eight ﬁelds 1 1 reset every four ﬁelds

1996 Jul 08 21

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Table 26Logic levels and function of FLC Table 27Subaddress 6F Table 28Logic levels and function of CCEN Table 29Subaddress 70 to 72 DATA BYTE FUNCTION FLC1 FLC0 0 0 interlaced 312.5 lines/ﬁeld at 50 Hz, 262.5 lines/ﬁeld at 60 Hz; default after reset 0 1 non-interlaced 312 lines/ﬁeld at 50 Hz, 262 lines/ﬁeld at 60 Hz 1 0 non-interlaced 313 lines/ﬁeld at 50 Hz, 263 lines/ﬁeld at 60 Hz 1 1 non-interlaced 313 lines/ﬁeld at 50 Hz, 263 lines/ﬁeld at 60 Hz DATA BYTE LOGIC LEVEL DESCRIPTION CCEN − enables individual line 21 encoding; see Table 28 TTXEN 0 disables teletext insertion 1 enables teletext insertion SCCLN − selects the actual line, where closed caption or extended data are encoded line = (SCCLN + 4) for M-systems line = (SCCLN + 1) for other systems DATA BYTE FUNCTION CCEN1 CCEN0 0 0 Line 21 encoding off 0 1 enables encoding in ﬁeld 1 (odd) 1 0 enables encoding in ﬁeld 2 (even) 1 1 enables encoding in both ﬁelds DATA BYTE DESCRIPTION RCV2S start of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed ﬁrst active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2S = 0F2H (110H) RCV2E end of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2E = 67CH (68AH)

1996 Jul 08 22

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Table 30Subaddress 73 to 75 Table 31Subaddress 76, 77 and 7C Table 32Subaddress 78, 79 and 7C Table 33Subaddress 7A to 7C SUBADDRESSES In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up. DATA BYTE DESCRIPTION TTXHS start of signal on pin TTXRQ (standard for 50 Hz ﬁeld rate = 13FH) values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed TTXHE end of signal on pin TTXRQ (standard for 50 Hz ﬁeld rate = TTXHS + 1402 = 6B9H) values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed DATA BYTE DESCRIPTION TTXOVS ﬁrst line of occurrence of signal on pin TTXRQ in odd ﬁeld TTXOVE last line of occurrence of signal on pin TTXRQ in odd ﬁeld DATA BYTE DESCRIPTION TTXEVS ﬁrst line of occurrence of signal on pin TTXRQ in even ﬁeld TTXEVE last line of occurrence of signal on pin TTXRQ in even ﬁeld DATA BYTE DESCRIPTION FAL ﬁrst active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines FAL = 0 coincides with the ﬁrst ﬁeld synchronization pulse LAL last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines LAL = 0 coincides with the ﬁrst ﬁeld synchronization pulse

1996 Jul 08 23

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Slave Transmitter Table 34Slave transmitter (slave address 89H or 8DH) Table 35No subaddress REGISTER FUNCTION SUBADDRESS DATA BYTE D7 D6 D5 D4 D3 D2 D1 D0 Status byte − VER2 VER1 VER0 CCRDO CCRDE 0 FSEQ O_E DATA BYTE LOGIC LEVEL DESCRIPTION VER − Version identiﬁcation of the device. It will be changed with all versions of the IC that have different programming models. Current Version is 000 binary. CCRDO 1 Closed caption bytes of the odd ﬁeld have been encoded. 0 The bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately after the data has been encoded. CCRDE 1 Closed caption bytes of the even ﬁeld have been encoded. 0 The bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately after the data has been encoded. FSEQ 0 Not ﬁrst ﬁeld of a sequence.

1 During ﬁrst ﬁeld of a sequence (repetition rate: NTSC = 4 ﬁelds, PAL = 8 ﬁelds,

SECAM = 12 ﬁelds. O_E 0 During odd ﬁeld. 1 During even ﬁeld.

1996 Jul 08 24

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Fig.3 Chrominance transfer characteristic 1. (1) SCBW = 1. (2) SCBW = 0. handbook, full pagewidth 6 8 10 12 14 024 MBE737 −12 −18 −30 −24 −36 −42 −54 −48 f (MHz) G v (dB) (1) (2) Fig.4 Chrominance transfer characteristic 2. (1) SCBW = 1. (2) SCBW = 0. handbook, halfpage 0 0.4 0.8 1.6 MBE735 1.2 f (MHz) G v (dB) (1) (2)

1996 Jul 08 25

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Fig.5 Total luminance of Y and CVBS; luminance transfer characteristic 1. handbook, full pagewidth 6 8 10 12 14 024 MGB707 −12 −18 −30 −24 −36 −42 −54 −48 f (MHz) G v (dB) Fig.6 Detailed luminance of Y and CVBS; luminance transfer characteristic 2. handbook, halfpage 02 6 MBE736 4 f (MHz) G v (dB)

1996 Jul 08 26

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Fig.7 Luminance transfer characteristic in RGB. handbook, full pagewidth 6 8 10 12 14 024 MGB708 −12 −18 −30 −24 −36 −42 −54 −48 f (MHz) G v (dB) Fig.8 Colour difference transfer characteristic in RGB. handbook, full pagewidth 6 8 10 12 14 024 MGB706 −12 −18 −30 −24 −36 −42 −54 −48 f (MHz) G v (dB)

1996 Jul 08 27

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Fig.9 Gain of SECAM pre-emphasis. handbook, full pagewidth 0.6 MGB705 G v (dB) f (MHz) Fig.10 Phase of SECAM pre-emphasis. handbook, full pagewidth 0.6 MGB704 ϕ (deg) f (MHz)

1996 Jul 08 28

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Fig.11 Gain of SECAM anti-Cloche. handbook, full pagewidth 0.6 MGB703 G v (dB) f (MHz) Fig.12 Phase of SECAM anti-Cloche. handbook, full pagewidth 0.6 MGB702 ϕ (deg) f (MHz)

1996 Jul 08 29

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 CHARACTERISTICS VDDD = 4.75 to 5.25 V; Tamb = 0 to +70°C; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Supply VDDD digital supply voltage 4.75 5.25 V VDDA analog supply voltage 4.75 5.25 V IDDD digital supply current note 1 − 250 mA IDDA analog supply current note 1 − 110 mA Inputs VIL LOW level input voltage (except SDA, SCL, AP, SP and XTALI) −0.5 +0.8 V VIH HIGH level input voltage (except LLC, SDA, SCL, AP, SP and XTALI) 2.0 V DDD + 0.5 V HIGH level input voltage (LLC) 2.4 V DDD + 0.5 V ILI input leakage current − 1 µA C I input capacitance clocks − 10 pF data − 8p F I/Os at high impedance− 8p F Outputs VOL LOW level output voltage (except SDA and XTALO) note 2 0 0.6 V VOH HIGH level output voltage (except LLC, SDA, and XTALO) note 2 2.4 V DDD + 0.5 V HIGH level output voltage (LLC) note 2 2.6 V DDD + 0.5 V I2C-bus; SDA and SCL VIL LOW level input voltage −0.5 +1.5 V VIH HIGH level input voltage 3.0 V DDD + 0.5 V II input current V I= LOW or HIGH −10 +10 µA VOL LOW level output voltage (SDA) I OL =3m A − 0.4 V IO output current during acknowledge 3 − mA Clock timing (LLC) TLLC cycle time note 3 34 41 ns δ duty factor tHIGH /TLLC note 4 40 60 % tr rise time note 3 − 5n s tf fall time note 3 − 6n s Input timing tSU input data set-up time (any other except CDIR, SCL, SDA,RESET, AP and SP) 6 − ns tHD input data hold time (any other except CDIR, SCL, SDA,RESET, AP and SP) 3 − ns

1996 Jul 08 30

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Notes 1. At maximum supply voltage with highly active input signals. 2. The levels have to be measured with load circuits of 1.2 kΩ to 3.0 V (standard TTL load) and C L = 25 pF. 3. The data is for both input and output direction. 4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 6. For full digital range, without load, V DDA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V. Crystal oscillator fn nominal frequency (usually 27 MHz) 3rd harmonic − 30 MHz Δf/fn permissible deviation of nominal frequency note 5 −50 +50 10 −6 C RYSTAL SPECIFICATION Tamb operating ambient temperature 0 70 °C C L load capacitance 8 − pF R S series resistance − 80 Ω C 1 motional capacitance (typical) 1.5 −20% 1.5 +20% fF C 0 parallel capacitance (typical) 3.5 −20% 3.5 +20% pF Data and reference signal output timing C L output load capacitance 7.5 40 pF tOH output hold time 4 − ns tOD output delay time − 25 ns CHROMA, Y, CVBS and RGB outputs Vo(p-p) output signal voltage (peak-to-peak value) note 6 1.9 2.1 V R I internal serial resistance 18 35 Ω R L output load resistance 80 −Ω B output signal bandwidth of DACs −3d B 1 0 − MHz ILE LF integral linearity error of DACs −± 2 LSB DLE LF differential linearity error of DACs −± 1 LSB SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

1996 Jul 08 31

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Fig.13 Clock data timing. handbook, full pagewidth MBE742 LLC clock output 0.6 V 1.5 V 2.6 V 2.0 V 0.8 V 2.4 V 0.6 V input data output data not valid validvalid not valid validvalid LLC clock input 0.8 V 1.5 V 2.4 V tHIGH tHD; DAT TLLC tHIGH TLLC td tHD; DAT tHD; DAT tSU; DAT tf tf tr tr Fig.14 Functional timing. The data demultiplexing phase is coupled to the internal horizontal phase. The phase of the RCV2 signal is programmed to 0F8h (110h for 50 Hz) in this example in output mode (RCV2S). handbook, full pagewidth MP(n) LLC Cb(0) Y(0) Cr(0) Y(1) Cb(2) RCV2 MGB699

1996 Jul 08 32

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Fig.15 Digital TV timing. The data demultiplexing phase is coupled to the internal horizontal phase. The Cref signal applies only for the 16 line digital TV format, because these signals are only valid in 13.5 MHz. The phase of the RCV2 signal is programmed to 0F2h (110h for 50 Hz) in this example in output mode (RCV2S). handbook, full pagewidthLLC CREF VP(n) Y(0) Cb(0) Y(1) Cr(0) Y(2) Cb(2) Y(3) Cr(2) Y(4) Cb(4)DP(n) RCV2 MBE739 Fig.16 RTCI timing. (1) Sequence bit: PAL = logic 0 then (R− Y) line normal; PAL = logic 1 then (R− Y) line inverted. NTSC = logic 0 then no change. (2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems. (3) Only from SAA7111 decoder. (4) SAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit. handbook, full pagewidth 128 14 19 67 6801 0 021 RTCI HPLL increment FSCPLL increment (4) H/L transition count start 4 bits reserved valid sample invalid samplenot used in SAA7182/83 sequence bit (1)reset bit (1) 5 bits reserved 8/LLC reserved (2) MGB700 LOW time slot:

1996 Jul 08 33

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 Teletext timing Time tFD is the time needed to interpolate input data TTX and inserting it into the CVBS and Y output signal, such that it appears at t TTX = 10.2µs after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ in order to deliver TTX data. Since the pulse representing the TTXRQ signal is fully programmable in duration and rising/falling edges (TTXHS and TTXHE), it always can be ensured that the TTX data is inserted at the correct position of 10.2µs after the leading edge of outgoing horizontal synchronization pulse. Time t TTXWin is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits (maximum) at a text data rate of 6.9375 bits/s. The insertion window is not opened if the control bit TTXEN is zero. T ELETEXT PROTOCOL The frequency relationship between TTX bit clock and the system clock LLC for 50 Hz field rate is given by the relationship of line frequency multiples, which means 1728/444. Thus 37 TTX bits correspond to 144 LLC clocks, each bit has a duration of nearly 4 LLC clocks. The chip-internal sequencer and variable phase interpolation filter minimizes the phase jitter, and thus generates a bandwidth limited signal, which is digital-to-analog converted for the CVBS and Y outputs. At the TTX input, bit duration scheme repeats after 37 TTX bits or 144 LLC clocks. The protocol demands that TXX bits 10, 19, 28 and 37 are carried by three LLC samples, all others by four LLC samples. After a cycle of 37 TTX bits, the next bits with three LLC samples are bits 47, 56, 65 and 74; this scheme holds for all succeeding cycles of

37 TTX bits, until 360 TTX bits (including 16 run-in bits)

are completed. For every additional line with TTX data, the bit duration scheme starts in the same way. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion. Fig.17 Teletext timing diagram. handbook, full pagewidth tTTXWintTTX tPD tFD CVBS/Y TTX TTXRQ textbit #: 1 2 3 4 5 6 7 8 9 10 11 434 434 1/LLC 1/LLC 12 13 14 15 16 17 18 19 20 21 22 23 24 MGB701

1996 Jul 08 34

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183

APPLICATION INFORMATION

dbook, full pagewidth µH nF pF X1

27.0 MHz

VDDA4VDDA5VDDA6VDDA7IY/C/CVBSIRGBXTALOXTALI VDDA3 100 nF pF kΩ kΩ 100 nF VDDA2 VSSA VDDA1 100 nF VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD VDDD2100 nF VDDD3100 nF VDDD4100 nF VDDD5100 nF VDDD6100 nF VDDD7100 nF VDDD8100 nF VDDD9100 nF VrefL1 VrefH1 VrefH2 VrefL2 VSSD1 to VSSD9 100 nF 100 nF 3, 15, 24, 30, 39, 42, 51, 79, 81 75 Ω RED61 VSSA 100 nF VSSA 100 nF 100 nF VSSA 100 nF VSSA 100 nF VSSA 100 nF VSSA VSSA 100 nF VSSA 75 Ω GREEN58 VSSA 75 Ω BLUE55 VSSA 75 Ω CVBS73 VSSA 75 Ω Y71 VSSAVSSA 75 Ω CHROMA69 +5 V analog 52 53 75 76 44 45 63 68 74 72 70 64 60 57 54 digital inputs and outputs +5 V digital SAA7182 SAA7183 (3) MGB698 Fig.18 Application environment of the EURO-DENC. (1) Typical value. (2) For 100/100 colour bar. (3) Philips 12NC ordering code: 4312 065 02341.

1996 Jul 08 35

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 PACKAGE OUTLINE REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. SOT189-2 5474 12 32 detail X (A )3 bp w M A 1 A A 4 Lp β k1 k Xy e E B DH EH v M B D Z D A Z E e v M A pin 1 index 0 5 10 mm scale 92-11-17 95-03-11 PLCC84: plastic leaded chip carrier; 84 leads SOT189-2 UNIT A A eH E Zywv β mm 4.57 4.19 0.51 3.30 0.53 0.33 0.021 0.013 1.27 0.51 2.16 45o 0.18 0.100.18 DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) D (1) 29.41 29.21 H D 30.35 30.10 EZ 2.16 Db1 0.81 0.66 k 1.22 1.07 0.180 0.165 0.020 0.13 A 3 0.25 Lp 1.44 1.02 0.057 0.040 1.158 1.150 29.41 29.21 1.158 1.150 1.195 1.185 30.35 30.10 1.195 1.185 eEeD 28.70 27.69 1.130 1.090 28.70 27.69 1.130 1.090 0.0850.032 0.026 0.048 0.042 Ee inches De

1996 Jul 08 36

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Reﬂow soldering Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250°C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering isnot recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed:

A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260°C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150°C within 6 seconds. Typical dwell time is 4 seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320°C.

1996 Jul 08 37

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I 2C COMPONENTS Data sheet status Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability. Where application information is given, it is advisory and does not form part of the speciﬁcation. Purchase of Philips I 2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

1996 Jul 08 38

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 NOTES

1996 Jul 08 39

Philips Semiconductors Preliminary speciﬁcation Digital Video Encoder (EURO-DENC) SAA7182; SAA7183 NOTES

Internet: http://www.semiconductors.philips.com/ps/ (1) SAA7182_83_2 June 26, 1996 11:51 am Philips Semiconductors – a worldwide company © Philips Electronics N.V. 1996 SCA50 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 83749, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 São Paulo, SÃO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria:Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil:see South America Bulgaria:Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 708 296 8556 China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 615 800, Fax. +358 615 80920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 52 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. +30 1 4894 339/911, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 648 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Middle East: see Italy Printed in The Netherlands 657021/1200/02/pp40 Date of release: 1996 Jul 08 Document order number: 9397 750 00951

Product Information

AN7183 specifications and overview.

Summary

Digital Video Encoder EURO-DENC 1996 Jul 08

Description

Digital Video Encoder EURO-DENC 1996 Jul 08

Source title AN7183 Datasheet(PDF) - NXP Semiconductors

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