AN642 MAXIM | Alldatasheet
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communications, DSOs and fast data acquisition systems. oscilloscopes, and high-speed data-acquisition systems. isolation, that are incorporated in Maxim's lower performance GST-1 process. Figure 1. This simplified block diagram shows how the MAX104 integrates a high-bandwidth T/H amplifier with a high-speed quantizer.
Figure 2. The MAX104's full-power bandwidth is shown as a function of input amplitude. reference amplifier. The negative input of this amplifier is internally tied to the reference ground (GNDR). needed with REFOUT connections. digital output codes occur at an input of 0V.
Figure 5. This FFT was measured with the MAX104 undersampling an analog input frequency of 1GHz at unaffected by clock signal amplitudes from 100mV to 1V. connected to the ECL VTT voltage (nominally -1.3V). three demux modes (DIV1, DIV2, or DIV4).
www.maxim-ic.com/an642 Page 5 of 7 ports on the rising edge of the data-ready clock. The DIV1 nondemultiplexed (nondemux) mode supports operation of the MAX104 at sampling speeds up to 500 megasamples per second (Msps). In this mode, the internal demux is disabled and the sampled data are presented to the primary output port only. To consume less power, the auxiliary port can be shut down by two separate inputs (AUXEN1 and AUXEN2). To save additional power, the external 50/g87 termination resistors connected to the logic PECL power supply (V CCO at -2V) can be removed from all auxiliary output ports. In a special decimated, demuxed output mode (DIV4), the MAX104 discards every other input sample and outputs data at one quarter of the input sampling rate. This mode is particularly useful for system debugging using the resulting slower output data rates. With an input clock of 1GHz, the effective output data rate will be reduced to 250MHz in this mode. Along with the on-chip demux, the MAX104 provides internal demux reset circuitry that enables multiple ADCs to be synchronized for proper interleaving operation. In addition, the reset signal appears as an external demux reset output for synchronizing external demuxes. Furthermore, the MAX104 provides latched, differential PECL outputs, which make the ADC ideal for driving controlled low-impedance lines. The PECL outputs can be powered from +3V to +5.25V DC supply voltages. PECL outputs on the MAX104 are typically terminated with a parallel 50 /g87 termination resistor into V TT = VCCO - 2V (the PECL termination voltage). Primary port outputs are labeled P0-P7 (LSB to MSB), while the auxiliary ports are labeled A0-A7. Outputs DREADY+ and DREADY- are data-ready true and complementary outputs, supplying the data clock. These signal lines are used to latch the output data from the primary to the auxiliary output ports, as well as supplying a synchronous clock for downstream digital circuitry, such as demuxes or high-speed memory devices. Data changes are triggered on the rising edge of the DREADY clock. Outputs OR+ and OR- are overrange true and complementary outputs. Outputs RSTOUT+ and RSTOUT- are the reset-out true and complementary outputs provided to reset downstream circuitry. The MAX104 is supplied in a 192-contact enhanced-super-ball-grid-array (ESBGA) package from Amkor/Anam (Chandler, AZ) that measures 25mm x 25mm. The MAX104 provides an on-board 1:2 demux function, slowing data rates to 500Mbps supplied on two ports. The package features 50 /g87 microstrip interconnects from the solder balls to the bond wires, which support high input/output (I/O) operating frequencies. In addition, the package enables a large number of solder balls to be dedicated to power supplies and ground. With a thickness of only 1.4mm, this 1.27mm pitch ESBGA package saves circuit-board space while providing excellent thermal performance. In many applications, the MAX104 can be used without a heat sink. The MAX104 is ideal for many applications where high sampling rates are required to either capture an instantaneous value from a fast-moving signal, such as in a high-speed data acquisition (DAQ) application, or to digitize a complex high-frequency, high-bandwidth signal. One example of this is in wideband digital receivers for digital base stations. In this case, signal bandwidths that exceed 300MHz are allowed to pass through the receiver intermediate-frequency (IF) stages to the demodulator. At this point, the information bandwidth may be filtered and amplified before being presented to the ADC front end. This approach, known as block or direct downconversion, requires that the input bandwidth of the ADC be sufficiently flat to prevent distortions and nonlinearities in the resulting digital representation. The high-speed data stream thus created is then presented to a digital demodulator which separates the individual channels and extracts the modulated information. Applying the ADC The exceptional SNR and spurious-free dynamic-range (SFDR) performance of the MAX104 at input frequencies below (e.g., at 125MHz and 250MHz) and well above the Nyquist frequency (e.g., operating at
options of lower and even higher sampling speeds. its error magnitude to no more than 1LSB. displays parameters as low as ±0.25LSB (Figures 6, 7). Figure 6. The MAX104's typical integral nonlinearity.
Figure 7. The MAX104's typical differential nonlinearity. A similar version of this article appeared in the March 1999 issue of Microwaves and RF.