AN628

AN628 STMICROELECTRONICS | Alldatasheet

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the mains, reducing the bulk capacitor peak current and the harmonic disturbances. phase with the input line voltage. and the switch. This minimizes line noise and the line spikes will be absorbed by the inductor. Figure 1. L4981 Block Diagram

THE L4981 PFC CONTROLLER IC The L4981 integrated circuit is a continous mode average current controller with several specific functions for active power factor correction. It can operate in high quality, medium/high power conversion range and provides all the necessary features to achieve a very high power factor, up to 0.99. Thanks to the BCD technology used, operative switching frequency higher than 200kHz can be used. The L4981 can be used in systems with universal input mains voltage without any line switch. This new PFC offers the alternative of synchronization working at fixed frequency (L4981A), or working in mod- ulated frequency (L4981B) to optimize the size of the input filter. Both devices control the conversion in average current mode PWM to maintain a sinusoidal line current without slope compensation. MAIN FEATURES: ■ Switching frequency higher than 200 kHz. ■ Under Voltage Lockout with hysteresis and programmable turn-on threshold. ■ Overvoltage and Overcurrent Protection. ■ Precise (2%) on chip Reference externally available. ■ Input/Output Synchronization (only for L4981A). ■ Feed Forward Line and Load regulation. ■ Universal input mains. ■ Average current mode PWM. ■ High Output Current totem pole driver. ■ Low Start-up supply current. ■ Soft Start. P.F.C. BOOST TOPOLOGY OPERATION The A.C. line voltage is rectified by a diode bridge and the rectified voltage delivered to the boost converter. The boost converter section, using a PWM switching technique, boosts the rectified input voltage to a D.C. controlled output voltage (VO). The section consists of a boost inductor (L), a controlled power switch (Q), a boost diode (D), an output capacitor (CO) and, obviously, a control circuitry. Referring to the time-variable mains voltage (sine waveform), the converter produces a boost inductor average current like the rectified input voltage, changing continuosly the duty-cycle of the active switch (Q). The boosted D.C. voltage is controlled to a programm ed value, higher than the maximum input instantaneous voltage (VIpk). Referring to the main currents shown in fig.2 schematic, the simplified formulae are (assuming: power efficiency = 1; output ripple voltage = 0; high frequency inductor ripple current = 0): 1) Peak inductor (L), switch (Q) and diode (D) currents 2) RMS inductor current ILpk IQpk IDpk 2 PO Vlpk ILrms 2 PO Vlpk

Figure 2. 3) RMS switch current 4) Average diode current IDavg = IO 5) RMS diode current 6) Total RMS capacitor (CO) current 7) RMS twice line frequency capacitor current 8) RMS high frequency capacitor current The figure 3 shows the above mentioned quantities, normalized to the D.C. output current (I O), plotted versus VIpk / VO ratio. Moreover, the ILpk · ILrms normalized to IO2 value, related to the inductor energy (I2 · L), is plotted in the diagram (dotted line). This last plot gives an idea on the heavy increase of the inductor size operating with large input voltage range. Obviously, in real application the efficiency is less than 100% ( η < 1). The output voltage ripple, related to the output capacitor (CO) is a parameter to be considered. The inductor high frequency current ripple (∆IL) is anoth- er parameter affected by the inductor value (L), the switching frequency (f sw) and the delivered power (PO). L IL IQ ID IO D D94IN119 QCONTROLLER Cin IC CO LOAD IQrms PO Vlpk

16 V lpk⋅

16 V O⋅

IC2 f() rms IO ICh f() rms IO

PWM block. This block, comparing the sawtooth produced by the oscillator, with the reference signal from the C/A output, modulates its output signal duty-cycle. Its output, by the l ogic and driver sections, allows the controlled switch (Q) to modulate the inductor current. Logic block. Controls the flow from the PWM and the output with the Auxiliary function signals and soft start. Driver block. The driver supplies the gate current to turn on and off the power switch (Q). It delivers up to 1A peak current to allow high switching frequency applications. Aux functions. The Auxiliary functions allow to avoid over stress on power components of the application. Power supply block. This circuitry delivers the internal supply and references, recognizes the Undervoltage and Stand-by conditions to save consumption. P.F.C. BOOST DESIGN CRITERIA L4981 PIN DESCRIPTION AND BIASING CIRCUITRY. Pin 1. P-GND (Power stage ground). This pin, on the pc-board, has to be connected close the external Mosfet source. Pin 2. IPK (Overcurrent protection input). The current limitation is obtained with an internal comparator that holds down the output driver when the voltage at IPK input goes down to zero. In the L4981A, to preset the IPK input there is an internal current source (Iipk) of typically 85µA. The maximum peak current (Ipk) can be programmed connecting (see fig. 6) a single resistor (R ipk) between this pin and the sense resistor (R S): In the L4981B, to preset the IPK input, an auxiliary resistor (Raux), connected from the VREF pin to the IPK pin, is required. The maximum peak current (Ipk) can be programmed choosing (see fig. 6) the resistances Raux and Ripk: Where: Note: If used with the L4981A, the auxiliary resistor avoids that the current source spread affects the precision of the protection simply getting an auxiliary current (I aux) much higher than Iipk. Ripk RS Ipk⋅ Iipk Ripk RS Ipk⋅ Iaux Iaux VVREF Raux

boost inductor size, etc.) and normally t he value amounts at some tens of msec. voltage (VO). This pin has to be connected with a com pensation network to the pin 14 (see fig.16). Figure 16. Figure 16a. loop gain can be splitt in two separated blocks. value less than 2.5% of the effective E/A output swing voltage (V VAOUT = 3.82V) could be chosen to fix the C r. where: Ka = 1/60 for 50Hz and 1/72 for 60Hz mains frequency.

The voltage open loop gain contains two poles in the orig in, then stability problem can arise. Connecting the resistor (Rr) in parallel to the capacitor C r to shift the E/A pole from the origin to 1/(R r · Cr), the stability is en- sured. The crossover frequency fc can be calculated by G pw · Gea\` = 1 and therefore: To allow the highest DC gain maintaining a phase margin of at least 22°, the Rr maximum value is imposed as: The output filter capacitor value (CO) is related to the output voltage filtering (see Power section design). Pin 14. VFEED (Error amplifier input). This pin (see fig. 16), connected to the boosted output voltage through a divider, allows the output D.C. voltage regulation. Neglec ting the contribution of the E/A feedback resistor (R r), the 5.1V reference and the output DC voltage (V O) define the ratio between R1 and R2: To be considered that the R1, togheter with the f eedback network(see pin 13 description) define the E/A gain. The R1/Rr ratio affects the load regulation (lower output current increases the output voltage) with the following relation: where: VOmax is the maximum output voltage variation due to the E/A gain reduction and load variation. The R1 and R2 will be chosen in the high precision class: Pin 15. P-UVLO (Programmable supply undervoltage threshold). An internal divider (between pin 19, pin 15 and ground) and an internal comparator with a threshold voltage of 1.28V fixes the default turn-on and turn-off 15.5V and 10V levels of the supply section (see fig. 17). Using an external divider (R H and RL) it's possible to change the supply thresholds: R H fixes the hysteresis, R L fixes the turn-on threshold. To design a divider for a given supply threshold, is useful know (see fig. 17), the typical resistor value, useful to design the external divider, are: R1 = 394k, R2 = 88k and R3 = 58k. Anyway, in fig. 17a/b a diagram with threshold values and a table, useful for a fast choice of RH and RL are shown. For DISABLE function see Appendix B. Gpw PO XCO⋅ PO fc PO  1 ⋅= Rr 2.75 VO VOmax∆ Vea∆ R1⋅ Rr

Figure 17. Pin 16. SYNC (In/Out synchronization). Only for L4981A, this function allows the device to be synchronized with other circuits of a system (see fig.18a). When the device is externally synchronized, the external clock has to satisfy these conditions: the signal amplitude must cross the threshold value (3.5V), the frequency has to be slightly higher than that programmed by the R-C constant (see pin 18) and the pulse width has to be at least 800 nsec. If the device has to synchronize other circuits, the signal delivered by this pin is a positive pulse of 4.6V (0.5mA) and the pulse duration is equal to the sawtooth falltime. The L4981B uses this pin to perform another function. If t he application does not use the SYNC function, it is preferrable to focus the EMI filtering problem using the B version. Pin 16, named FREQ-MOD in B version, al- lows to change the switching frequency in order to spr ead the energy content over a wider spectrum range. To perform the frequency modulation (see fig.18b), the pin must be connected, through a resistor (R fm), to the rectified line voltage. This allows to change dinamically (cycle by cycle) the (C OSC) charge and the discharge currents that define the ramp slopes of the oscillator sawtooth. The effect of the resistor produces the frequency change (see fig.18c) between the nominal value (f sw) and its minimum value which occurs when the input volt- age reaches the peak value (V Ipk). The total frequency variation (see also pin 17 and 18) can be estimated by the formula: UVLO 1.28V P-UVLO RH RL D94IN066A R2 R3 RH = RL * 6.8 VCC ON VCC OFF RH RL 11V 10V 82k Ω 12kΩ 12V 10.1V 220k Ω 33kΩ 13V 10.5V 430k Ω 62kΩ 14V 10.8V 909k Ω 133kΩ 14.5V 10.9V 1.36M Ω 200kΩ 15V 11V 2.7M Ω 390kΩ a) b) Programmable Under Voltage VCCON and VCCOFF vs. RL fsw∆ fsw VIPK Rosc⋅

where: Rfm is the programming current resistor. K is a constant value = 0.1157 for R value in K Ω and fSW in KHz. A typical 20% can be a good compromise. Figure 18. fsw∆ fsw Vl 0.8 0.4 0.2 0 45 90 135 Electrical degrees 180 0.8 0.4 0.2 fsw 1.28V I COSC 10I 200I 8.5V 1/VMRS Ifm FREQ-MOD D94IN065A ROSC COSC ROSC Rfm

2 POLES

Modulation Frequency Normalzed in an Half Cycle of the Mains Voltage

The maximum discharge current of Id = 12mA, this means a minimum R osc value of 22KΩ. 17) and therefore the switching frequency. The typical ramp valley-peak voltage (V srp) is fixed to 5V. Figure 19. Oscillator Diagram shoot and to control the dI/dt of the switch. completely transferred to the output (bulk) capacitor.

Figure 20. Figure 21. The energy transferred from the boost inductor to the bulk capacitor in each cycle is: where: L = Boost Inductance ILp = Inductor Peak Current (ILt + ∆IL/2) ILv = Inductor Valley Current (ILt - ∆IL/2) ILt = Instantaneous Line Current (ILp + ILv)/2 ∆IL = Twice Inductor Current Ripple (ILp - ILV) Because the instantaneous line current (ILt) that corresponds to the average inductor current in the cycle, draws a full rectified (half- sinusoidal) waveform, it is usef ul to refer to the AC line RMS and peak parameters: where: Irms = ILrms = PI/VIrms is the line current PI = PO/η is the input power η is the power yeld. E/cycle 1 2---LI Lp

2 ILv

ILpk 2I Lrms⋅=

The power transferred by the inductor in each cycle where: ton = δ / fsw and δ = (VO - VIt) / VO For a given L, the twice ripple current ∆IL is the quantity associated to the transferred energy and can be calcu- lated as a certain percentage of the ILpk inductor current. If the maximum Vlpk value is higher than the VO/2, the maximum ∆IL occours when VIt = and its value is If the Vlpk maximum value does not reach VO/2 voltage value, the maximum ∆IL is reduced and its value is : In continuous mode operation, an acceptable curent ripple level (K r) can be considered between 10% to 35%. Smaller current ripple on the inductor involves smaller noise on the rectified main bus reducing the input filter size; but the ripple reduction will impose an increase of the boost inductor. The high voltage, the flux density and the frequency range make the standard high frequency ferrite the most useful material in P.F.C. applications. To avoid the core saturation, related to the high permeability materials, it is necessary built an air-gap in order to allow an adequate magnetic force range (H+Hgap). An easy approach, is to have an approximated minimum value of core size that could be used to perform the conversion: Volume where : K = specific energy constant. L = Boost inductor value in H. The specific energy constant (K), mainly depends on the ratio between the gap length (l gap) and the effective length (leff) of the magnetic core set and on the maximum ∆B swing. Practically can be used to get the minimum volume of the core set in cm 3. After the minimum core-set size is estimated, the suitable type will be selected with technical and economic evaluations. Next step will be the design of the coil parameters. The above mentioned formula Pt LI Lt IL∆⋅⋅ ton IL∆ Vlt VO Vlt–()⋅ VO ILm a x()∆ VO ILm a x()∆ Vlpk VO Vlpk–() Kr IL∆ KLI Lpk ILpk IL∆ K1 4 Ieff Igap POt LI Lt IL∆⋅⋅ ton

if referred to the magnetic path, can be rewritten : where : Ae = effective area of the core section. l eff = effective magnetic path length. ∆B = deviated magnetic flux density. H = magnetic field strength. The ratio between the ferrite and the air path magnetic permeability, depends on the ferrite materials. Core ma- terials for power application (such as B50/51), have a initial permeability value about 2500 times that of air. This means that, above a certain air-gap length percentage, it is possible to neglect the leff (length of the core) sim- plifing the calculation e.g. if a 1% of air-gap length, respect to the core lenght value is used, the error introduced is about 4%. Rewriting equating to and simplifing Because: and finally: This simplified relation is much easier to use than the complete one: After N has been defined, it's necessary to check the core for saturation of the magnetic path (rated N · Imax vs. Air-gap on ferrites databook). If the check is too close the rated limit, an increase of the lgap (gap lengh) and a new calculation will be necessary. Copper losses R L · I2Lrms and former's winding space available will be con- sidered for the wire selection. POt Ae I eff H B∆ ton POt Ae I eff H B∆ ton POt Ae I gap Hgap ton POt LI Lt IL∆⋅⋅ ton Igap Hgap⋅ NI Lt and B ∆⋅≈µ 0 H∆⋅= H∆ N IL∆ Igap N LI gap⋅ N L µo Ae π 4--- Igap⋅+ Ieff

An auxiliary winding can be used just to get a low cost supply for the I.C. It will be a low cost thin wire coil will be used and the number of turns is the only parameter to define. Input Bridge The input diodes bridge can be standard off-line, slow-recovery and low cost devices. The device selection con- siders just the input current (Irms) and the thermal data. Input Capacitor The input filter capacitor (CIN) has to sustain the input instantaneous voltage (VIt), with an imposed voltage rip- ple, during the turn-on (ton) time of the Mosfet. The worst conditions will be found at the minimum rated input voltage V Irms(min). The maximum high frequency voltage ripple (r = ∆VI / VI) has to be imposed: Where: Kr is the current ripple coefficient. r = 0.02 to 0.08. The CIN maximum value is limited to avoid current distortion. Output Bulk Capacitor The choice of the output bulk capacitor (C O), mainly depends on the electrical parameters that affect the filter performances and also on the subsequent application. The D.C. output voltage and overvoltage, the output power and voltage ripple are the first parameters to con- sider in all applications. The RMS capacitor ripple current I C(2f)rms = I o/ and so, the output voltage ripple (∆VO) will be: With a low ESR capacitor can be simplify: Although the ESR, normally does not affect the output ripple parameter, it has to be considered in power losses account both for the rectified mains frequency and the switching frequency. If the application (i.e. computer supply) has to guarantee a specified Hold-Up time (tHOLD), the capacitance size- ing criteria will change: The CO has to deliver the supply energy for a certain time and a specific dropout voltage. where: VO_min = minimum output voltage value (normally at the maximum load conditions) CIN Kr Irms VO∆ IO CO IO PO CO 2P OtHOLD⋅ VO_min

2 Vop_min

Vop_min = minimum output operative voltage before the 'power fail' detection. Coss is the Drain capacitance at VDS = 25V. Cext is the external layout stray capacitance. Prec is the contribution due to the diode recovery. To reduce the crossover losses a snubber network can be used. this specifications, and are expecially suitable for this application. The sense resistor produces the signal for the current feedback loop and for the overcurrent protection circuit. noise ratio. In much high power applications, it could be considered the magnetic sensing approach (see fig. 22). Figure 22. Magnetic Sense

a typical "low-medium range power" PFC application. – Wide range mains; V INrms = 88 Vac to 264 Vac. – Pre-Regulated DC output voltage; V O = 400 V. – Rated output power; P O = 200W. The design starts fixing the operating conditions. The circuit in fig. 23 can be proposed as reference for medium range power PFC application. Figure 23. Low-medium Power Typical Application (VO = 400V; PO = 200W)

The input capacitor, placed across the rectified mains, must be considered as part of the EMI filter. The advan- tage, in placing this part after the mains rectification, is the shunt effect for the high frequency current in order to avoid it to flow throws the diodes of the bridge due to the poor recovery characteristic. On the other side, the value of this capacitor must to be held as low as possible because the inherent DC voltage content affects the harmonic distortion. With 220nF, the high frequency is filter enough and the introduced DC level can be considered not significant at reasonable load. Output capacitor For the output capacitor selection, it can be consider just the output voltage ripple. Choosing 100µF/450Vthr 100/120Hz ripple is ± 8Vac Instead, if the pre regulated voltage bus must ensure enough energy for Hold-up requirements (i.e. the energy is delivered to a power supply system), the Coot value will be increased to around 180 µF. Sense resistor The sense resistance (Rest) is selected considering both, the signal level and the power dissipation parameters. Using ±70mΩ, the sense signal is good enough to be managed by the current loop. On the other side, the max- imum power dissipation will be: Pros = RS · (Ilrms2 + Ilhfrms2) ≤ 0.5W Where Alarms max. = 2.50A Power Mos The Mosfet breakdown voltage is imposed; Bvdss ≥ Vout + Dvout + margin = 500V. The Rdson is selected taking in to account the conduction power dissipation. The formula for calculation is: Pon_max = Iqrms2 · Rdon Adding the switching (and the capacitive) losses we can estimate 8W to 10W total power dissipation. Boost Diode The continuous current mode of operation, suggest using an Ultra-fast reverse recovery diode. The STMicro- electronics TURBOSWITCH™ family offers a good solution for this kind of application. Boost Inductor The inductor design starts defining the L value that is a function of the switching frequency and the accepted current ripple. In this design, we suggest an inductor value L = 0.75mH that can be realized using an ET3411 gapped set-core ferrite.

The results, concerning the described circuit, have been te sted. And the result are shortly here reported: DEMO-BOARD: Design process and Evaluation results In order to provide a powerful tool for the complete evaluation of the L4981, It is available a populated Demo- Board. The design process and the description for the demo, is here described. The demo has been designed to operate in wide range mains and the size and is finalized for a "medium-high" output power range. Let us start fixing the overall target of the application. Electrical target specification: – Wide range mains; V INrms = 88 to 264 Vac. – Regulated DC output voltage; V O = 400 V. – Rated output power; P O = 360W in any mains condition. – Target efficiency ≥ 90% in nominal load conditions. Chosen operation conditions of the application – The rectified mains (100/120Hz) full load voltage ripple is ± 7-8 V (peak to peak) this is achieved using an output capacitor Cout = 220Uf/450V – The maximum current ripple, in nominal load condition, is selected to be about 20%. This can be ob- tained using the boost inductor L = 0.55mH and setting the switching frequency at 100kHz. ## – The Over Voltage Protection has been set at V out + 58V The demo is capable to deliver around 400W output power; anyway in order to limit the temperature, the rated power is limited to 360W. The schematic is shown in fig 24. Vi f Pi PF A - T H D H 3H 5H 7H 9 VO ∆VO PO η

Figure 24. Demo Board Circuit (VO = 400V; PO = 360W) current, due to the recovery of the boost diode (D4), and the associate noise emission. ative spike thus avoiding the Breakdown activation of the booster diode D4. D7, C14 and R18 will clamp the energy of L2 at the turn off edge of the Mos. inrush current limiter NTC is placed between the cathode of the boost diode and the bulk capacitor C15. especially at minimum mains value. efficient anyway; it can be inadequate when the output power is reduced down to less than 5W. Here follows some comment concerning the design and the selection of the power parts of the demo.

2.5 V+ BUS=400V

The demo is not provided with complete dedicated EMI filter. At the input side, two parts compose the capacitor; the first (Cf.) is placed across the AC input of the bridge and the second one (C1) is tied to the rectified mains. The advantage, of this configuration is the minimization of the DC content in placing a low value after the mains rectification (C1), just to filter the high frequency. The capacitor Cf placed in the AC side must be considered as part of the EMI filter. Output capacitor selection For the output capacitor selection, it can be consider just the output voltage ripple. Choosing Co = 220µF (450V), the maximum rectified mains ripple is: Sense resistor selection The sense resistance is set at 50mOhm (Rs = 3 · 0.15Ohm//) maximum power dissipation (@ 88Vac mains and 360W) will be: PRs(max) = RS · (Ilrms2 + Ilhfrms2) = 1.04W Where: Ilrms max. = 4.55A Power Mos In the selection of the power switch, it has been prefe rred to share the thermal dissipation in two separate TO220 packages. This is a good solution because the size of the heath sinkers can be limited. The breakdown voltage is imposed = 500V. Considering the On resistance (@ T j = 100°C) = 320 mΩ the formula for the dissipated power calculation are: Conductive losses P_On(max) = IQ(max)2 · Rdon = 3.9 · 0.32 = 4.9W. Adding the capacitive (about 2.5W) and the switching losses (as low as 2-3 W, thanks to the snubber) we can estimate 10 to 12W total power dissipation at lower mains value. Boost Diode The 8A 600V chosen Turbuswitch fits well with the application. The power dissipated in the boost diode is about 1.4W. Boost Inductor The 0.55mH chosen inductor value allows a low ripple (23%) of its current; moreover, there is enough room (in the industrialization phase) to reduce the switching frequency holding an acceptable current ripple (e.g. reduc- ing the frequency to 75 kHz the current ripple will be held within 30%. In this design, the coil has been realized with a gapped set-core ferrite E42*12*15. The results that can expect, realizing the described circuit, has been tested. And the result are shortly reported from Table 1 to Table 6. The PCB and component Layout can be seen in figgs 25, 26 and 27 (The Gerber files of the PCB are available on request). πo

Figure 27. P.C.B. Solder Side (Dimensions 88 x 150mm) Table 1. Maximum power range at 110Vac – Power-mos (Q1+Q2) dissipated power = 9.6W. – Bridge (B1) dissipated power = 6.3W. – Boost turbo-diode (D4) dissipated power = 1.6W. – NTC dissipated power = 1.1W. Vmains Pout Vout Pin THD PF Eff.

Table 2. Maximum power range at 220Vac – Power-mos (Q1+Q2) dissipated power = 7.1W. – Bridge (B1) dissipated power = 4W. – Boost turbo-diode (D4) dissipated power = 1.3W. – NTC dissipated power = 0.8W. Table 3. Nominal power range at 110Vac – Power-mos (Q1+Q2) dissipated power = 9.3W. – Bridge (B1) dissipated power = 5.7W. – Boost turbo-diode (D4) dissipated power = 1.5W. – NTC dissipated power = 1W. Table 4. Nominal power range at 220Vac – Power-mos (Q1+Q2) dissipated power = 6.9W. – Bridge (B1) dissipated power = 3.5W. – Boost turbo-diode (D4) dissipated power = 1.3W. – NTC dissipated power = 0.8W. Vmains Pout Vout Pin THD PF Eff. Vmains Pout Vout Pin THD PF Eff. Vmains Pout Vout Pin THD PF Eff.

Table 5. Half power range at 110Vac – Power-mos (Q1+Q2) dissipated power = 7.5W. – Bridge (B1) dissipated power = 3.7W. – Boost turbo-diode (D4) dissipated power = 1.1W. – NTC dissipated power = 0.7W. Table 6. Half power range at 220Vac – Power-mos (Q1+Q2) dissipated power = 5.64W. – Bridge (B1) dissipated power = 1.9W. – Boost turbo-diode (D4) dissipated power = 0.88W. – NTC dissipated power = 0.52W. look at some switching waveform. In figure 28, it is depicted the power drain voltage and the current measured in L2 (aux. Inductor) . power dissipated inside the switch and the high frequency contents of the switching. effect of the Voltage Clamp (D7, C14, R18). R25) limiting the dV/dt and the above-mentioned Voltage Clamp. D5+D6 and its control on the second slope of the recovery itself. Vmains Pout Vout Pin THD PF Eff. Vmains Pout Vout Pin THD PF Eff.

volves a poor load transient response. is working with VLFF voltage between 2V and 5.1V. the suitable signal voltage avoiding sense resistor (R1) power dissipation. In the real application the sense resistor is often replaced by sense transformer. Figure 32. Application example ence voltage (pin 11 of the controller) shifts the output of the OP-AMP. VO = 5.1V at the maximum load (IO max).

Sometimes it is useful to disable the controller. For example, in a complete system in which a PWM regulator follows the PFC stage, at low output power it is advantageous to shutdown the PFC section to improve the over- all system efficiency (stand-by / sleep mode). Likewise most of controllers, one way to do this (using L4981A/ B), is pulling down either the Soft-Start or the E/A output pin . In addition the L4981A/B can be disabled ground- ing the P-UVLO (pin 15) see fig 33.The P-UVLO function has been designed to program the supply thresholds by means of an external divider (see application note for details) but it can be effectively used for this purpose forcing a voltage below the internal reference (1.28V).Besides turning off the driver output stage this method puts the controller in "before start-up" condition and gives the advantage of minimizing the supply consumption of the IC. Figure 33. UVLO 1.28V P-UVLO RH RL D95IN281B R2 R3 I ≥ 1mA DISABLE

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publicati on are subject to change without notice. This publication supersedes and replac es all information previously supplied. STMicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectro nics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Ital y - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States AN628 APPLICATION NOTE