AN557

AN557 STMICROELECTRONICS | Alldatasheet

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Technical content

The technology architecture is based on the vertical DMOS silicon gate process that allows a channel length of 1.5 micron ; using a junction isolation technique it has been possible to mix on the same chip Bipolar and CMOS transistors along with the DMOS power components (Fig. 2). Figure 1 shows how this process brings a rapid increase in power IC complexity compared to conventional bipolar technology. In the 70’s class B circuits and DC circuits allowed output power in the range of 70W. By 1980, with the in- troduction of switching techniques in power ICs, output powers up to 200W were reached ; with BCD tech- nology the output power increased up to 400W. EASY APPLICATION DESIGN WITH THE L4970A, MONOLITHIC DC-DC CONVERTERS FAMILY The L497XA series of high current switching regulator ICs exploit Multipower-BCD technology to achieve very high output currents with low power dissipation – up to 10A in the Multiwatt power package and 3.5A in a DIP package .

Figure 3. The Basic Step-down Switching Regulator Configuration ward VF drop across the diode era taken into account. It is a good rule to respect to IoMIN ≥ IL/2 relationship, that implies good operation in continuous mode. variations of the switching frequency may occur and the output regulation decreases. pacitor gives rise to the voltage ripple.

Figure 4. Principal Circuit Waveforms of the figure 1 Circuit.

Which therefore gives: Fig. 4h shows the voltage ripple VESR due to the resistive component of the capacitor. This component is VESR (t) = iC (t) × ESR. Fig. 4i shows the overall ripple Vo, which is the sum of the two previous compo- nents. As the frequency increases (> 20kHz), which is required to reduce both the cost and the sizes of L and C, the VESR component becomes dominant. Often it is necessary to use capacitors with greater ca- pacitance (or more capacitors connected in parallel to limit the value of ESR within the required level. We will now examine the stepdown configuration in more detail, referring to fig. 1 and taking the be-haviour shown in Fig. 4 into account. Starting from the initial conditions, where Q = ON, v C = Vo and iL = iD = 0, using Kirckoff second principle we may write the following expression: Vi = vL + vC (Vsat is neglected against Vi). (1) which gives : (2) The current through the inductance is given by : (3) When V i, Vo, and L are constant, IL varies linearly with t. Therefore, it follows that : (4) When Q is OFF the current through the coil has reached its maximum value, Ipeak and because it cannot very instantaneously, the voltage across the ased to allow the recirculation of the current through the load. When Q switches OFF, the following situation is present: vC (t) = Vo, iL (t) = iD (t) = Ipeak And the equation associated to the following loop may be written : (5) where : vC = Vo (6) It follows therefore that : (7) QΔ 1 2--- T 2--- ILΔ V CΔ Q C---- ILΔ V i L dIL dIL dIL V i V o–() IL V i V o–() IL V i V o–() TON V F L dIL dIL V F V o+() iL t() V F V o+

The negative sign may be interpretated with the fact that the current is now decreasing. Assuming that VF may be neglected against Vo, during the OFF time the following behaviour occurs : (8) therefore : (9) But, because Δ IL+ = ΔIL– if follows that : which allows us to calculate Vo: (10) where T is the switching period. Expression (10) links the output voltage Vo to the input voltage Vi and to the duty cycle. The relation-ship between the currents is the following : (11) EFFICIENCY The system efficiency is expressed by the following formula : where Po = VoIo (with Io = ILOAD ) is the output power to the load and Pi is the input power absorbed by the system. Pi is given by Po, plus all the other system losses. The expression of the efficiency becomes there- fore the following : (12) DC LOSSES Psat :saturation losses of the power transistor Q. These losses increase as Vi decreases. (13) where and V sat is the power transistor saturation at current Io. PD : losses due to the recirculation diode. These losses increase as Vi increases, as in this case the ON time of the diode is greater. (14) IL V o IL V o V i V o–() TON V oTOFF V o V i TON TON TOFF TON IiDC IoDC TON η % P o P i η P o P sat V sat Io TON V o V i TON V o V i P D V F Io V i V o– V i V o V i

where VF is the forward voltage of the recirculation diode at current Io. PL : losses due to the series resistance RS of the coil PL = RS Io2 (15) Pq: losses due to the stand-by current and to the power driving current: Pq = Vi Iq, (16) in which Iq is the operating supply current at the operating switching frequency. Iq includes the oscillator current. SWITCHING LOSSES Psw: switching losses of the power transistor : The switching losses of the recirculation diode are neglected (which are anyway negligible) as it is as- sumed that diode is used with recovery time much smaller than the rise time of the power transistor. We can neglect losses in the coil (it is assumed that Δ IL is very small compared to Io) and in the output capacitor, which is assumed to show a low ESR. Calculation of the inductance value, L Calculation TON and TOFF through (4) and (9) respectively it follows that : But because : TON + TOFF = T and ΔIL+ = ΔIL– = Δ IL, it follows that : (17) Calculating L, the previous relation becomes : (18) Fixing the current ripple in the coil required by the design (for instance 30% of Io), and introducing the fre- quency instead of the period, it follows that : where L is in Henry and f in Hz Vi × 0.3 × Io × f Calculation of the output capacitor C From the output node in fig. 3 it may be seen that the current through the output capacitor is given by: ic (t) = iL (t) – Io P sw V iIo tr tf+ TON IL +Δ L⋅ IL -Δ L⋅ V o TON ILΔ L⋅ ILΔ L⋅ V o L V i V o–() V o L V i V o–() V o

Figure 5. Equivalent Circuit Showing Recirculation when Q1 is Turned Off. Sudden variations of the load current give rise to overvoltages and undervoltages on the output voltage.

8 Vif2LC

8 Vi V C fΔ 2 L

erates the internal reference voltage of 5.1V, with a precision of ±2%, necessary for the feedback. the coil, and therefore to the load, the product Volt x Sec constant. Figure 6. Block Diagram of the 10A Monolithic Regulator L4970A.

1) Oscillator charge current: (For 15V < Vi < 45V) 2) Oscillator discharge current: IDISCH = 20mA 3) Peak voltage ramp: This formula is obtained in the following way: indicating with Ve the voltage of the emitter of the NPN tran- sistor connected to Vcc, and V- the voltage at the inverted input of the comparator, one has: (a) (b) by substituting (a) into (b), one obtains: 4) Valley voltage ramp: Vth-L = 2Vbe 5) Switching frequency: It should be noted that formula (5) does not take into account the discharge time of Cosc which cannot be neglected when one is working at frequencies equal or higher than 200KHz. The discharge time is also tied to the value of Cosc itself. Analitycally one has: from which is obtained the more closely approximate expression of the oscillator frequency: During the discharge time of Cosc, a clock pulse is generated internally that is made subsequently avail- able on the Sync. pin and that can be used to synchronize other regulators. (3 devices of the same family In general, it is better that the Sync pulse is at least 300-400ns in order to be able to synchronize a range of existing regulators; to obtain this result, values of suggested capacitors, in different test circuits, have I CHARGE V i 9V be– R osc V th H– V i 9V be– V e V i 3----- V be–= V V e 2V be–  2V be+=– V V i 3----- V be–  2V be– V i 9V be– fSW R osc C osc TDISCH V th H– V th L–– fSW R osc C osc⋅

been selected. The typical duration of the synchronizing pulse with the suggested values of Cosc are as follows: Obviously, synchronize pulses of eccessive duration can greatly reduce the max duty-cycle and produce distortions in the sawtooth of the synchronized regulator working as slave. P.W.M. Comparing the sawtooth signal generated by the oscillator and the output of the error amplifier, generates the PWM signal which is sent to the driver of the output power stage. The PWM signal, in the path towards the output stage, also encounters a latch block to prevent other pulses from being sent at same period to the output, possibly damaging the power stage. In the PWM block, a duty-cycle limiter has also been in- troduced. Such a limiter is obtained by taking advantage of the synchronizing pulse generated, the power output stage is inhibited. Even if the error amplifier gives a large signal to the peak of the ramp, the power stage will not be able to operate in DC, but will be switched off at each clock pulse. The max. obtainable duty-cycle is higher than 90%; this, however depends on the working frequency and the value of Cosc. Using the formulas 6) and 7) a precise calculation can be done. SOFT START The Soft Start function is essential for a correct startup of the device and for an output voltage that, at the switch on, increases in a monotonous mode without dangerous output overvoltages and without over- stress for the power stage. Soft Start operates at the startup of the system and after an intervention of the thermal protection. Fig. 9 shows the simplified diagram of the startup functions. The function is carried out by means of an external capacitor connected to the Soft Start pin, which is charged with a constant current of about 100µA to a value of around 7V. During the charging time, the output of the error transcon-ductance amplifier, because of Q1, is forced to increase at the same rising edge time of the external softstart capacitor Css. L497X Family (MULTIWATT PACKAGE) C osc (nf) - Rosc = 16KΩ Sync (ns) 0.68 140 12 3 0 1.2 270 1.5 330 2.2 450 3.3 680 4.7 1100 L497X Family (POWERDIP PACKAGE) C osc (nf) - Rosc = 30KΩ Sync (ns) 1.2 230 1.5 280 2.2 420 3.3 600 4.7 900

The PWM comparator block commutates when Vr = Vc. Therefore: from which is obtained The time t obtained from this equation is equal to the ON time of the power transistor. The corresponding duty-cycle is given by: 10) Consequently, after leaving the discharged capacitor of Soft Start, the output of the regulator will reach its value when the voltage across the Css capacitor, charged with constant current, has reached the value Vr - 0.5V. The time necessary in order that the output rises from zero to the nominal value is given by: 11) in which C ss is the Soft Start capacitor and Iss the Soft Start current. Considering Soft Start time as tss, the required time for the Soft Start capacitor to change itself approx from (2Vbe - 0.5V) = (1.2V - 0.5V) to Vr - 0.5V, is: 12) By taking Vr from (10): 13) and substituting it in (12), we obtain: 14) UNDERVOLTAGE LOCKOUT The device contains the protection block of under-voltage lockout which keeps the power stage turned-off as long as the supply voltage does not reach at least 12V. At this point the device starts up with Soft Start. The function of undervoltage is also provided with an hysteresis of 1V to make it better immune to the rip- ple present on the supply voltage. ERROR AMPLIFIER The error amplifier is a transconductance type and deliver an output current proportional to the voltage in- balance of the two inputs. The simplified diagram is presented in fig 12.The principal characteristics of this uncompensated operational amplifier are the following: Gm = 4mA/V, Ro = 2.5Mohm, Avo = 80dB, Isource- sink = 200 Ignoring the high frequency response and hypothesizing that the second pole is below the 0 dB axis in the all the conditions of loop compensation, it is possible to make a first approximation with the equivalent cir- cuit of fig. 14 V r V c V pp V i 9V be– t Vr T V i 9V be–()⋅⋅ D ton Vr T V i 9V be–()⋅⋅ V r V i 9V be–()⋅ V o V i tstart up– C ss V r 0.5V–() Iss tss C ss V r 1.2V–() Iss V r V o V i tss C ss Iss V o V i

The 40KHz internal oscillator is synchronized with the principal one. If the system work with a oscillator tracks the principal oscillator frequency. In this way the switching frequency will not increase in overload situation. A particular care has to be taken in the inductor value in order to avoid problems during overload or short circuit conditions. A critical situation is present with high switching frequency, (more than 200KHz) where a small inductor value is used and with high capacitive load. In order to return in nominal condition after a short circuit the inductor ripple at 40KHz with the nominal output voltage and current has to be lower than the current limitation value. Example Let us consider L4970A, 10A. (the same approach can be used for all the family). The inductor ripple current is given by the following formula: where fsw = 40KHz ±10% In order to get the maximum inductor ripple current, the previous formula becomes: The current limitation for L4970A will start to work at 13A. therefore: where I onom = 10A for L4970A. POWER FAIL-RESET CIRCUIT The L4970A include a voltage sensing circuit that may be used to generate a power on power off reset signal for a microprocessor system. The circuit senses the input supply voltage and the output generated voltage and will generate the required reset signal only when both the sensed voltages have reached the required value for correct system operation. The Reset signal is generated after a delay time programma- ble by an external capacitor on the delay pin. Fig 25 shows the circuit implementation of Reset circuit. The supply voltage is sensed on an external pin, for programmability of the threshold, by a first comparator. The second comparator has the reference threshold set at slightly less the ref. voltage for the regulation circuit and the other input connected internally at the feedback point on the regulated voltage. When both the supply voltage and the regulated voltage are in the correct range, transistor Q1 turns off and allows the current generator to charge the delay capacitor discharges completely before initialization of a new Reset cycle. The output gate assures immediate take of reset signal without waiting for complete dis- charge of delay capacitor. Reset output is an open collector transistor capable of sinking 20mA at 200mV voltage. Fig 26 shows reset waveforms. I LΔ V i V o–() V o⋅ ILΔ V imax V omax–() V omax⋅ Ilim min Ionom ILΔ

The simplified diagram of the output stage is shown in the fig. 27. when one wants to obtain good performance at high switching frequency. easy driving proves to be particularly suitable for this type of application that normally works at high frequency. gate by Q1 so that Q1 can go in saturation, and its source can go up rise towards Vi. into region of low resistance. fall time, a typical value of 50ns. shows the main features of the DMOS transistor. Figure 28. Gate-charge curve for the power

The thermal protection intervenes when the junction temperature reaches 150°C; it intervenes directly on the output stage turning it off quikly and in the meantime discharging the soft start capacitor. The reference voltage and the oscillator will continue to work regularly. The thermal shutdown has a hysteresis, after its intervention, it is necessary to wait for the junction tem- perature to lower around 30°C before the device will begin to work properly again. The device restart to work by using the soft start function. Table 2. High Current Switching Regulator ICs.

APPLICATIONS

Even though the regulators of the L4970A family has been designed to work only in step down configura- tion we will see next how these regulators can be use in large range of applications. In same cases the L4970A device will be used as an example for the entire family assembled in Multiwatt package and the L4974A will be used for the types in powerdip package. Anyway the suggested applications can be extended to any other device of the family by adjusting if nec- essary the external components using the given equation for the calculation. Typical Application The Fig. 29 shows the electrical diagram of the typical application, complete with all the auxiliary functions. The same application suggested in the data sheet as test circuit and is the same used for the final dynamic test. All our devices are 100% tested both in static and dynamic conditions. Included in the dynamic test are obviously the external components: the coil, catch diode and output ca- pacitor which have been defined for all regulators. Shown below are the electrical diagrams of 5 devices that compose the family of this regulator complete Parameter L497X FAMILY L4970A L4977A L4975A L4974A L4972A L4972AD Surf. Mount. Max. Input Operating Voltage 50V 50V 50V 50V 50V 50V Output Voltage Range 5.1V ( ±2%) to 40V Max. Output Current 10A 7A 5A 3.5A 2A 2A Power Switch R DSON at 25°C 0.13Ω typ. Switching Mode Control System Continuous Mode, Direct Duty Cycle Control with Voltage Feed-Forward Max. Switching Freq. 500KHz 500KHz 500KHz 200KHz 200KHz 200KHz Efficiency VINPUT = 35V VOUT = 5.1V 10A 80% at 200KHz 80% at 200KHz 85% at 200KHz 3.5A 85% at 100KHz 85% at 100KHz 85% at 100KHz Current Limiting Constant Current Soft Start Y es Reset and Power Fail Y es Synch Y es Crowbar No Package Max. R th j-case (pin) R th j-amb Multiwatt15 1°C/W 35°C/W Multiwatt15 1°C/W 35°C/W Multiwatt15 1°C/W 35°C/W Powerdip 16+2+2 12°C/W 60°C/W Powerdip 16+2+2 12°C/W 60°C/W SO20L 6°C/W 80°C/W

• 2 capacitors in parallel to increase input RMS current capability ** 3 capacitors in parallel to reduce total output ESR Table A Table B SUGGESTED BOOTSTRAP CAPACITORS R1 = 30KΩ * C1, C2 = 3300µF 63VL EYF (ROE) R2 = 10KΩ C3, C4, C5, C6 = 2.2µF R3 = 15KΩ C7 = 390pF Film R4 = 16KΩ C8 = 22nF MKT 1817 (ERO) R5 = 22Ω 0,5W R6 = 4K7 C9 = 2.2nF KP1830 R7 = 10Ω C10 = 220nF MKT R8 = see tab. A C11 = 2.2nF MP1830 R9 = OPTION **C12, C13, C14 = 220 µF 40VL EKR R10 = 4K7 C15 = 1 µF Film R11 = 10Ω D1 = MBR 1560CT (or 16A/60V or equivalent) L1 = 40µH core 58071 MAGNETICS 27 TURNS Ø 1,3mm (AWG 16) COGEMA 949178 V0 R10 R8 12V 4.7K Ω 6.2KΩ 15V 4.7K Ω 9.1KΩ 18V 4.7K Ω 12KΩ 24V 4.7K Ω 18KΩ Operating Frequency Bootstrap Cap.c10 f = 20KHz ≥680nF f = 50KHz ≥470nF f = 100KHz ≥330nF f = 200KHz ≥220nF f = 500KHz ≥100nF

Figure 33. Test and Evaluation Board Circuit. (Vi = 15 to 50V); Load regulation = 7mV (Io = 0.5 to 2A); for component values Refer to the fig. 32 (Part list). Note: In the Test and Application Circuit for L4972D are not mounted C2, C14 and R8.

Figure 36. Test and Evaluation Board Circuit. Note: In the Test and Application Circuit for L4974D are not mounted C2, C14 and R8.

Figure 39. Test and Evaluation Board Circuit For component values, refer to test circuit part list.

Figure 42. Test and Evaluation Board Circuit component values, refer to test circuit part list.

eral it is sensitive to temperature. instantaneous peak of energy to the load at the switching frequency. age rating, just like its RMS current. only one of double value, and with the same voltage rating. pacitors the total current ripple. ious capacitors charging some more others, that could damage the reliability of the system. the capacitor should be done. allowed on the capacitor package. Table 3. Low-voltage electrolytic capacitors for switch-mode power supplies with low impedance

Table 4. Admissible ripple current

Figure 53. Low Cost Application Circuit. with output voltage adjustable between 5.1V. and 24V. and at the same time current peak bigger than the output current at the switching frequency. center tap with only 2 diodes with higher reverse voltage. A cost reduction of the trasformer can be reached using an active power factor corrector. looking on the power factor corrector application note. POWER SUPPLY WITH MAINS HIGH FREQUENCY PREREGULATOR. cost, a high frequency preregulator can be used. ly the device, providing for the isolation requirements. 40V; it can be a bit increased if using a backup battery of 48 nominal Volts. its own current limitation and thermal protection. frequency at least 5% higher than the others device (working as slave) one. quency of the controller (See Fig. 55).

The current, flowing in backward, to have 0V it will be: Δ VR2 = R2 · 0.21 = 4.7k · 0.21 = 1V Therefore, when the cursor "P" reaches Vref + 1V the output voltage goes to zero. At this point we are able to define as well the values of P1 and R3. When the "P" cursor is completely moved to high, there should be 6V of dropping to "P", and in this way 0.6mA will flow. The current flowing in R3, considering that the voltage at pin 15 has a typical value of 12V, it will be of 0.8mA. In this case the R3 value will be 7K5ohm. 3.3V / 10A DC-DC CONVERTER When an output voltage lower to the reference voltage of 5.1V must be stabilized with a good result from stability and regulation point of view, and not having available the not-inverting input of the error amplifier, it is possible to use an external reference. In this case a TL431C reference has been chosen, which is cheaper and widespread used. In this case more than a simple reference, it is a true shunt regulator, containing a reference, an error amplifier and a transistor capable of absorbing a max current of 100mA. Such component can be compensated like a common OP/AMP, and therefore in our application can sub- stitute both the internal reference and the error amplifier. The fig. 61 represents the electrical diagram of the application at 3.3V. The operating input voltage is between 12V (due to the internal UVLO) and 35V, with a minimum operating switching frequency of 100KHz. The maximum operating input voltage is limited only 35V because the minimum "ON" time, which should not be reduced below 1 microsecond. At input voltage of 35V, output voltage of 3.3V and fs=100KHz the Ton time is already about of 1 microsecond. Figure 61. V ref L4970A3 2.2µF 36K 2.2nF 1 2 14 15 22K TL431 0.1µF 330Ω STPS 1545 0.22µF 50µH EKR 1000µF 10V Vo=3.3V Io=10A 2200 µF 12V <Vi <35V CORE TYPE 58071 MAGNETICS D93IN001

best if matched in Vbe, and some other passive components. For a cost reduction Q1 can be substitute by a simple diode 1N4148. The divider composed by R2 and R1 fixes a voltage at the whished voltage value (for example 50 -100mV) on the Q2 emitter. Q2 will be reversed bias untill the emitter voltage of Q1 will raech the same value as itself. At this point Q2 will be direct bias and will begin to absorb current from its collector; in the moment in which Q2 will enter into conduction, a variation ΔVsc at the current sense resistor will give a variation of the Q2 current equal to: When the current absorbed by Q2 will reach the maximum current delivered by the error amplifier output (or by the current of the soft-start if this pin is prefered to use), the error amplifier will fall out of regulation and its output voltage will begin to decrease reducing, conseguentely, the duty cycle; then the regulator will begin in this way to behave as a generator of current instead of voltage. The emitter voltage of Q2 is fixed by the following formula: A general criterium, is that of fixing the divider "R1R2" in such way as to make a current flow that is greater than the necessary lowering the output voltage of the error amplifier. The maximum current delivered by the output of the transconduttance error amplifier is 200mA; the current that has to flow in the divider R1R2 should be around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more soft interventions. By varying the value of R2, the point of intervention of the current limitation will be moved. The resistor Rx contributes to introducing a more or less accentuate foldback effect, on the output current. In the following table suggest a few values of Rsense according to the nax output current. The criterium used to defined the value of the sense resistor is essentially tied to the max power dissipated by the resistance, as well as to the market availability. If the mains objective is to maximize the efficiency when (delivering for example 10A), it is convenient to use two current transformers instead of a dissipative resistor, one in series to the source of the internal DMOS and one in series to the catch diode. Using such solution, a quite simple and fine regulation of the current is possible to implement. Figure 66 shows a current generator solution with high precision on the current, using an op/amp instead of two small signal transistors. Higher input voltage. Since the maximum operating input voltage of this family is 50V, when one of these devices must be sup- plied with more elevated voltages, it is necessary to introduce a preregulator. Fixing the output voltage of the preregulator of 45V, the power dissipation of the preregulator is: P d = Ii · VCE = Ii · (Vi - 45) R sense (mΩ ) Io (A) Device 100 3.5 L4970A L4977A L4975A L4974A L4972A ICQ2Δ V SCΔ V EQ2 V REF ==

Figure 67. Design Example for L4974A or higher then the output regulated voltage. In this case a well known buck-boost topology is suggested. can be used. For input voltage less than 20V the zener diode can be avoided. transistor turn-off, disconnecting the power supply. power transistor is protected, but the current in the coil and the freewheeling diode is not limited.

Figure 70. LAYOUT CONSIDERATIONS Both for linear and switching power supplies when the current exceeds 1A a careful layout becomes im- portant to achieve a good regulation. The problem becomes more evident when designing switching reg- ulators in which pulsed currents are over imposed on dc currents. In drawing the layout, therefore, special care has to be taken to separate ground paths for signal currents and ground paths for load currents, which generally show a much higher value. When operating at high frequencies the path lenght becomes extremely important. The paths introduce distributed inductances, producing ringing phenomena and radiating noise into the surrounding space. The recirculation diode must be connected close to output pin, to avoid giving rise to dangerous extra negative voltages, due to the distributed inductance. HEATSINK DIMENSIONING The heatsink dissipates the heat produced by the device to prevent the internal temperature from reaching values which could be dangerous for device operation and reliability. Integrated circuits in plastic package must never exceed 150°C even in the worst conditions. This limit has been set because the encapsulating resin has problems of vitrification if subjected to temperatures of more than 150°C for long periods or of more than 170°C for short periods. In any case the temperature accelerates the ageing process and therefore influences the device life. A well designed heatsink should keep the junction temperature between 90°C and 110°C. Fig 71 shows the structure of a power device. As demonstrated in thermo-dynamics, a thermal circuit can be considered to be an electrical circuit where R1, R2 represent the thermal resistance of the elements (expressed in °C/W) (see fig. 72). C1, C2 are the thermal capacitance (expressed in °C/W). I is the dissipated power. V is the temperature difference with respect to the reference (ground). This circuit can be simplified as shown in fig. 74, where: C C is the thermal capacitance of the die plus that of the tab. C h is the thermal capacitance of the heatsink R jc is the junction case thermal resistance R th is the heatsink thermal resistance HIGH POWER PREREGULATOR L1 L2 L7805 L7812 L4805 5V/1A 12V/1A 5V/0.4A D93IN010A L2 and C2 are necessary to reduce the switching frequency spikes