AN537

AN537 MICROCHIP | Alldatasheet

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© 1992 Microchip Technology Inc. DS00537A-page 1 Serial EEPROM Endurance AN537 The term “endurance” has become a confusing param- eter for both users and manufacturers of EEPROM products. This is largely because many semiconductor vendors treat this important application-dependent reli- ability parameter as a vague specmanship topic. As a result, the system engineer often designs without proper reliability information or under-utilizes the EEPROM as an effective solution. Endurance (the number of times an EEPROM cell can be erased and rewritten without corrupting data) is a mea- sure of the device’s reliability, not its parametric perfor- mance. As such, endurance is not achieved by some- how making EEPROM devices more durable or robust to extend the life of the intrinsic erase/write cycle, but rather by reducing their defect-density failure rates. This has a direct impact on the design engineer characterizing EEPROM memory needs for an application and evaluat- ing components from various manufacturers. The sys- tem design engineer needs to understand not only the relationship between the application, expected use and failure mechanisms, but also how the manufacturer has arrived at published endurance data for its components. This tutorial volume is intended to clarify some of the issues in the industry and provide a tool for the system design engineer, the system reliability engineer, and the component engineer to determine EEPROM reliability and understanding how to apply it to actual application requirements. It will examine four main areas:

• CMOS floating gate memory cell operation and char- acteristics
• Significant process and design interactions and en- durance characterization variables
• Common misinterpretations of endurance
• Determining some real world application reliability requirements EEPROM MEMORY CELL OPERATION AND CHARACTERISTICS In discussing endurance characteristics of EEPROMs, it’s important to review how these components operate, and why and how they fail. Figure 1 illustrates a CMOS floating gate EEPROM cell, including voltage conditions for READ, ERASE, and WRITE operations. To erase or write, the row select transistor must have the relatively high potential of 20V. This voltage is internally gener- ated on chip by a charge pump, with the only external voltage required being V DD . The only difference be- tween an ERASE and a WRITE is the direction of the applied field potential relative to the polysilicon floating gate. When 20V is applied to the polysilicon memory cell gate and 0V is applied to the bit line drain (column), electrons tunnel from the substrate through the 90-angstrom Tun- nel Dielectric (TD) oxide to the polysilicon floating gate until the polysilicon floating gate is saturated with charge. The cell is now at an ERASE state of “1”. When 0V is applied to the polysilicon memory cell gate and 20V is applied to the bit line drain (column), electrons tunnel from the polysilicon floating gate through the TD oxide to the substrate. The cell then is at a WRITE state of “0”. This sequence of the transfer of charge onto the floating gate (ERASE) and the electrical removal of that charge from the floating gate (WRITE) is one ERASE/ WRITE cycle, or “E/W cycle.” The field (applied voltage to an oxide thickness) across the tunneling path created by the 20V potential is ex- tremely high in order to transfer the electrons. Over the cell’s “application time,” as measured by E/W cycles, the EEPROM cell begins to wear out due to the field stress. The EEPROM cell wears out as the number of cycles increase resulting in the voltage margin between the ERASE and WRITE states decreasing until finally there is not enough margin for the EEPROM sense amp to detect a difference in the two states during a READ. Failure is defined as when the sense amp can no longer reliably differentiate logic state changes. Figure 2 (single cell EEPROM endurance characteris- tics) illustrates that the intrinsic wear out point for a normal cell with specified dimensions and electrical characteristics is very acceptable, in excess of 2 million E/W cycles. Failures at lower cycles are due mostly to very small defects or imperfections in the oxide or silicon-to-oxide interface. Everything a System Engineer Needs to Know About Serial EEPROM Endurance 8-15

DS00537A-page 2 © 1992 Microchip Technology Inc. Serial EEPROM Endurance Error correction circuits are design techniques com- monly used by EEPROM manufacturers to increase endurance by reducing the failure rate caused by single bit failures. These circuits are transparent to the user. One typical scheme is using 4 bits of error correction for every 8 “real” bits (one byte). In this scheme, one bit failure in the byte is correctable, while if two bits within the byte fail, the byte is not correctable. Another error correction scheme is to use one “parity” bit for every “cell.” Here both EEPROM cells must fail to result in a bit fail. A key point to remember is that most failures occurring at less than 2 million E/W cycles are due to the number of defects per a given area (defect density dependent.) Thus high EEPROM endurance reliability is achieved by reducing the defect density failure rates, not by increas- ing the number of intrinsic cycles in the cell’s operational design. FIGURE 1 - CMOS FLOATING GATE EEPROM CELL Memory Cell Gate Row Select Transistor Inter-Level Dielectric

90 ANG Td Oxide

0.0 volts 0.0 volts 0.0 volts 0.0 volts 0.0 volts 20.0 volts 20.0 volts 0.0 volts 18.0 volts 20.0 volts 0.0 volts Float 1.6 volts 5.0 volts 5.0 volts 0.0 volts Bit Line Row Select Gate Memory Cell Gate Common Source (Not to scale) Poly-Silicon, Level 2 Poly-Silicon, Level 2Poly-Silicon, Level 1 8-16

© 1992 Microchip Technology Inc. DS00537A-page 3 Serial EEPROM Endurance FIGURE 2 - SINGLE EEPROM CELL ENDURANCE CHARACTERISTICS PROCESS AND DESIGN VARIABLES AFFECTING ENDURANCE There are many subtle process and design variables that have a strong impact on endurance. These interact- ing variables will play very different roles depending on the different process technologies of various semicon- ductor manufacturers. The primary interaction is the amount of TIME at the HIGH VOLTAGES that is ultimately applied to the cell. A finite amount of time at finite voltages are required to achieve “optimal” ERASE and WRITE thresholds. If the time is too short and the voltage is too low, the EEPROM will not program to the proper threshold. Also, if the programming ramp time is too fast and the voltage is too high, the EEPROM’s endurance will be reduced. Unfor- tunately, there is most often a trade-off between fast reliable programming performance or high endurance reliability. Some of the significant process and design variables are shown below and their impact on program- ming performance and endurance performance. PARAMETER PROGRAMMING ENDURANCE Internal High Voltages HIGHER = Faster Programming LOWER = Increased Endurance Internal High Voltage Ramp Rate FASTER = Faster Programming SLOWER = Increased Endurance Programming Time LONGER = Improved Voltage SHORTER = Less Oxide Stress for Margin on the Cell Increased Reliability TD Oxide thickness THICKER = Slower Programming THINNER = Reduced Endurance Temperature LOWER = Faster Programming LOWER = Increased Endurance Cell Margin (Volts) Erase/Write Cycles Erase Write Sense Amp Level 1 1,000,000 Failure will occur when either the ERASE or WRITE margin crosses the sense amp level 8-17

DS00537A-page 4 © 1992 Microchip Technology Inc. Serial EEPROM Endurance COMMON MISINTERPRETATIONS In examining industry EEPROM literature on the topic of endurance, it’s easy to misunderstand or misinterpret endurance concepts due to incomplete databook state- ments. The following are clarifications to some of the common misinterpretations: Endurance and Read Cycles READ operations are unlimited since they impose virtu- ally no stress on the cell. Endurance data apply only to E/W cycles. Erase/Write Ratings E/W ratings are based on each byte in the application, not on the number of opcodes or control byte commands utilized. For example, if a part is rated to 100K E/W cycles, then each individual byte can be erased and written 100K times. The part is NOT limited to only a total of 100K E/W opcodes or control bytes. This is probably the most common misinterpretation made by system designers. Endurance is thus an interactive application- specific reliability parameter. It is not a typical data sheet specification, such as a parametric AC/DC specification with benchmark standards for measurement. Cycles/Day In many cases, a serial EEPROM is used for widely varying functions in an application. These functions have different E/W usage requirements (cycles/day), resulting in different endurance requirements and, usu- ally, different reliability results for each function. For example, assume a given end-product application will have a 10-year life. For each function within that application, an assumption must be made for the ex- pected E/W cycles per day for a given segment of bytes. If a function has a segment of bytes cycled 1 time per day, then this segment of bytes will have 3,650 cycles in its lifetime (365 days per year for 10 years at 1 cycle per day and 7 days per week operation). Any given segment of bytes would have to cycle 274 times per day everyday to reach 1,000,000 E/W cycles in its 10-year application lifetime. Such a frequency is, of course, very rare in actual applications. For reference purposes, Figure 3 indicates typical cycles per day for some common applications. Although many manufacturers routinely discuss very high numbers of E/ W cycles, the amount of applications actually utilizing 1 million cycles is very small. A further and very important incorrect assumption often made is that ALL bits in an application need the same number of cycles and endurance ratings. In most applications, however, functions that require a high FIGURE 3 - TYPICAL SERIAL EEPROM E/W CYCLES/DAY BY APPLICATION Maintenance Log Last Number Redial Electronic Lock Access Power Down Storage Digital Potentiometer Look Up Table Tuner Controls System Configuration Anti-Lock Brakes Speed Dial Airbag 0.001 0.01 0.1 1 10 100 1000 Cycles/Day 8-18

© 1992 Microchip Technology Inc. DS00537A-page 5 Serial EEPROM Endurance First, memory cell failure rates are defect density driven up to the intrinsic wear out point. Existing defects in a cell, while not causing failure initially, are stressed during every transfer of electrons through the TD oxide until they eventually cause cell failure. Worst case testing would be to erase and write each bit, which is what a write all “0”s pattern with an auto-erase of “1” routine will perform. Indeed, this write all “0”s test pattern will produce very different results than a check- erboard test pattern of alternating “1”s and “0”s within a byte, since cells are changed more often writing all “0”s than in an alternating “1” and “0” write pattern. The resultant failure rate differences are indicated on the pattern effect graph in Figure 4. In actual use, however, a system will experience a random pattern much more like the alternating “1”s and “0”s pattern than the more stressful all “0”s pattern. The key point for system designers is to determine how accurate a test routine has been used to determine a particular manufacturer’s endurance data, and make the appropriate judgement on that part’s expected en- durance in the application. FIGURE 4 - PATTERN EFFECT ON ENDURANCE TESTING Erase/Write Cycles Cumulative Failure Rate Byte Write 0 Pattern Alternating "1" and "0" Pattern number of E/W cycles per day require only a small number of bits. Last number redial in a telephone, for example, consumes many E/W cycles per day, but utilizes only a few bytes for this function. By contrast, speed dial storage in that same telephone consumes only a fraction of E/W cycles per day, but requires a relatively large segment of bits to accommodate the many speed dial options. In such an application, the same serial EEPROM normally performs both functions at different address locations. ENDURANCE DATA FROM THE CUSTOMER’S PERSPECTIVE Unfortunately, an industry standard for an endurance test method has yet to be adopted. Since endurance data is not baselined, the process of evaluating endur- ance becomes that much more complicated for the system designer and reliability engineer. It is not uncommon for customers to request endurance data from many semiconductor vendors. All vendors would be expected to comment that they experience a low failure rate through 100K E/W cycles. While this can be a true statement, it can also be a very incomplete statement. It is extremely doubtful that all vendors test their components to the same conditions. Yet the variables within endurance testing are extremely signifi- cant. Small differences in text protocol can have enor- mous differences. Pattern, cycling mode, temperature and array size, for example, are the most significant testing variables. 8-19

DS00537A-page 6 © 1992 Microchip Technology Inc. Serial EEPROM Endurance Second, the cycling mode graph in Figure 5 indicates that significantly different results can be achieved in endurance testing using a block cycle mode than using a byte cycle mode. The block mode is commonly used by manufacturers to “speed up” the endurance charac- terization process. However, endurance results usually will appear much better for the block mode than the byte mode, due to the high voltage variables discussed earlier. The reason is that the voltage ramp rate is significantly SLOWER, the high voltages are slightly lower, thus less stressful for block cycling since the capacitive load of the entire array is on the high voltage charge pump. The capacitive load is much lower with a single row or byte, which thus has a significantly faster ramp rate. Also, there is not a polysilicon to polysilicon stress for adjacent cells since all cells are at the same potential. Most often, these factors combine to yield lower failure rates for block cycling than for byte cycling. Again, the test conditions must match the system condi- tions. Finally, increasing temperature also increases stress on the cell. Microchip’s endurance characterization data indicates that increasing temperature adds an activa- tion energy (Ea) of 0.12eV on the cell. From a 25°C to 85°C ambient the acceleration factor is approximately 2.1. Therefore, the higher the temperature, the higher the stress. These results will vary significantly with each EEPROM manufacturer. RECOMMENDED EEPROM ENDURANCE TESTING Microchip believes that EEPROM components should be endurance tested to reflect system conditions. There- fore, units are cycled to an alternating ONE and ZERO pattern (checkerboard), then to an alternating ZERO and ONE pattern (inverse checkerboard). Again, since endurance characterization data indicates that a random single bit fail is the primary first order failure mode, endurance is defect density (def/cm2 or segment of bit size) dependent. Therefore an expected failure rate range by density can be established. DETERMINING THE RELIABILITY CALCULATIONS There are three primary components for the system design engineers to use in determining the endurance reliability required for a defect density limited applica- tion. These three components are:

• Erase/write cycles/day estimated for the function.
• The number of bits in the function (or segment size).
• Case operating temperature of the Serial EEPROM. Let’s look at three typical examples utilizing the above information to predict a cumulative failure rate at differ- ent points in a system lifetime. Please note that Industry endurance perceptions have improved from a very high (> 2%) failure rate expectation to a very low actual PPM level failure rate in the past few years. FIGURE 5 - CYCLING MODE EFFECT ON ENDURANCE TESTING Erase/Write Cycles Cumulative Failure Rate Byte Mode Block Mode 8-20

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