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Page 1 of 15  2008 Teridian Semiconductor Corp. Rev 2.1 A Maxim Integrated Products Brand AUGUST 2008 APPLICATION NOTE CONTENTS  Introduction to TERIDIAN 78P235x LIUs  Layout Guidelines  Recommended I/O Terminations  Transformers  Supplemental Surge Protection  Return Loss Matching Circuit (optional)  Coaxial Connectors  Crystal Oscillator Requirements  Thermally Enhanced LQFPs  E4 Reference Design  Sample Jitter and Pulse Mask Test Results APPLICABLE DEVICES  78P2352 Dual Channel LIU  78P2351 Single Channel LIU  78P2351R Small form factor LIU INTRODUCTION TO TERIDIAN 78P235x LIUs The TERIDIAN 78P235x ST M1e/E4 Line Interface Units (LIU) ICs are TERIDIAN’s second- generation design. Next generation design architectures and techniques are used to provide system designers with enhanced functionality, performance and improved noise immunity. On the receiver s ide, one such technique is the use of a digital PLL, rather than the traditional analog PLL. Note the absence of the external loop filter capacitor. Thanks to the digital PLL, this is now provided on chip. The removal of the pin and external connection for this critical node eliminates EMI, a noise injection port, and significantly improves the noise immunity. Additionally, since the loop damping is controlled on chip and is digital, the 0.1dB jitter peaking specification is now guaranteed by the digital loop filter. Traditionally, an external 1% resistor is used to set the transmitter amplitude, and sometimes used in setting internal biasing. Thus, the pin can be a source of EMI pickup directly into critical blocks of the device. On this generation design , this external resistor and pin have been removed and placed internally, thus completely eliminating the potential for EMI interference. LAYOUT AND I/O TERMINATION GUIDELINES When designing an analog interface for error -free performance, there are sever al important factors to consider. This document provides a few recommendations that can help alleviate unwanted noise due to sub- optimal board layout around the LIU. It also provides general guidelines for meeting the stringent return loss and CMI transmi t pulse shape requirements, both of which are largely dependant on PCB design and layout. GROUND PLANE A common system grounding approach is to use a different ground at the coax connectors for safety isolation and improved electromagnetic compatibility. In this implementation, the coax connector shield is directly connected to frame or chassis ground. The component ground is an isolated plane that connects directly to the negative supply pins of active components. These grounds are isolated from each other by placing a strip of area, which is void of copper, in the ground plane underneath the primary of the transformers as shown in Figure 1 below. The chassis/frame ground plane is directly connected to the equipment chassis, which connects to the facili ties Earth ground structure. Reference ITU -T recommendation K.27 for more information on grounding recommendations.

grounds near the transformer with a strip of low inductance wire. Figure 1. Two different ground planes As with the component ground plane, the power plane layer should only extend to the LIU side of the transformer. to-plane current fringing at the plane edges. component on the bottom side. Ceramic, low ESR caps are recommended for best frequency response. Generally X7R dielectric capacitors provide the best price/performance trade-off.

Design Guidelines for TERIDIAN 78P235x LIUs Page 6 of 15  2008 Teridian Semiconductor Corp. Rev 2.1 TRANSFORMER SELECTION The 78P235x LIUs use 1:1CT (center -tapped) wide band transformers for both transmit and receive ports. These wideband transformers must exhibit the following characteristics:  75Ω impedance (primary and secondary)  Max RF power: ~250mA  Max DC current: ~30mA  Avg. Insertion loss: 1dB max  Return loss: Min 16dB (7 –250 MHz)  Frequency Response: The bandwidth or frequency response of available transformers can range from 400MHz to 800MHz. For some system environments, more bandwidth- limiting transformers can help eliminate the overshoots that can cause pulse mask failures. Too narrow of a bandwidth will result in a rounded transmit pulse shape and receiver sensitivity to binary CMI zeroes at max cable loss. To provide system designers with greater flexibility, Teridian has evaluated and approved multiple vendors in compatible SMT footprints. The following table lists the recommended single and dual transformers from different vendors. NOTES: 1. To request test data on any of the listed transformers or to get an updated list of qualified vendors, please send an email to: wan.support@teridiansemiconductor.com 2. Pinout naming conventions can vary from vendor to vendor, but all winding diagrams should match those found in Figure 9. Single core transformers Manufacturer Part Number Mini Circuit ADT1-1WT-1 Halo TG04-TDK2NS Tamura TTC-298 Midcom 7400-30R-LF1 Datatronic SM78809 Dual core transformers Manufacturer Part Number Halo TG04-TDK1N1 TAMURA TTC-300 Midcom 000-7419-30R-LF1

individual component’s return loss won’t be efficient and will provide misleading results. Figure 8. (Optional) Discrete components to improve the return loss

Design Guidelines for TERIDIAN 78P235x LIUs Page 9 of 15  2008 Teridian Semiconductor Corp. Rev 2.1 COAXIAL CONNECTORS Coaxial connectors must be of the 75- ohm variant to avoid compromising the mechanical properties of the mating receptacle and to match the impedance of the line. For optimal EMC performanc e and ESD immunity at the faceplate, it is critical that the shield of the coax connectors be well bonded to the frame or chassis in any board design. The system enclosure should also be properly grounded at the earth facility. For optimal space savings, Teridian suggests the use of 75 ohm DIN 1.0/2.3 connectors (BT Type 54), which can be sourced from the following suppliers.

  • Xian Connector
  • Compel
  • Radiall
  • SIAM
  • Amphenol
  • Tekmos
  • Tru
  • AMP / Tyco
  • Hsu-Tsan Group CRYSTAL OSCILLATOR REQUIREMENTS The following requirements are provided with the assumption that plesiochronous transmit timing mode is enabled. If using a crystal oscillator in any of the synchronous modes, the clock stability over the life of the oscillator will be inherently limited by the SONET/SDH /PDH bit rate requirements of +/ - 20ppm for STS -3/STM-1 and +/-15ppm for E4. Several factors to consider when selecting a crystal oscillator for plesiochronous mode:  Frequency tolerance / stability (70ppm or better)  Aging (not to exceed 100ppm over life)  Rise / Fall time  Output amplitude (must be at least 2V signal swing)  Period jitter (up to 220ps evaluated without any appreciable effects) Evaluation of the following crystal oscillators at Teridian showed no appreciable differences in jitter performance. Vendor Part number CTS CB3LV-3C-19.440000 Ecliptek EH2645ETTS-19.440M SaRonix S1613B-19.44 Abracon ASV-19.44MHz-C Crystek C3392-19.44MHz

Design Guidelines for TERIDIAN 78P235x LIUs Page 11 of 15  2008 Teridian Semiconductor Corp. Rev 2.1 REFERENCE DESIGN WITH TRANSWITCH L4M (E4) MAPPER For E4 applications, the L4M mapper from Transwitch is a very commonly used device. The Teridian 78P2351 can work with the L4M mapper seamlessly for such applications. The following block diagram displays how two devices are inter-connected at the system level. TDK 78P2351 E4/STM1e LIU SDH (STM1) Overhead Processor Serial 155Mbps LVPECL (NRZ coding) POxD POCK PICK PIxD Transwitch L4M TXC-03456 E4 Mapper VCXO 34.816MHz RXCI CKREF TXDn TXC RXDn RXCO LOS (active-high)EXLOS E4 Line Interface (75ohm coax) Loop filter CTRL /CTRL Div 2 4-bit nibble 5V to 3.3V Data Buffer 4-bit nibble 35MHz 35MHz Figure 12: Inter-connection Between Transwitch L4M and 78P2351 Notes:  Since the Transwitch L4M provides a clock for the 78P2351, the 78P2351 should be set for parallel -slave mode accordingly.  The Transwitch L4M is a 5V device and the 78P2351 is a 3.3V device. A 5V to 3.3V data buffer is needed to translate the voltages between them  During L4M Line Loopback, configure the 78P2351 for Loop-timing parallel-slave mode.  The dual channel 78P2352 is not recommended for E4 applications due to the asynchronous nature of each E4 signaling path. OPTICAL MEDIA INTERFACE Please send email to wan.support@Teridiansemiconductor.com for detailed instructions on how to use the optical media interface. LOSS OF LOCK BEHAVIOR After power -up or chip reset, the receiver LOL status bits (and pins) may be in an undefined state and report incorrect status. To properly reset the Rx LOL detector, one must assert & de-assert the LOLOR bit (5) in the signal control register during initialization. Use of receiver loss of lock detector is not recommended in HW (pin control) operation. False Rx LOL assertion or toggling the LOLOR bit will not affect the integrity of t he data path or clock recovery.

Design Guidelines for TERIDIAN 78P235x LIUs Page 12 of 15  2008 Teridian Semiconductor Corp. Rev 2.1 SAMPLE JITTER TEST RESULTS Receive Jitter Tolerance Jitter Transfer Intrinsic Transmit Jitter STM-1e FIFO enabled FIFO bypassed (Plesiochronous timing mode) Filters on 0.025UIp-pk 0.049UIp-pk Filters off 0.053UIp-pk 0.049UIp-pk

Design Guidelines for TERIDIAN 78P235x LIUs Page 13 of 15  2008 Teridian Semiconductor Corp. Rev 2.1 SAMPLE TRANSMIT PULSE SHAPE RESULTS There are generally two methods for specifying and measuring the transmit pulse signal integrity. Pulse Mask Templates originate from ITU -T G.703 and Eye Diagrams originate from ANSI T1- 102. Telcordia GR -253-CORE refers to both and provides a better description on how to use the eye diagrams. Pulse Template The Pulse Template specifies the characteristics of singular pulses. It defines the precise shape of the pulse including rise time, fall time, amplitude and overshoot. It takes into account the affect of inter -symbol interference from successive pulses and reflection from improper terminations. To perform pulse template measurements, the oscilloscope must be able to isolate the pulse under evaluation, be it binary 1 or 0. The Tektronics TDS 784 is one oscilloscope that has the ability to trigger on CMI signals, capturing only the pulses of interest. The signal can be acquired using average or sample mode depending on the parameters to be evaluated. Average mode provides the clearest indication of pulse shape and allows measurement of continuous anomalies such as refl ection and inter -symbol interference. Sample mode will provide information on spurious signal noise and occasional violations of the pulse template. As noted in G.703, it is important to eliminate the effects of low frequency jitter or wander when making pulse mask measurements. Therefore it is not recommended to use long persistent acquisition methods (DPO) for performing pulse template measurements. Instrumentation Variations These measurements were taken on the Tektronics TDS 784D oscilloscope. Generally auto set will properly select the proper acquisition method and set time and voltage scales. However, often these settings come up incorrect and will need to be adjusted. Different scopes will default to different acquisition modes depending on model. It is important to carefully monitor all scope settings when performing pulse shape measurements.

Design Guidelines for TERIDIAN 78P235x LIUs Page 14 of 15  2008 Teridian Semiconductor Corp. Rev 2.1 Eye Diagram The Eye Diagram provides a longer -term view of the signal, taking into account the relative time position of successive pulses. It provides less information about pulse shape but allows a more thorough analysis of the cumulative effects of wander and jitter. Eye diagrams require the use of DPO mode or other long- term persistence method to preserve information from the preceding pulses then overlaying them in a continuous fashion. The timing and pulse width variations are then displayed as a widening of the eye diagram’s traces, which must remain within the template to meet specification. “Maximum Eye Diagram” @ 0ft and “Small Eye Diagram” @ 225ft A few words about transmit timing modes in the 78P235x The 78P235x LIUs use delay lock loop (DLL) technology to track the incoming data and recovery timing. In the 78P235x, there are two different modes in which the integrated CDR is used to r ecovery the transmit clock. This section will describe both and their effects on CMI pulse mask testing. Most transmit timing modes of the 78P235x are synchronous (re -timing) modes where a system reference clock is provided to the LIU that is source synchronous with the timing of the transmit data source (i.e. SDH Overhead Processor), E4 Mapper). In this mode of operation, the transmit output is re- timed to eliminate any jitter caused by clock recovery or serialization. For application where only data is available at the system (NRZ) interface, a plesiochronous transmit timing mode is available. In this mode, the recovered transmit clock is used for CMI encoding and pulse shaping. D

622 MHz

BW ~ 1 MHz 235x Transmit - Synchronous (re-timing) modes Tx Data In System Reference +/- 20ppm for STM1 +/- 15ppm for E4 De-coupled Tx output exhibits lower phase jitter due to re-timing with FIFO BW ~ 1 MHz 235x Transmit - Plesiochronous mode  BW = 80 kHz  32 phase taps (100ps )  Direct coupled Tx output will exhibit high freq. phase jitter +/- 70ppm or better

Design Guidelines for TERIDIAN 78P235x LIUs Page 15 of 15  2008 Teridian Semiconductor Corp. Rev 2.1 The DLLs use 32 phase taps to recover a 311MHz clock (nominal phase tap spacing is 100ps). With jitter of the incoming data and variable transition density, the recovered clock will naturally hop between a couple of taps even when phase locked. In plesiochronous timing mode, this will appear as hig h frequency phase jumps or phase jitter during isolated CMI pulse mask measurements (most noticeable with CMI binary 0) This jitter generation is normal and inherent to all CDR’s, although more linear with analog PLLs. The magnitude of the output jitter is directly related to the bandwidth of the Tx CDR which is 80kHz in the case of the 78P235x transmit CDR. It should be noted this jitter will not effect intrinsic jitter measurements when measured with standards filters enabled. The two plots above show a close- in view of the peak -to-peak transmit phase jitter in plesiochronous (left) and synchronous modes (right). This is most noticeable on t he falling edge of a CMI Binary 0 Pulse Template Measurement. It should be noted that every isolated pulse is still compliant to the Pulse Template requirements, but mask counting and infinite persistence results will vary from scope to scope depending on acquisition methods. Be sure to center triggering position or amplitudes to avoid false failures on falling edge of CMI - Binary 0 pulse masks