AN487 STMICROELECTRONICS | Alldatasheet
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power DMOS elements, Bipolar transistors and CMOS logic. teristics of high efficiency, fast switching speed, no secondary breakdown of the power DMOS element. rent and supervisor functions like Reset and Power Fail signal for microprocessors applications. process brings a rapid increase in power IC complexity compared to conventional bipolar technology. Figure 1. BCD process and increase in power ICs complexity.
A resistor, between Rosc and GND , defines a current that is mirrored internally to charge the oscillator capacitor on the Cosc pin. The voltage at pin.Rosc is a function of Vcc value for the implementation of the feed-forward function (oscillator slope proportional to Vcc). A comparator is sensing the voltage across Cosc capacitor and dis-carge it when the ramp exceedes an upper threshold proportional to Vcc for the implementation of the feed-forward function. The Cosc discharge current is internally controlled at a value of about 20 mA. The lower threshold of the comparator is about 1.3V (2VBE). Here are reported basic equations for the oscillator: for 15V ≤ V CC ≤ 45V (1) IDISCH @ 20mA (2) for 15V ≤ VCC ≤ 45V (3) VTH. LOW = 2VBE (4) (5) Note that formula (5) does not take in account the discharge time of COSC , that is not negletable working at high FSWITCH (200 KHz), and that is dependent on COSC value. (6) By which : (7) During the discharge time of Cosc a clock pulse is generated that is available on pin.SYNC and that can be used to synchronize max 3 devices of the same family. See also fig. 6 and fig. 7 for the switching fre- quency versus value of R4 (Rosc). PWM The comparison between oscillator sawtooth and error amplifier output generates the PWM signal that feeds the driving stages. A PWM latch structure is implemented to avoid multiple pulses that could be dan- gerous for the power stage. A maximum duty cycle limitation is implemented in the PWM stage. Such limitation is obtained by the synchronization pulse generated in the oscillator section during the Cosc dis- charge time. When the pulse is present the driver is inhibited. In this way even if the error amplifier output completely overcomes the oscillator sawtooth, the power stage can not work in DC conditions, but is switched off during the clock pulse allowing a maximum duty cycle tipically in the range 90 - 95 % . SOFT START Soft start (see fig.8) is an essential function for correct start-up and to obtain a monotonically increasing output voltage, without overstressing the output power stage. Soft start operates at the start-up of the sys- tem and after the intervention of thermal protection. The function is realized through a capacitor connected to soft start pin, which is charged at constant current(about 100uA) up to a value of about 7V. During the charging time , through PNP transistor Q1 the voltage at the output of the transconduc-tance amplifier is forced to increase with the same rising speed of Css capacitor. As the capacitor is charged, I CHARGE V CC 9V BE– R OSC V TH.HIGH V CC 9V BE– FSWITCH R OSC C OSC TDISCH V TH.HIGH V TH.LOW–() C osc⋅ R osc C osc
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. about 30°C below the intervention threshold. Figure 26. Gate-charge curve for the power DMOS.