AN4660 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 27
Technical content
Datasheet sections
- 1 Hardware migration
- 1.1 Pinout compatibility
- 1.2 Boot mode compatibility
- 1.3 System bootloader
- 2 Peripheral migration
- 2.1 STM32 product cross-compatibility
- 2.2 Memory mapping
- 2.3 Flash memory
- 2.4 Embedded Flash memory
- 2.5 Flexible memory controller (FMC)
- 2.6 Interrupt vectors
- 2.7 External interrupt lines (EXTI)
- 2.8 RCC
- 2.8.1 Maximum frequency according to powe r scale parameter
- 2.9 PWR
- 2.10 RTC
- 2.11 U(S)ART
- 2.12 I2C
- 2.13 SPI
- 2.14 CRC
- 2.15 USB OTG
- 2.16 ADC
- 2.16.1 External trigger for regular channels
- 2.16.2 External trigger for injected channels
- 3 Conclusion
- 4 Revision history
- To fulfill higher product requirements, extra demands on memory size, or an increased number of I/Os.
- To meet cost reduction constraints that require to switch to smaller components and shrink the PCB area. This application note is written as an help with the analysis of the steps involved when migrating from an existing STM32F42xxx/STM32F43xxx device to STM32F74xxx/STM32F75xxx device based design. This application note provides a guideline on hardware migration and peripheral migration. To better understand the information inside this application note, the user should be familiar with the STM32 microcontroller family. For additional information, please refer to STM32F42xxx/STM32F43xxx and STM32F74xxx/STM32F75xxx reference manuals (RM0090 and RM0385) and datasheets. Documents are available for download at www.st.com.
Table 1. Applicable products
Table 3. Boot mode selection compar ison between STM32F42xxx/F43xxx and Table 4. STM32F42xxx/F43xxx and STM32F74xxx/F75xxx bootloader communication Table 5. STM32 peripheral compatibility analysis STM32F42xxx/F43xxx versus Table 6. IP bus mapping differences between ST M32F42xxx/F43xxx and STM32F74xxx/F75xxx . 10 Table 7. Flash memory differences between ST M32F42xxx/F43xxx and STM32F74xxx/F75xxx . . 11 Table 10. Interrupt vector differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . 14 Table 13. Maximum frequency compar ison between STM32F42xxx/F43xxx and Table 21. External trigger for regular channel differences between Table 22. External trigger for injected channel differences between
1 Hardware migration
1.1 Pinout compatibility
degree of freedom during the development cycle. Figure 1. Incompatible board design for LQFP100 package STM32F74xxx/F75xxx for the LQFP100 package. Table 2. STM32F42xxx/F43xxx and STM32F74xxx/F75xxx pinout differences
19 VDD VSSA
20 VSSA VREF+
21 VREF+ VDDA
22 VDDA PA0-WKUP
23 PA0-WKUP PA1
24 PA1 PA2
25 PA2 PA3
26 PA3 VSS
27 VSS VDD
28 VDD PA4
29 PA4 PA5
30 PA5 PA6
31 PA6 PA7
32 PA7 PC4
33 PC4 PC5
34 PC5 PB0
35 PB0 PB1
36 PB1 PB2
37 PB2 PE7
38 PE7 PE8
39 PE8 PE9
40 PE9 PE10
41 PE10 PE11
42 PE11 PE12
43 PE12 PE13
44 PE13 PE14
45 PE14 PE15
46 PE15 PB10
47 PB10 PB11
48 PB11 VCAP1
49 VCAP1 VSS
1.2 Boot mode compatibility
Table 3. Boot mode selection comparison between STM32F42xxx/F43xxx and
0 BOOT_ADD0
1 BOOT_ADD1
01 System
1.3 System bootloader
Table 4 shows the supported communication peripherals by the system bootloader. from AXIM interface. For more details on system bootloader refer to AN2606.
2 Peripheral migration
2.1 STM32 product cross-compatibility
- The first category is for the peripherals which are by definition common to all products. Those peripherals are identical, so they have the same structure, registers and control bits. There is no need to perform any firmware change to keep the same functionality at the application level after migration. All the features and behavior remain the same.
- The second category is for the peripherals which are shared by all STM32 products but have only minor differences (in general to support new features), so migration from one product to another is very easy and does not need any significant new development effort.
- The third category is for peripherals which have been considerably changed from one product to another (new architecture, new features...). For this category of peripherals, the migration will require a new development at application level.
- The SW compatibility mentioned in the Table 5 only refers to the register description for "low level" drivers. The Cube Hardware Abstraction Layer (HAL) is compatible between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 5 shows STM32 peripheral compatibility between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx.
2.2 Memory mapping
STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. RCC Yes Yes Yes New LSE drive modes.
- 4/3 for 100 pin package and 6/3 for other packages.
- No: not available for STM32F437xx.
- Yes: available for STM32F439xx.
Table 6. IP bus mapping differences between STM32F42xxx/F43xxx and
2.3 Flash memory
STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. STM32F75xxx reference manual (RM0385). Table 7. Flash memory differences between STM32F42xxx/F43xxx and
2.4 Embedded Flash memory
The main memory and information block organization are shown in Table 8. Table 8. Flash module 1 Mbyte single bank organization (STM32F74xxx/F75xxx)
2.5 Flexible memory controller (FMC)
Table 9. FMC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx
2.6 Interrupt vectors
2.7 External inter rupt lines (EXTI)
Table 10. Interrupt vector differences between STM32F42xxx/F43xxx and
91 NA SAI2
92 NA QuadSPI
93 NA LPTIM1
94 NA HDMI-CEC
95 NA I2C4_EV
96 NA I2C4_ER
97 NA SPDIFRX
Table 11. EXTI line differences between STM32F42xxx/F43xxx and
16 PVD output
17 RTC alarm event
18 USB OTG FS wakeup event
19 Ethernet wakeup event
20 USB OTG HS (configured in FS) wakeup event
21 RTC tamper and TimeStamp events
22 RTC wakeup event
23 NA LPTIM1 asynchronous event
2.8 RCC
between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 12. RCC differences between STM32F42xxx/F43xxx and – External clock mapped on the I2S_CKIN pin.
2.8.1 Maximum frequency accor ding to power scale parameter
STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 13. Maximum frequency comparison between STM32F42xxx/F43xxx and
2.9 PWR
Table 14. PWR differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx or to clear the wakeup pins flags.
2.10 RTC
Table 15. RTC comparison between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx
AN4660 Peripheral migration
2.11 U(S)ART
The U(S)ART is not SW compatible with STM32F42xxx/F43xxx and includes new additional features detailed in Table 16. Table 16. U(S)ART differences between STM32F42xxx/F43xxx and
Features
– LIN mode – SPI Master – IrDA SIR ENDEC block – Hardware flow control (CTS/RTS) – Continuous communication using DMA – Multiprocessor communication – Single-wire half-duplex communication Smartcard mode T = 0 and T= 1 has to be implemented by software. Number of stop bits: 0.5, 1, 1.5, 2 Support the T=0 and T=1 asynchronous protocols. Number of stop bits: 1, 1.5, 2 smartcard operation. NA – Support for ModBus communication - Timeout feature - CR/LF character recognition – Receiver timeout interrupt – Auto baud rate detection – Driver Enable – Swappable Tx/Rx pin configuration U(S)ART registers – Software not compatible
Peripheral migration AN4660
2.12 I2C
The STM32F42xxx/F43xxx and STM32F74xxx/F75xxx share the same features on the I2C, but the software and register configuration are not compatible. Table 17 presents the I2C differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx.
2.13 SPI
The STM32F42xxx/F43xxx and STM32F74xxx/F75xxx implement different features on the SPI. Table 18 presents the SPI differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 17. I2C differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx – 7-bit and 10-bit addressing mode –S M B u s – Standard mode (up to 100 kbit/s) – Fast mode (up to 400 kbit/s) – Single clock source – Programmable clock source I2C registers – Software not compatible. Table 18. SPI differences between STM32F42xxx/F43xxx and
AN4660 Peripheral migration
2.14 CRC
The STM32F74xxx/F75xxx implements similar CRC (Cyclic redundancy check) calculation unit as STM32F42xxx/F43xxx. Table 19 presents the CRC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 19. CRC differences between STM32F42xxx/F43xxx and – Single input/output 32-bit data register – CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size – General-purpose 8-bit register (can be used for temporary storage) – Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7 – Handles 32-bit data size – Fully programmable polynomial with programmable size (7, 8, 16, 32bits) – Handles 8-,16-, 32-bit data size – Programmable CRC initial value – Input buffer to avoid bus stall during calculation – Reversibility option on I/O data CRC registers – Software compatible. – STM32F74xxx/F75xxx include new features.
Peripheral migration AN4660
2.15 USB OTG
Table 20 presents USB OTG differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 20. USB OTG differences between STM32F42xxx/F43xxx and – Universal Serial Bus revision 2.0 – Full support for the USB On-The-Go (USB OTG). FS mode: – 1 bidirectional control endpoint – 3 IN endpoints (bulk, interrupt, isochronous) – 3 OUT endpoints (bulk, interrupt, isochronous HS mode: – 6 bidirectional endpoints (including EP0) – 12 host mode channels FS mode: – 1 bidirectional control endpoint – 5 IN endpoints (bulk, interrupt, isochronous) – 5 OUT endpoints (bulk, interrupt, isochronous) HS mode: – 8 bidirectional endpoints (including EP0) – 16 host channels with periodic – USB internal connect/disconnect feature with an internal pull-up resistor on the USB D + (USB_DP) line. NA – Independent VDDUSB power supply allowing lower VDDCORE while using USB. Buffer memory FS mode: – 1.25Kbytes data FIFOs – Management of up to 4 Tx FIFOs (1 for each IN end point) + 1 Rx FIFO. HS mode: – 4 KB total RAM FS mode: – 1.25Kbytes data FIFOs – Management of up to 6 Tx FIFOs (1 for each IN end point) + 1 Rx FIFO. HS mode: – 4 KB total RAM Low-power modes FS mode: – USB suspend and resume HS mode: – No LPM supported FS mode: – USB suspend and resume – Link power management (LPM) support HS mode: – Yes LPM supported Configuration – SW not compatible
2.16 ADC
features except for external triggers in regular and injected channels. injected channels between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx.
2.16.1 External trigger for regular channels
0000 TIM1_CH1 event TIM1_CC1 event
0001 TIM1_CH2 event TIM1_CC2 event
0010 TIM1_CH3 event TIM1_CC3 event
0011 TIM2_CH2 event TIM2_CC2 event
0100 TIM2_CH3 event TIM5_TRGO event
0101 TIM2_CH4 event TIM4_CC4 event
0110 TIM2_TRGO event TIM3_CC4
0111 TIM3_CH1 event TIM8_TRGO event
1000 TIM3_TRGO event TIM8_TRGO(2) event
1001 TIM4_CH4 event TIM1_TRGO event
1010 TIM5_CH1 event TIM1_TRGO(2) event
1011 TIM5_CH2 event TIM2_TRGO event
1100 TIM5_CH3 event TIM4_TRGO event
1101 TIM8_CH1 event TIM6_TRGO event
1110 TIM8_TRGO event NA
2.16.2 External trigger for injected channels
0000 TIM1_CH4 event TIM1_TRGO event
0001 TIM1_TRGO event TIM1_CC4 event
0010 TIM2_CH1 event TIM2_TRGO event
0011 TIM2_TRGO event TIM2_CC1 event
0100 TIM3_CH2 event TIM3_CC4 event
0101 TIM3_CH4 event TIM4_TRGO event
0110 TIM4_CH1 event NA
0111 TIM4_CH2 event TIM8_CC4 event
1000 TIM4_CH3 event TIM1_TRGO(2) event
1001 TIM4_TRGO event TIM8_TRGO event
1010 TIM5_CH4 event TIM8_TRGO(2) event
1011 TIM5_TRGO event TIM3_CC3 event
1100 TIM8_CH2 event TIM5_TRGO event
1101 TIM8_CH3 event TIM3_CC1 event
1110 TIM8_CH4 event TIM6_TRGO event
3 Conclusion
This application note is a useful complement to the datasheets and reference manuals, which gives a simple guideline to migrate from an existing STM32F42xxx/F43xxx device to STM32F74xxx/F75xxx device.
4 Revision history
Table 23. Document revision history 31-Mar-2015 1 Initial release.