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/C0080 /C0115 /C0111/C0110/C0111 /C0115 AN460 Using the P82B96 for bus interface IC12a and IC28 Data Handbook
2001 Feb 14
22001 Feb 14
output path, from the backward input signal path. connected with long wiring which could introduce noise. difficult interfacing tasks. Sx lines at I2C nodes that include P82B96. interconnection, and distance. exceed the supply rail levels. collector output a pull-up resistor is applied. the chip supply of 10 V, Sx has a 1600Ω pull-up to a 5 V supply. NOTE : The logic voltages and currents at ‘SDA’ are set by VCC and pull-up. Figure 1. Interfacing an “I2C” type of bus with different logic levels Horiz: 200ns/div. VertL 2V/div. Figure 2. Propagation Sx to Tx Horiz: 200ns/div. VertL 2V/div. Figure 3. Propagation Rx to Sx
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opto-couplers to provide galvanic separation. changing the type of opto-coupler or the circuit values. potential differences require it. This example shows the simplicity of a low speed application. Figure 4. Galvanic isolation of I2C nodes via opto-couplers Figure 5. Opto-isolation of I2C nodes via 6N137 for 100 kHz operation
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converted to CAN bus software data format by the PCA82C250. the application of the P82B96. These are discussed below. diodes can cause unpredictable behavior. In applications where these voltage ratings could be exceeded, e.g. and the buffered bus pins as shown in Figure 7. Figure 6. Linking I2C nodes via a differential bus
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Figure 7. Driving a high voltage, low impedance “I2C” bus mW dissipation can be exceeded within a very short time. short-circuit does not occur. resistor used and the total capacitive load presented to the bus. the varying current in the bus pull up resistor. the Rx threshold may need to be taken into account. Rx. The low at Rx enables a ‘clamp’ at 1V, the logic low, on Sx. by its load capacitance and the pull up resistor used at Tx. waveforms are shown in Figure 8. opto-couplers in the loop will exaggerate these delays (see Figure 4). Horiz: 200ns/div. VertL 2V/div. Figure 8. Low to High propagation of Sx with Tx linked to RX
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presents difficulties: forgive the occasional use of these descriptions. We have named one side of the P82B96 the ‘I2C’ side (Sx and Sy). product. We refer to the linked Rx/Tx I/O as the ‘buffered’ bus side. static sink capability will overlap some P82B715 applications. drives — and P82B96 extends operation down to 2 V supply. address this in the specifications for the P82B96.
- The 30 mA Tx and Ty outputs do not guarantee full 100 kHz
- If the buffered side is used to directly drive long wires then
the use of external schottky diode and zener clamps (Figure 7). Table 1. Table of drive capability
3.3 V ±10% bus
15 V bus, 500Ω
15 V bus > 500Ω
Philips Semiconductors Application note AN460Using the P82B96 for bus interface
2001 Feb 14 7
Treatment of (unused) I/O pins In some systems, one or other side of the P82B96 might be required to be ‘hot plugged’ to the I2C bus of some other separate equipment. This will require some pull up capability to be provided on both sides of the plug. Each input pin (Sx or Rx) is a high impedance input and cannot be left floating. Internal pull-ups have not been used because they would only pull-up to the IC supply (V CC ), thereby demanding that VCC cannot be lower than the connected bus voltages. In the P82B96 any input may be pulled up to +15 V, independent of VCC . No currents will flow into the I/O pins (except when outputs drive a bus low). The inputs are like LM324 inputs, based on PNP input transistors, so they source tiny currents when externally driven low. External pull up resistors fitted at Sx pins should cause the specified minimum 200 µA to flow when that input is low. The Rx input should be treated just like any op-amp input and not left floating. A pull-up of 100 K should cope with PCB leakage in humid conditions. Diodes have not been fitted between I/O pins and VCC , to allow them to be pulled to voltages above the chip’s VCC . This permits, for example, use of the P82B96 on a 3 V supply, driving a 3 V buffered bus, to interface with a normal 5 V I 2C input. It also allows the I2C busses to remain active even if the P82B96 VCC fails. Failure of VCC and consequences for bus operation The P82B96 maintains its function for VCC below 2 V. At normal temperatures it starts to shut off at around 1.2 V. That means that if the normal VCC supply is 5 V, and that supply was to fall to 2 V, then it just retains normal operation — it cannot ‘release’ the busses even though the supply is now only 40% of normal. During failure of the VCC power supply no abnormal signals are caused on any I/O until the supply falls below a value below which point there will be no signals transmitted through the chip, and all I/Os will become open circuit. That voltage is of the order of 1 V. Margins on switching levels There are certain constraints that determine the two low levels on the I2C bus interface Sx and Sy. The I2C bus must always be driven below the lowest level that guarantees a low on any bus to which it is connected. For a normal 5 V I2C bus the minimum low is 1.5 V. The P82B96 guaranteed low level is set well below this, at 1V maximum for the I2C maximum allowed 3 mA. (It assumes a normal 5 V I2C bus on the Sx/Sy side of the buffer, but this should not be taken as a restriction) The externally connected I 2C chips must, in turn, pull the I2C pin below the threshold required to set Tx/Ty low. Those external chips all have a maximum static low specification of 0.4 V at 3 mA. Therefore the typical threshold for the Sx and Sy inputs is 650 mV at 25°C, with 600 mV as the minimum. If there was not a difference between the Sx low output (the larger voltage) at the smallest permitted load current, and the Sx input threshold (a lesser voltage) the chip would latch. As the Sx sink current decreases the output low level at Sx decreases. For this reason a minimum sink current at Sx is specified (200 µA) The temperature coefficient on the input and output thresholds of Sx and Sy is –2 mV/K. The other side (Tx/Rx and Ty/Ry) is designed for connection to any bus from 2 V to 15 V. The typical threshold switching level is 50% of VCC . Tolerances tighter than the normal 70/30% levels have been specified so the guaranteed noise margins, especially when working with long 15V busses, are improved.
Philips Semiconductors Application note AN460Using the P82B96 for bus interface
2001 Feb 14 8
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors
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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. /C0080 /C0115 /C0111/C0110/C0111 /C0115