AN4566 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 The STM32 DAC system
- 1.1 DAC equivalent circuit
- 1.2 DAC speed on the specification
- 1.3 External OpAmp implementation
- 1.4 Digital data update rate
- 1.5 Summary
- 2 Example
- 2.1 External OpAmp choice
- 2.2 Software implementation
- 2.2.1 Digital sine waveform pattern preparation
- 2.2.2 Setting the sine waveform frequency
- 2.2.3 Offset calibration
- 2.2.4 Output gain calibration
- 2.3 Hardware implementation
- 3 Measurements
- 3.1 Board modification
- 3.2 Measurement results
- 4 Conclusions
- 5 Revision history
to operate up to 1 Msps (megasamples per second). operational amplifiers (OpAmps). example focusing on 5 Msps sine wave generation is presented in Section 2. Table 1. Applicable products
1 The STM32 DAC system
1.1 DAC equivalent circuit
and the output impedance, as shown in Figure 1. The output impedance of the DAC is constant, ind ependently from the digital input signal. RDAC = 2*Ra (S1 and S2 switches are open). and the output impedance is almost zero thanks to the feedback loop. Figure 1. DAC equivalent circuit
1.2 DAC speed on the specification
(equivalent to a frequency of 555 kHz).
1.3 External OpAmp implementation
DACOUT capacitance (Cp) will determine the conversion time. Figure 2. External OpAmp configuration DAC on chip of the STM32, otherwise it will create a DAC gain error. On chip semiconductor resistors usually feature a very wide spread on the absolute value. capacitor on the DACOUT will form the RC filter. This RC filter limit the speed performance. For the voltage follower mode, it is not necessary to perform the gain calibration.
1.4 Digital data update rate
the data is move to the DAC Output Register (DOR) for the conversion. transferring the data from RAM to DAC. actions by the CPU. This keeps CPU resources free for other operations. combination with the data transfer done by the DMA.
- the clock cycle of the APB (DAC clock);
- the DMA transfer cycle from memory to the DAC (includes the AHB to APB bridge);
- the trigger mechanism itself. The DAC on STM32F407x microcontrollers is running on the APB1:
- three cycles after the trigger, DHR data is moved to the DOR register;
- at the same time a DMA request is generated from DAC to DMA;
- DMA transfer takes at least one APB clock cycle. So a total of 4APB clock cycles are needed to update the DAC DOR register data. As APB1 maximum clock is 42 MHz (for ST32F407x), 10.5 Msps is the maximum update rate for the DAC output register when timer trigger and the DMA are used for the data update. The minimum transfer clock cycle by DMA to the DAC are not the same for all STM32 microcontrollers, because of the different bus configuration. Table 2 shows the maximum sampling rate for different STM32 products.
Table 2. Maximum sampling time for different STM32 microcontrollers
The STM32 DAC system AN4566 Note: Values reported in Table 2 have been measured on the bench, when bus is not used by any other system: in real applications it’s necessary to have some margin.
1.5 Summary
By using external high speed OpAmp, it is possible to extend the speed performance of the STM32 DACs more than 1 Msps. In Section 2 we will provide an example showing how to use this technique on STM32 products.
2 Example
The example of the high speed use of the DAC is based on STM32F407, it shows how to generate a 200 kHz sine wave by the DAC operating at 5 Msps.
2.1 External OpAmp choice
As indicated before, the external OpAmp will define the DAC total performance. To choose the OpAmp, the following parameters must be considered.
- slew Rate;
- gain bandwidth (GBW);
- open loop gain;
- supply voltage range;
- output voltage swing performance;
- input common mode voltage range;
- minimum stable gain. If lowest code to highest code transient on 5 Msps case with VREF voltage is 3.3 V, the OpAmp needs to have a slew rate higher than 3.3 * 5 * 106 = 16.5 Volts/µs. If STM32 DAC is working at 3.3 V, it’s possible to use the OpAmp 3.3 V supply (it’s also possible to consider another analog supply rail, actually this is the option used in the example). It is recommended to have minimum two times of sampling speed of the gain bandwidth, so, for 5 Msps, GBW needs to be wider than 10 MHz. To keep good DAC linearity, open loop gain must be higher than 60 dB. If it’s needed to have the output voltage near the supply voltage, then the output voltage swing of the OpAmp should preferably be rail to rail, otherwise, should voltage swing be near to the supply or ground rail, signal will be saturated and this will result in distortion. Even the OpAmp negative input is fixed at the reference voltage level, it is necessary to verify that the input common voltage range covers the reference voltage level with a margin. The used OpAmp gain is about -1, so the OpAmp must be stable at this gain. By considering above criteria, LMH6645/6646/6647 from Texas Instruments fit the requirements:
- slew rate: 22 Volts/µs;
- gain band width: 55 MHz;
- open loop gain: 87 dB;
- supply voltage range: 2.5 to 12 V;
- input Common Mode Voltage 0.3 V beyond rails;
- output Voltage Swing 20 mV from Rails;
- stable from gain +1.
2.2 Software implementation
For this example the STM32F407 is powered with a 3.3 V supply.
2.2.1 Digital sine wavef orm pattern preparation
As described in the AN3126, sine wave pattern needs to be prepared according to the following formula YSineDigital x() 2Π x nS ⎛⎞ 1+sin⎝⎠ ⎛⎞ 0xFFF 1+ Digital inputs are converted to output voltages by linear conversion between 0 and VREF+. The analog output voltage on each DAC channel pin is determined as: DACOutput VREF DOR So the analog sine waveform can be determined by the following equation YSineAnalog x() 3.3Volt Y SineDigital x() 0xFFF⁄⋅= The table can be saved in the memory and transferred by DMA. The transfer is triggered by the same timer that triggers the DAC.
2.2.2 Setting the sine waveform frequency
To set the frequency of the sine wave signal, it’s necessary to set the frequency of the Timer Trigger output. The frequency of the produced sine wave is f Sinewave = fTimerTRGO / nS If TIMx_TRGO is 5 MHz (nS=25), then the frequency of the DAC sine wave is 200 kHz. To have the exact frequency on the output, syste m clock need to be adjusted, so that the timer can generate exactly 5 MHz. In STM32F407 system, some timer can run with a clock frequency twice the one of the APB1 clock, so resolution is two times better than APB1 clock. However DAC will capture the trigger signal by APB1 clock, so the DAC timing cannot be better than APB1 clock. For example, if the timer is programmed with 25 clock cycles (corresponding to 12.5 cycles of the APB1 clock) then the DAC trigger occurs 12 times, then 13 times, alternately. So one APB1 clock results in jitter on every sampling period.
- System Clock Source = PLL (HSE)
- SYSCLK (Hz) = 160000000
- HCLK (Hz) = 160000000
- AHB Prescaler =1
- APB1 Prescaler = 4
- APB2 Prescaler = 2
- HSE Frequency (Hz) = 8000000
- PLL_M = 8
- PLL_N = 320
- PLL_P = 2
- PLL_Q = 7 For the trigger, TIM6 was used. With this configuration, 80 MHz is the timer clock, so, to get 5 MHz trigger, the prescaler was set to 1 (PSC=0), and the counter was set to 16 (CNT=15).
2.2.3 Offset calibration
OpAmp itself, and that coming from the external VREF resistor ladder. available ADC channels of the STM32 microcontrollers.
- measure the OpAmp output by the ADC;
- set up the DAC DOR of the ADC result of last measurement (in this case 2065);
- verify the result by ADC (in this case, 2048, still 1LSB offset).
2.2.4 Output gain calibration
feedback resistance of the external OpAmp. available STM32 ADC channels. Table 3. Example of the offset calibration measurement
- measure the OpAmp output by the ADC;
- measure the OpAmp output by the ADC.
So the Amplifier has a gain of 1.0508, obtained as (3135 - 983) / 2048. supply rail and ground rails. By using the above equation, Table 5 can be generated. Table 4. Example of the calibration measurement Table 5. Example of digital sample values
Table 5. Example of digital sample values (continued)
2.3 Hardware implementation
As described in Section 2.1, an external component has been chosen. The actual circuit is shown in Figure 3, the component values are listed in Table 6. C1 was added to avoid overshoot on the output signal. Figure 3. Circuit implementation Table 6. Component values
3 Measurements
3.1 Board modification
has been removed from the board.
3.2 Measurement results
The output signal is shown in Figure 4, while Figure 5 is the corresponding FFT analysis. Figure 4. Output signal
Figure 5. FFT result The 2nd and 3rd harmonics are around the noise level.
4 Conclusions
The DAC used by STM32F4 microcontrollers has been characterized up to 1 Msps: by using high speed external OpAmp, we have demonstrated it can operate up to 5 Msps. Additional remarks:
- by using high speed sampling rate, it’s possible to reduce the anti-aliasing filter’s order;
- by using the on chip ADC, it is possible to calibrate the output swing and the offset.
5 Revision history
Table 7. Document revision history 03-Nov-2014 1 Initial release.