AN4506 STMICROELECTRONICS | Alldatasheet
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Technical content
Datasheet sections
- 1 Registers
- 2 Operating modes
- 2.1 Power-down mode
- 2.2 Sleep mode
- 2.3 Low ODR mode
- 2.4 Normal mode
- 2.5 Switching modes
- 3 Reading angular rate data
- 3.1 Startup sequence
- 3.2 Using the status register
- 3.3 Using the data-ready (DRDY) signal
- 3.4 Using the block data update (BDU) feature
- 3.5 DEN function
- 3.5.1 Level-sensitive trigger stamping (LVLen = 1; EXTRen = 0; IMPen = 0)
- 3.5.2 Pulse sensitive trigger (LVLen = 1; EXTRen = 0; IMPen = 1)
- 3.5.3 Edge-sensitive trigger (LVLen = 0; EXTRen = 1; IMPen = 0)
- 3.6 Understanding angular rate data
- 3.6.1 Data alignment
- 3.6.2 Big-little endian selection
- 3.6.3 Example of angular rate data
- 4 Digital filters
- 4.1 Filter configuration
- 4.2 Low-pass filters
- 4.3 High-pass filter
- 4.3.1 Normal mode
- 4.3.2 REFERENCE mode
- 4.3.3 Autoreset
- 5 Interrupt generation
- 5.1 Interrupt pin configuration
L3GD20H: 3-axis digital output gyroscope By Michele Ferraina Introduction This document is intended to provide information on the use of, and application hints related to, ST’s L3GD20H 3-axis digital gyroscope. The L3GD20H is a 3-axis angular rate sensor with a digital I2C/SPI serial interface standard output. The device has a full scale of ±245/±500/±2000 dps and is capable of measuring rates with a user-selectable bandwidth. The device may be configured to generate interrupt signals by detecting an independent wake-up event. Thresholds and timing of the interrupt generator are programmable by the end user on the fly. The L3GD20H has an integrated 32-level first in first out (FIFO) buffer allowing the user to store data in order to limit intervention by the host processor. The L3GD20H is available in a small thin plastic land grid array package (LGA-16 3x3x1) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. The ultra-small size and weight of the SMD package make it an ideal choice for handheld portable applications such as smartphones, wearables or any other application where reduced package size and weight are required.
1 Registers
Table 1. Registers
2 Operating modes
mode, Sleep mode, Low ODR mode and Normal mode. Low_ODR and Normal mode) and output data rate (Table 2 and Table 3). Table 2. Operating mode selection Table 3. Data rate configuration
Table 4 shows the typical values of power consumption for the different operating modes. Power consumption in Normal mode is independent of the selected ODR.
2.1 Power-down mode
sampled in memory before going into Power-down mode.
2.2 Sleep mode
2.3 Low ODR mode
bits in the CTRL1 register: 12.5 Hz, 25 Hz and 50 Hz. Refer to Table 3 for ODR and bandwidth configurations. Data interrupt generation is active and configured through the IG_CFG register.
2.4 Normal mode
In Normal mode, data are generated at the data rate (ODR) selected through the DR bits. Data interrupt generation is active and configured through the IG_CFG register. Table 4. Power consumption
2.5 Switching modes
The delay in order to switch modes is shown in Table 5.
3 Reading angular rate data
3.1 Startup sequence
the embedded flash to the internal registers. When the boot procedure is completed, i.e. ODR) mode and to enable at least one of the axes. Table 5. Turn-on time Starting mode Target mode Turn-on time - typ.
Reading angular rate data AN4506
3.2 Using the status register
The device is provided with a STATUS register which should be polled to check when a new set of data is available. The reading procedure should be the following: The check performed at step 3 allows the user to understand whether the reading rate is adequate compared to the data production rate. If one or more angular rate samples have been overwritten by new data, because of an insufficient reading rate, the ZYXOR bit of the STATUS register is set to 1. The overrun bits and the new data available bits are automatically cleared when all the data present inside the device have been read and new data have not been produced in the meantime.
3.3 Using the data-ready (DRDY) signal
The device may be configured to have one HW signal to determine when a new set of measurement data is available for reading. This signal is represented by the XYZDA bit of the STATUS register. The signal can be driven to the DRDY/INT2 pin by setting the I2_DRDY bit to 1 in the CTRL3 register and its polarity to active-low or active-high through the H_Lactive bit of the CTRL3 register (see Section 5.1). The data-ready signal rises to 1 when a new set of angular rate data has been generated and is available for reading. The interrupt is reset when the higher part of one of the enabled channels has been read (29h, 2Bh, 2Dh). 1. Read STATUS 2. If STATUS(3) = 0 then go to 1 3. If STATUS(7) = 1 then some data have been overwritten 4. Read OUT_X_L 5. Read OUT_X_H 6. Read OUT_Y_L 7. Read OUT_Y_H 8. Read OUT_Z_L 9. Read OUT_Z_H 10. Data processing 11. Go to 1
Figure 2. Data-ready signal
3.4 Using the block data update (BDU) feature
strongly recommended to set the BDU (block data update) bit to 1 in the CTRL4 register. both MSB and LSB parts of the data are read. Data must be read starting from the lower address.
3.5 DEN function
modes can be used: level-sensitive, pulse-sensitive and edge-sensitive trigger.
3.5.1 Level-sensitive trigger stamping (LVLen = 1; EXTRen = 0; IMPen = 0)
the axis selected through the Xen, Yen, and Zen bits in CTRL_REG1 (20h). Data are stored inside the FIFO with the internally selected ODR. Table 6. DEN configurations
Figure 3. Data synchronization: level sensitive Figure 4. Level-sensitive trigger stamping
3.5.2 Pulse sensitive trigger (LVLen = 1; EXTRen = 0; IMPen = 1)
occurs, the LSB bit of the next generated gyroscope X, Y, Z output data is set to 0. Figure 5. Data synchronization: pulse sensitive
3.5.3 Edge-sensitive trigger (LVLen = 0; EXTRen = 1; IMPen = 0)
gyroscope output registers are not updated. Figure 6. Data synchronization: edge sensitive
3.6 Understanding angular rate data
expressed as a 2’s complement number.
3.6.1 Data alignment
Angular rate data are represented as 16-bit numbers and are left-justified.
3.6.2 Big-little endian selection
endian and big-endian data representations. This mode corresponds to bit BLE (in CTRL4 register) reset to 0 (default configuration). memory at the lowest address, and the low-order byte at the highest address.
3.6.3 Example of angular rate data
4 Digital filters
Table 7. Output data registers content vs. angular rate (FS = 245 dps) Table 8. CTRL5 register
Figure 7. Low-pass/high-pass filter connections block diagram
4.1 Filter configuration
Table 9. Out_Sel configuration setting Table 10. IG_SEL configuration settings
4.2 Low-pass filters
(ft) for the low-pass filters are shown in Table 13. Table 11. Low-pass filter cutoff frequency
4.3 High-pass filter
Table 12. CTRL2 register Table 13. High-pass filter cut-off frequencies [Hz] Table 14. High-pass filter mode configuration
4.3.1 Normal mode
instantly deleting the DC component of the angular rate. Figure 8. High-pass filter reset by reading the REFERENCE register
4.3.2 REFERENCE mode
Table 15. REFERENCE mode LSB value
Figure 9. REFERENCE mode
4.3.3 Autoreset
occurs. REFERENCE is, however, used to set the filter instantaneously. Note: The XYZ dataset used to reset the filter is the one after the interrupt. Figure 10. Autoreset
5 Interrupt generation
INT2 pin is dedicated to DRDY and FIFO interrupts.
5.1 Interrupt pin configuration
ready or the interrupt signals. The functionality of the pins is selected through CTRL3(22h). Refer to Table 16, Table 17 and to the block diagram in Figure 11 for more details. Figure 11. Interrupt signals and interrupt pins Table 16. CTRL3 register Table 17. CTRL3 description
5.2 Interrupt configuration
involved in the interrupt generation behavior are IG_CFG, IG_THS and IG_DURATION. the IG_SRC register it is possible to understand which condition happened. Table 18. IG_CFG register Table 19. IG_CFG description Cleared by reading IG_SRC reg. Table 20. Interrupt mode configuration
0 OR combination of interrupt events
1 AND combination of interrupt events
5.3 Threshold
reference angular rates used by interrupt generation circuitry. The value of 1 LSB of the threshold depends on the selected full scale (Table 23).
5.4 Duration
interrupt event to be recognized. Duration steps and maximum values depend on the ODR chosen. Table 21. IG_THS_xH register Table 22. IG_THS_xL register Table 23. Threshold LSB value Table 24. IG_DURATION register Table 25. IG_DURATION description Table 26. Duration LSB value in Normal mode
Wait = ‘0’: the interrupt falls immediately if signal crosses the selected threshold (Figure 12). counter register (Figure 13). Figure 12. Wait disabled
- Wait bit = ‘0’ /barb2right/barb2rightInterrupt disabled as soon as condition is no longer valid (ex: Rate value below threshold) Rate (dps) Rate Threshold t(n) t(n) t(n) Interrupt Counter Duration Value “Wait” Disabled
Figure 13. Wait enabled
5.5 Selective axis movement and wake-up interrupts
reading the IG_SRC register it is possible to understand which condition happened. generation block is represented in Figure 14. the enabled axes are passing the threshold. read of the IG_SRC register is performed. threshold must be passed to generate the interrupt request. Figure 14. No-move, wake-up interrupt generator
IG_THS. Refer to Figure 15 for more details. Figure 15. NM_WU_CFG high and low
5.5.1 Wake-up
defined threshold (Figure 16). Figure 16. Wake-up interrupt
5.5.2 HP filter bypassed
and its occurrence is signalled through the use of the INT1 pin.
AN4506 Interrupt generation
5.5.3 Using the HP filter
The code provided below gives a basic routine which shows the practical use of the wake- up feature performed on high-pass filtered data. In particular, the device is configured to recognize when the high-frequency component of the angular rate applied along either the X, Y, or Z-axis exceeds a preset threshold (100 dps is used in the example). The event which triggers the interrupt is latched inside the device and its occurrence is signaled through the use of the INT1 pin.
1 Write 0Fh into CTRL1 // Turn on the sensor and enable X, Y, and Z
// ODR = 100 Hz
2 Write 00h into CTRL2 // High-pass filter disabled
3 Write 80h into CTRL3 // Interrupt driven to INT1 pad
4 Write 00h into CTRL4 // FS = 245 dps
5 Write 34h into IG_THS_XH // Threshold = 100 dps
6 Write 3Eh into IG_THS_XL // Threshold = 100 dps
7 Write 00h into IG_DURATION // Duration = 0
8 Write 02h into IG_CFG // Enable XH interrupt generation
9 Poll INT1 pad; if INT1=0 then go to 8 // Poll INT1 pin waiting for the
// wake-up event
10 Read IG_SRC // Return the event that has triggered the
// interrupt 11 (Wake-up event has occurred; insert your code here) // Event handling
12 Go to 8
// ODR = 100 Hz
2 Write 00h into CTRL2 // High-pass filter in Normal mode
5 Write 05h into CTRL5
// Data in DataReg and FIFO are high-pass filtered. // High-pass-filtered data are used for interrupt // generation
6 Write 34h into IG_THS_XH // Threshold = 100 dps
7 Write 3Eh into IG_THS_XL // Threshold = 100 dps
8 Write 34h into IG_THS_YH // Threshold = 100 dps
9 Write 3Eh into IG_THS_YL // Threshold = 100 dps
10 Write 34h into IG_THS_ZH // Threshold = 100 dps
11 Write 3Eh into IG_THS_ZL // Threshold = 100 dps
12 Write 00h into IG_DURATION // Duration = 0
without waiting for the filter to settle.
5.6 Selective axis movement detection
Z-axis. This means the device is doing a pure yaw rotation. Figure 17. No-move interrupt
13 Read REFERENCE
14 Write 6Ah into IG_CFG // Enable XH, YH and ZH interrupt generation.
15 Poll INT1 pad; if INT1=0 then go to 8 // Poll INT1 pin waiting for the
16 Read IG_SRC // Return the event that has triggered the
18 Go to 15
AN4506 Interrupt generation This paragraph provides the basics for the use of the selective axis movement detection feature. Here below is reported the example code which implements the SW routine for the selective axis movement recognition: The code sample exploits a threshold set at 60 dps selective axis movement detection and the event is notified by the hardware signal INT1. At step 7, the IG_DURATION register is configured like this to ignore events that are shorter than 1/DR = 1/100 ~= 10 msec in order to avoid false detections. Once the selective axis movement detection has occurred, a read of the IG_SRC register clears the request and the device is ready to recognize other events. // ODR = 100 Hz
6 Write 1Fh into IG_THS_XH // Threshold = 60 dps
7 Write 58h into IG_THS_XL // Threshold = 60 dps
8 Write 1Fh into IG_THS_YH // Threshold = 60 dps
9 Write 58h into IG_THS_YL // Threshold = 60 dps
10 Write 1Fh into IG_THS_ZH // Threshold = 60 dps
11 Write 58h into IG_THS_ZL // Threshold = 60 dps
12 Write 01h into IG_DURATION // Duration = 10 ms
13 Write 65h into IG_CFG // Enable XL, YL and ZH interrupt generation in AND
// configuration. Interrupt latched
14 Poll INT1 pad; if INT1=0 then go to 8 // Poll INT1 pin waiting for the
// wake-up event
15 Read IG_SRC // Return the event that has triggered the
// interrupt 16 (Wake-up event has occurred; insert your code here) // Event handling
17 Go to 15
6 First-in first-out (FIFO) buffer
three output channels, X, Y, and Z. and burst the significant data out from the FIFO. dedicated interrupts on the DRDY/INT2 pin.
6.1 FIFO description
data are stored in the 16-bit 2’s complement left-justified representation. to the FIFO at the selected output data rate (ODR). oldest value is overwritten. Table 27. FIFO buffer full representation (32nd sample set stored)
sample is overwritten. The new oldest sample set is made available in the output registers. registers (28h to 2Dh) always contain the oldest FIFO sample set.
6.2 FIFO registers
6.2.1 Control register 5 (0x24)
current angular rate value but they always contain the oldest value stored in FIFO. Table 28. FIFO overrun representation (33 Table 29. FIFO enable bit in CTRL5
Figure 18. FIFO_EN connection block diagram
6.2.2 FIFO control register (0x2E)
This register is dedicated to FIFO mode selection and FIFO threshold configuration.
- FM[2:0] = (1,0,0): Bypass-to-Stream mode
- FM[2:0] = (1,1,0): Dynamic Stream mode
this value, the FTH bit is set to “1” in the FIFO source register. Table 30. FIFO_CTRL register
6.2.3 FIFO source register (0x2F)
FTH bit is set high when FIFO content exceeds FIFO threshold. value. The OVRN bit is reset when the first sample set has been read. EMPTY flag is set high when all FIFO samples have been read and FIFO is empty. Register content is updated synchronous to the FIFO write and read operation. generate a dedicated interrupt on the DRDY/INT2 pin by configuring CTRL3. INT2_Empty bit drives Empty event (EMPTY) on the DRDY/INT2 pin. Table 31. FIFO_SRC register Table 32. FIFO_SRC_REG behavior assuming FTH[4:0] = 15 Table 33. CTRL3 (0x22)
First-in first-out (FIFO) buffer AN4506
6.3 FIFO modes
The L3GD20H FIFO buffer can be configured to operate in five different modes selectable by the FM[2:0] field in the FIFO_CTRL register. Available configurations ensure a high level of flexibility and extend the number of functions usable in application development. Bypass, FIFO, Stream, Dynamic Stream, Stream-to-FIFO, Bypass-to-Stream and Bypass- to-FIFO modes are described in the following paragraphs.
6.3.1 Bypass mode
When Bypass mode is enabled, FIFO is not operational: buffer content is cleared, output registers (0x28 to 0x2D) are frozen at the last value loaded, and the FIFO buffer remains empty until another mode is selected. Follow these steps for Bypass mode configuration: 1. Turn on FIFO by setting the FIFO_En bit to “1” in control register 5 (0x24). After this operation the FIFO buffer is enabled but isn’t collecting data, output registers are frozen to the last sample set loaded. 2. Activate Bypass mode by setting the FM[2:0] field to “000” in the FIFO_CTRL register (0x2E). If this mode is enabled, the FIFO_SRC register (0x2F) is forced equal to 0x20. Bypass mode must be used in order to stop and reset the FIFO buffer when a different mode is operating. Note that setting the FIFO buffer in Bypass mode clears the whole buffer content.
6.3.2 FIFO mode
In FIFO mode, the buffer continues filling until full (32 sample sets stored,) then it stops collecting data and the FIFO content remains unchanged until a different mode is selected. Follow these steps for FIFO mode configuration: 1. Turn on FIFO by setting the FIFO_En bit to “1” in control register 5 (0x24). After this operation the FIFO buffer is enabled but is not collecting data, output registers are frozen to the last samples set loaded. 2. Activate FIFO mode by setting the FM[2:0] field to “001” in the FIFO control register (0x2E). By selecting this mode, FIFO starts data collection and the source register (0x2F) changes according to the number of samples stored. At the end of the procedure, the FIFO source register is set to 0xDF and the OVRN flag generates an interrupt if the INT2_ORun bit is set to 1 in the CTRL3 register. Data can be retrieved when the OVRN is “1”, by performing a 32 sample set read from the output registers. Data can also be retrieved on the FTH flag instead of the OVRN when the application requires a lower number of samples. Communication speed is not so important in FIFO mode because data collection is stopped and there is no risk of overwriting data already acquired. Before restarting FIFO mode, at the end of the reading procedure, it is necessary to set Bypass mode (to clear the FIFO content).
- Set FIFO_En = 1: enable FIFO;
- Wait for OVRN or FTH interrupt;
- Read data from gyroscope output registers;
- Set FM[2:0] = (0,0,0): enable Bypass mode;
Figure 19. FIFO mode behavior
6.3.3 Stream mode
configuration is used to stop this mode.
- Turn on FIFO by setting the FIFO_En bit to “1” in the CTRL5 register (0x24). After this
frozen to the last sample set loaded.
- Activate Stream mode by setting the FM[2:0] field to “010” in the FIFO_CTRL register
the application requires a lower number of samples (see Section 6.3.4). Figure 20. Stream mode fast reading behavior
- FIFO sample set (6 bytes) is read faster than 1*ODR: data are correctly retrieved
because a free slot is made available before new data is generated.
- FIFO sample set (6 bytes) is read synchronous to 1*ODR: data are correctly retrieved
- FIFO sample set (6 bytes) is read slower than 1*ODR; in this case some data are lost
between the current ODR and the FIFO sample set reading rate.
6.3.4 Dynamic Stream mode
FIFO threshold level is lower than 31, to avoid a multiple read of the same sample. Figure 23. Stream mode with threshold Figure 24. Dynamic Stream mode with threshold number of the new data available in FIFO depends on the previous reading.
AN4506 First-in first-out (FIFO) buffer way, the number of new data available in the FIFO does not depend on the previous reading. Follow these steps for Dynamic Stream mode configuration: 1. Turn on FIFO by setting the FIFO_En bit to “1” in the CTRL5 register (0x24). After this operation the FIFO buffer is enabled but is not collecting data, output registers are frozen to the last sample set loaded. 2. Activate Dynamic Stream mode by setting the FM[2:0] field to “110” in the FIFO_CTRL register (0x2E).
6.3.5 Stream-to-FIFO mode
This mode is a combination of the Stream and FIFO modes described above. In Stream-to- FIFO mode, the FIFO buffer starts operating in Stream mode and switches to FIFO mode when the selected interrupt occurs. Follow these steps for Stream-to-FIFO mode configuration: 1. Configure desired interrupt generator using register IG_CFG (0x30). 2. Turn on FIFO by setting the FIFO_En bit to “1” in the CTRL5 register (0x24). After this operation the FIFO buffer is enabled but is not collecting data, output registers are frozen to the last samples set loaded. 3. Activate Stream-to-FIFO mode by setting the FM[2:0] field to “011” in the FIFO control register (0x2E). The interrupt trigger is related to the IA bit in the IG_SRC register and it is generated even if the interrupt signal is not driven to an interrupt pad. Switching modes is performed if both IA and OVRN bits are set high. Stream-to-FIFO mode is sensitive to the trigger level and not to the trigger edge; this means that if Stream-to-FIFO is in FIFO mode and the interrupt condition disappears, the FIFO buffer returns to Stream mode because the IA bit becomes zero. It is recommended to latch the interrupt signal used as the FIFO trigger in order to avoid losing interrupt events. If the selected interrupt is latched, it is necessary to read the register IG_SRC to clear the IA bit; after reading, the IA bit takes 2*ODR to go low. In Stream mode the FIFO buffer continues filling, when the buffer is full, the OVRN bit is set high and the next samples overwrite the oldest. When trigger occurs, two different cases can be observed: 1. If the FIFO buffer is already full (OVRN = “1”), it stops collecting data at the first sample after the trigger. FIFO content is composed of #30 samples collected before the trigger event, the sample that has generated the interrupt event and one sample after trigger. 2. If FIFO is not full yet (initial transient), it continues filling until it is full (OVRN = “1”) and then, if trigger is still present, it stops collecting data.
Figure 25. Stream-to-FIFO mode: interrupt not latched Figure 26. Stream-to-FIFO mode: interrupt latched FIFO buffer is full and stopped.
6.3.6 Bypass-to-Stream mode
mode when the selected interrupt occurs.
- Configure the desired interrupt generator by using register IG_CFG (0x30).
- Turn on FIFO by setting the FIFO_En bit to “1” in the CTRL5 register (0x24). After this
frozen to the last samples set loaded.
- Activate Bypass-to-Stream mode by setting the FM[2:0] field to “100” in the
because the IA bit becomes zero. IG_SRC to clear the IA bit; after reading, the IA bit takes 2*ODR to go low. high and the next samples overwrite the oldest. Figure 27. Bypass-to-Stream mode
6.3.7 Bypass-to-FIFO mode
- Configure the desired interrupt generator by using register IG_CFG (0x30).
- Turn on FIFO by setting the FIFO_En bit to “1” in the CTRL5 register (0x24). After this
frozen to the last samples set loaded.
- Activate Bypass-to-FIFO mode by setting the FM[2:0] field to “111” in the FIFO_CTRL
the interrupt signal is not driven to an interrupt pad. IG_SRC to clear the IA bit; after reading, the IA bit takes 2*ODR to go low.
OVRN bit is reset when the first sample set has been read.
6.4 FIFO threshold
Figure 28. FIFO threshold behavior - FTH[4:0] = 10 that nine unread sample sets remain in FIFO. DRDY/INT2 pin by setting the INT2_FTH bit high in the CTRL3 register.
6.5 Retrieving data from FIFO
to 2Dh) returns the oldest FIFO sample set. Whenever output registers are read, their content is moved to the SPI/I2C output buffer. and the output registers load the current oldest value stored in the FIFO buffer. set is available in the FIFO buffer. 0x28 when register 0x2D is reached. is used (max. rate 400 kHz), the selectable ODR must be lower than 228 Hz. Figure 29. FIFO reading diagram - FTH[4:0] = 10 slot expanded in the diagram.
7 Temperature sensor
8 Revision history
Table 34. Document revision history 18-Jun-2014 1 Initial release.