AN4421 STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

Datasheet sections

  • 1 Hardware and AC/DC considerati ons
  • 1.1 Hardware considerations
  • 1.2 AC/DC characteristics
  • 1.2.1 AC/DC differences
  • 1.2.2 Pull resistor on SDA line
  • 2 Software considerations
  • 2.1 I²C-bus and standard EEPROM memories (M24x xx)
  • 2.2 Differences when accessing a standard EEPROM (M24xxx) or
  • 2.3 Differences when accessing an ISO15693 dynamic tag (M24LRxx) or
  • 3 Revision history

Migrating from M24LR to M24SR series Introduction Both M24LRxx and M24SRxx dynamic tags can be accessed through the I²C-bus. This application note aims at helping to design an application able to interface through the I²C- bus either the M24LRxx (a) or the M24SRxx(b). Some references are also made when accessing the standard M24xxx (EEPROM accessed through the I²C-bus). a. Also accessible through RF (ISO15693 standard) b. Also accessible through RF (ISO14443 standard)

1 Hardware and AC/DC considerations

1.1 Hardware considerations

differences between the two devices are detailed inTable 1.

1.2 AC/DC characteristics

1.2.1 AC/DC differences

moving from M24LRxx to M24SRxx (or reverse move). Table 1. Pinout differences between M24LRxx and M24SRxx devices General Purpose Output functionality. Table 2. AC/DC differences between M24LRxx and M24SRxx devices

1.2.2 Pull resistor on SDA line

external pull up resistor Rbus.

  • High enough so that the current flowing through Rbus and SDA remains lower than the specified Iol value (a few mA)
  • Reasonably low so that the cut-off frequency(a) defined with the SDA line parasitic capacitor Cbus is higher than the maximum SCL clock frequency. Depending on the application parasitic capacitor value Rbus, Cbus can be defined as explained in Figure 1 curves.

Figure 1. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus Figure 2. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus

2 Software considerations

2.1 I²C-bus and standard EEPROM memories (M24xxx)

other than 1010b (to select the memory) is not acknowledged by the memory device. enable address is the same as the value decoded on the Ei inputs. Write (to Slave) operations.

2.2 Differences when accessing a standard EEPROM (M24xxx)

Stop condition, as in the Write sequence example shown in Figure 3. Table 3. Device select byte (first byte)

  1. The most significant bit, b7, is sent first.

Figure 3. Access to a standard EEPROM

  • The standard EEPROM Device Select byte is defined in Table 4.
  • The M24LRxx Device Select byte is defined in Table 5.

Table 4. Standard EEPROM Device Select byte

  1. The most significant bit, b7, is sent first.
  2. E0 bit and E1 bit are compared against the respective values read from external pins E0, E1 of the

Table 5. M24LRxx Device Select byte

  1. The most significant bit, b7, is sent first.
  2. E0 bit and E1 bit are compared against the respective values read from external pins E0, E1 of the
  3. E2 is not connected to any exte rnal pin, see M24LRxx for details.

EEPROM or an M24LRxx dynamic tag.

2.3 Differences when accessing an ISO15693 dynamic tag

different from the M24LRxx sequence.

  1. The I²C-bus Master starts the communication by sending a request, that is a Device

Select byte with the RW bit set to 0 followed by the command field.

  1. Once a valid request is received by the M24SRxx, it prepares its answer.
  2. Then the I²C-bus Master sends a response r equest, that is a Device Select byte with

the RW bit set to 1, followed by the data received from the M24SRxx. I²C-bus Master and the M24SRxx. Figure 4. Command+response sequence between the I²C-bus Master and the

  1. S is the I²C Start condition.
  2. RW is the 8th bit of Device Select.
  3. P is the I²C Stop condition.

3 Revision history

Table 6. Document revision history 17-Mar-2014 1 Initial release.