AN4397 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 19
Technical content
Datasheet sections
- 1 Schematic and bill of material
- 2 System setup
- 3 Layout
- 4 Component selection
- 4.1 MPPT setting
- 4.2 Input capacitance
- 4.3 Capacitance on MPP-REF pin
- 4.3.1 Inductor selection
- 4.3.2 Output voltage ripple
- 4.3.3 UVP and EOC setting
- 5 Board description
- 6 Revision history
performances please refer to the SPV1050 datasheet. best system configuration to make the SPV1050 device working at the most of efficiency. Harvest energy from PV panels supplying 2.6 V ≤ VMP ≤ 9 V and 10 µA ≤ IMP ≤ 20 mA. of charge voltage threshold (VEOC). MP from 150 mV up to 18 V, IMP up to 100 mA, VUVP down to 2.2 V and VEOC up to 5.3 V. The STEVAL-ISV020V1 is shown in Figure 1. Figure 1. STEVAL-ISV020V1 evaluation board
AN4397 Schematic and bill of material
1 Schematic and bill of material
The schematic, bill of material and gerber files can be downloaded from the Design resources tab of the STEVAL-ISV020V1 product folder on www.st.com.
Figure 2. STEVAL-ISV020V1 schematic
Figure 3. STEVAL-ISV020V1 application diagram
Table 1. Bill of material
Table 1. Bill of material (continued)
2 System setup
Figure 4. Supply and load connections a power supply VGEN to determine VOC and a resistor RIN to determine IMP and VMP. emulated by a power supply with a resistor in series.
3 Layout
views) of the STEVAL-ISV020V1. Figure 5. Layout ‐ silkscreen view Figure 6. Layout - top view Figure 7. Layout ‐ bottom view
The same ground plane has to connect the exposed pad and the pins PGND and GND. The capacitor on the STORE pin must be placed as close as possible to the pin. Details on the recommended layout solution are shown in Figure 8 and Figure 9. Figure 8. Ground plane detail Figure 9. Components placement detail
Component selection AN4397
4 Component selection
This section describes the application rules to be followed for properly selecting the components around the SPV1050 device.
4.1 MPPT setting
The “Maximum Power Point” (MPP) is set through the input resistor partitioning R1, R2 and R3. As a preliminary rule, the voltage on the MPP pin (VMPP), which depends on the voltage supplied by the selected source (VIN), must be ≤ VUVP (which is set by the output resistor partitioning R3, R4, R5). So, the following equation: Equation 1 can be rewritten as follows: Equation 2 VOC(MAX) stands for the maximum voltage that the source can supply (open circuit voltage). Further, the MPPRATIO = VMPP_SET / VOC is set by the following equation: Equation 3 For the PV panels the VMP is typically in the range between 70% and 80% of VOC. Finally, the leakage on the input resistor partitioning must be negligible, hence typically it must be: Equation 4
10 M ≤ R1 + R2 + R3 ≤ 20 M
VUVP VOC MAX R2 R3+ VMPP SET VIN x MPP RATIO VOC VIN x R3
4.2 Input capacitance
alternatively the inductance has to be reduced. (e.g. reducing input capacitance) at very low input power. Figure 10. Input stage equivalent circuit Fig ure 11. Effect of C1 on sampled voltage
Component selection AN4397
4.3 Capacitance on MPP-REF pin
It's recommended to use C8 = 10 nF in most of the application cases.
4.3.1 Inductor selection
The SPV1050 device controls the switching of the integrated DC-DC by limiting the peak current flowing through the inductor L1. L1 = 22 µH covers the most typical application range: the lower is the series resistance of the selected inductor, the lower is its DC loss. The current capability of the selected inductor must be ≥ 200 mA.
4.3.2 Output voltage ripple
In case of battery with high series resistance and fast load transient, the capacitor on the STORE pin may momentarily discharge and cause the undesired triggering of the VUVP threshold, implying the battery disconnection. Although the fast transient might be masked by a proper capacitance between UVP and GND pins, if the battery has low peak current capability, the voltage on the STORE pin may further drop down lower than VUVP. Increasing the capacitance on the STORE pin has the drawback of affecting the output time constant and consequently delays the startup time. The same capacitor might be placed in parallel to the battery. The selection of the battery and of the output capacitance on the STORE pin (C9) is strictly related to the following application parameters: The series resistance of the battery (RBATT) The EOC threshold (VEOC) and the UVP threshold (VUVP) The maximum load current (ILOAD(MAX)) The TLOAD(ON), how long the load sink (ILOAD(MAX)) The maximum allowed voltage drop on LDOs outputs (VDROP(MAX)) The maximum current that can be supplied to the load is the sum of the currents that can be supplied by the battery (IBATT(MAX)) and by the C9 (ISTORE): Equation 7 ILOAD(MAX) = IBATT(MAX) + ISTORE The maximum current that the battery can supply without triggering the UVP threshold is: Equation 8 The amount of charge that the C9 can supply is: Equation 9 Q9 = C9 • VDROP(MAX) IBATT MAX VBATT VUVP– RBATT
AN4397 Component selection Considering that I = C • dV/dt, it follows: Equation 10 Thus: Equation 11
4.3.3 UVP and EOC setting
The pins UVP and EOC have to be connected to the STORE pin by the resistor partitioning R4, R5 and R6 to setup the related thresholds by scaling down those voltage values and by comparing them with the internal bandgap voltage reference set at 1.23 V. The design rules to setup R4, R5 and R6 are the following: Equation 12 Equation 13 Further, in order to minimize the leakage due to the output resistor partitioning it has to be typically: Equation 14
10 M ≤ R4 + R5 + R6 ≤ 20 M
IBATT MAX ILOAD MAX CSTORE VDROP MAX TLOAD ON CSTORE TLOAD VDROP MAX VBG VUVP R5 R6+ VBG VEOC
5 Board description
VBATT: connect this pin to the positive of the battery. LDO2: connect this pin to the load to be supplied at 3.3 V. LDO1: connect this pin to the load to be supplied at 1.8 V. BATT-CON: output logic pin for battery connection monitoring. (typically 10 M) to a voltage rail lower than VSTORE. BATT-CHG: output logic pin for battery charging status monitoring. (typically 10 M) to a voltage rail lower than VSTORE. signal from the microcontroller. signal from the microcontroller. Table 2. CN1 connector Table 3. CN2 connector Table 4. CN3 connector
STORE: connect this pin to the tank capacitor CSTORE. to the fixed end of charge voltage connected to the J3. Table 5. CN3 connector Table 6. J1, J2, J3: enable/disable MPPT
- The R2 must be unsoldered.
Table 7. SW1, SW2: enable/disable LDOs
6 Revision history
Table 8. Document revision history 15-May-2014 1 Initial release.