AN4367 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Z4 Core exception overview
  • 1.1 Machine check interrupt (IVOR1)
  • 1.1.1 Machine check registers
  • 2 Machine check handler
  • 2.1 Low level handler
  • 2.1.1 Start phase
  • 2.1.2 Final phase
  • 2.1.3 Modification of the MCSRR0 register
  • 2.2 User handler
  • 3 SPC56EL60xx/SPC56xL70xx exception cases
  • 3.1 Flash 2b ECC error
  • 3.1.1 Cause of the exception
  • 3.1.2 Machine check exception status
  • 3.1.3 User exception handler
  • 3.1.4 Error solving

SPC56EL60xx/SPC56xL70xx device exception handling Introduction This document provides overview of SPC56EL60xx/SPC56xL70xx exception handling with main focus on different kind of exception that the application code can face during the runtime like Flash 2b ECC error, RAM 2b ECC error, MPU protection violation, AIPS access protection violation and others. It starts simple overview of Machine check interrupt highlighting important things from application perspective. To get detailed view and to implement low level machine check interrupt handler it is necessary to use Z4 Core User Manual which describes all the details about the Core exception and interrupts. The following part lists the SPC56EL60xx/SPC56xL70xx exceptions, describes the reason of the exception, how to find it and what possibilities exists to remove the fault. www.st.com

1 Z4 Core exception overview

Core Reference Manual. This reference manual is available online at http://www.st.com. several important fault states of SPC56EL60xx/SPC56xL70xx device.

1.1 Machine check interrupt (IVOR1)

error situation during the CPU-Submodule bus transaction.

1.1.1 Machine check registers

Table 1. Machine check interrupt causes Table 2. Machine check register otherwise MCAR register is not updated.

of the address in case of new asynchronous machine check fault. the address of the instruction that caused the error condition. error, if additional modification of the MCSRR0 register is not explicitly done. the same instruction, that was the cause of the exception. Table 2. Machine check register (continued) Table 3. Machine check causes Instruction fetch, Data store and load. then the MCAR register is not affected.

2 Machine check handler

  • Low level handler
  • User handler

2.1 Low level handler

the code execution to higher level routine and accesses special purpose Core registers. root cause of the exception and fault removal is done. finish the interrupt and return back to the interrupted process. Figure 1. Machine check exception flow

2.1.1 Start phase

possible (precise exception).

handler to analyze the root cause of the exception later. shall follow rules and recommendation described there.

2.1.2 Final phase

MSR register with MCSRR1 content, MCSRR0 modification might be needed.

  1. User handler was able to find the cause of the machine check exception and to fix it in
  2. User was able to find the cause of the exception, but the problem remains and re-

Modification of the MCSRR0 is needed.

2.1.3 Modification of the MCSRR0 register

execution of the faulty instruction and retriggering the machine check exception. instruction pointed by the current MCSRR0 register content, see Figure 2. Figure 2. Modification of MCSRR0 register content

2.2 User handler

  • Low level driver (MCAR, MCSR etc.)
  • Peripherals status registers for further elaboration Based on the results of analysis and corrective actions done, user handler should pass the information about the return type back to the low level driver; indication if MCSRR0 content should be modified or not before mcrfi instruction.

Figure 3. Machine check exception user handler flow

3 SPC56EL60xx/SPC56xL70xx exception cases

while running code on SPC56EL60xx/SPC56xL70xx device. analysis relies on memory area check.

3.1 Flash 2b ECC error

3.1.1 Cause of the exception

access. This leads to machine check exception because of bus_error termination. Figure 4. Flash 2b ECC error Table 4. SPC56EL60xx/SPC56xL70xx exception causes

3.1.2 Machine check exception status

3.1.3 User exception handler

  • Type of access, instruction fetch, data read, data write. Only instruction fetch or data read access are expected in case of 2bECC Flash error
  • Memory range
  • Memory access must be within area belonging to the Flash memory. User has to know which part belongs to the code flash and which part to the data flash memory.

3.1.4 Error solving

takes significant amount of time. stuck in the read of the fault flash address invoking machine checks. Table 5. Flash 2b ECC - machine check exception status area, register modification will be most probably needed. MCSR Type of operation is highlighted here, instruction fetch, data load or data write.

Revision history

Table 6. Document revision history 02-Oct-2013 1 Initial release.