AN4231 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 22
Technical content
Datasheet sections
- 1 Low Power Modes overview
- 1.1 Settings for RAM in STANDBY
- 2 STANDBY Mode transition
- 3 Application code structure
- 3.1 Peripheral used
- 3.2 Code implementation
- 3.2.1 Disable Software Watchdog
- 3.2.2 Clock Generation Module
- 3.2.3 PLL configuration
- 3.2.4 Reset Generation Module function
- 3.2.5 Wakeup Unit configuration
- 3.2.6 Enter in STANDBY mode
- 3.2.7 Locator file configuration
- 3.2.8 RAM wakeup code
- 3.3 Conclusions
Standby mode exit from FLASH to RAM configuration settings for SPC564Bxx and SPC56ECxx device family Introduction The aim of this application note is to describe the correct procedure to manage one of the available low power modes for the SPC564Bxx and SPC56ECxx devices; in particular the enter/exit sequence for the STANDBY mode, which mode allows to reach the maximum power saving state. Due to the multicore nature of the device, several combinations are allowed. In fact it is possible to exit from STANDBY mode enabling Z4 or Z0 core and using backup RAM or FLASH memory. Following the four possible combinations: From Z4 STANDBY exit enabling the Z4 core using Flash memory allocated for Z4 From Z4 STANDBY exit enabling the Z4 core using the backup RAM allocated for Z4 From Z4 STANDBY exit enabling the Z0 core using the Flash memory allocated for Z0 From Z4 STANDBY exit enabling the Z0 core using the backup RAM allocated for Z0 All these combinations are obtained by easily modifyng the next example code. The Reset Generation Module (RGM) contains the functionality to select the alternative boot via the backup RAM on STANDBY mode exit. This document describes about the STANDBY exit from Flash to RAM, using Z4 core because it is the lowest power mode that are enabled with a low latency for wakeup event. The CFLASH and DFLASH are kept in low power mode or in power down at the STANDBY exit, then the PHASE2 and PHASE3 states of the reset state machine do not need to wait for Flash initialization and all the processes are performed faster.
AN4231 Low Power Modes overview
1 Low Power Modes overview
Many automotive applications need to optimize power consumption in order to preserve the battery lifetime in all electronic components and minimize electromagnetic emissions. For this reason, microcontrollers of SPC564Bxx and SPC56ECxx family have the possibility to remain in particular states called “Low Power Modes” when the primary target is to minimize the power consumption. The Low Power Modes in the SPC564Bxx and SPC56ECxx family devices are: HALT mode STOP mode STANDBY mode The HALT mode is intended as a first level low power mode, in which the platform is stopped but system clock remains the same as in running mode. This is a reduced-activity low-power mode during which the clock to the core is disabled. It is configured to switch off analog peripherals like PLL, Flash, main regulator etc. for efficient power management at the cost of higher wakeup latency. The STOP mode is intended as an advanced low power mode, during which the clock of the platform is disabled. It is possible to switch off most of the peripheral oscillator at the cost of higher wakeup latency. The STANDBY mode is a reduced leakage low power mode in which only the power domain 0 (always on) is connected and power supply is cut off from most of the device. Wakeup from this mode takes a relatively long time and content is lost or must be restored from backup. Those modes and their relative power domains are controlled by the Power Control Unit (MC_PCU) which allows switching through four different power domains. When a power domain is disconnected from the supply, its power consumption is reduced to zero and the status information of the same power domain is lost.
Figure 1. MC_ME mode diagram and KEY values to enter in STANDBY mode. exit using an external event and the power domain 0. wake up the microcontroller once a wakeup event occurs.
AN4231 Low Power Modes overview Wakeup unit (WKPU) 8 KB of RAM Real time clock/ Autonomous Periodic Interrupt (RTC_API) CANSampler Slow IRC Fast IRC (can be optionally disabled) System Status and Configuration Module (SSCM) This mode is intended as follows: As an extreme low-power mode with everything powered down apart from the necessary circuitry to allow device wakeup and eventually a RTC/API (real time clock) implementation To be used by software to remain in the lowest power consumption state with no requirement to wake up quickly To exit from this mode, a wakeup event occurs. For this reason, the wake up unit is configured before entering in the STANDBY mode.However, in addition to booting from the default location, the microcontroller is also configured to boot from the backup RAM. In the case of booting from backup RAM, it is also possible to keep the CFLASH and DFLASH disable by writing “01” to the CFLAON and DFLAON field in the ME_DRUN_MC register prior to STANDBY entry. This allows a lower power consumption and a faster wakeup time, due to the fact that it does not need to wait for FLASH initialization (about ~120 us). If there is a STANDBY mode request while any wakeup event is active, the microcontroller does not enter STANDBY mode. In STANDBY mode power domain 1 is disabled. Power domains 2 and 3 are selectively configured to enable additional SRAM as defined in Figure 2. For more information on the Low Power Management refer to the Chapter 11 of the RM.
1.1 Settings for RAM in STANDBY
STANDBY mode offers maximum power saving. The level of power saving is software- controllable via the settings in the PCU_PCONFn registers for power domain 2 onwards. Power domain 0 stays connected to the power supply while power domain 1 is disconnected from the power supply. Power domains 2 and 3 contain the backup RAM extensions and is only powered down during STANDBY mode. Therefore, writing ‘0’ to the respective bits for the other modes do not power down those domains. Depending on PCONF[2-3] configuration, there are four possible combinations for the amount of RAM active in STANDBY mode as shown in the Table 2. The 40 KB option results in a non-contiguous address space.
Figure 2. Power domain organization Table 1. RAM configurations in modes Table 2. PCONF setting for RAM in STANDBY
2 STANDBY Mode transition
example, only power domain 1 is disabled during STANDBY mode. the power domain is disconnected from the power supply (power-down state). Figure 3. MC_PCU Events During Power Sequences (STANDBY mode) is deasserted (power-up state).
3 Application code structure
system memory in order to be available in VLE mode for the core. which is added in order to manage the memory section for the core Z4. Figure 4. Diagram flow of application code implemented
3.1 Peripheral used
3.2 Code implementation
Enter the STANDBY mode from the Mode entry MCTL register. – Configure the MMU for SRAM, BAM, Peripheral Bridge.
3.2.1 Disable Software Watchdog
to the control register of the SWT module. Figure 5. Software Watchdog function
3.2.2 Clock Generation Module
and to jump to the PLL configuration function. Figure 6. CGM init function
3.2.3 PLL configuration
the FXOSC oscillator at 40 MHz. PLL and setting the PLL as system clock. the output of the PLL to be at 120 MHz frequency. Two keys are written in the Mode Entry MCTL register In order to complete the mode entry. measure the PLL frequency divided by four.
Figure 7. PLL configuration function
3.2.4 Reset Generation Module function
BOOT_FROM_BKP_RAM is set and if it is boot from FLASH or from backup RAM. When using the Z4 from RAM in STANDBY mode it needs to ensure that VLE code is used. By default, the Z0 core is the core that is on STANDBY exit. Figure 8. RGM init function
3.2.5 Wakeup Unit configuration
interrupt messaging from the wakeup/interrupt pads to the interrupt controller.
Figure 9. WKUP init function
3.2.6 Enter in STANDBY mode
This function allows entering in STANDBY mode in order to complete the mode transition. Figure 10. Standby mode entry function The STANDBY_MODE hex value for the STANDBY is “0x0000000D“.
3.2.7 Locator file configuration
There are also some variables used to copy code from FLASH to RAM when booting.
Figure 11. Locator file and memory section organization Stack_ram is the RAM reserved for stack (4 KB).
3.2.8 RAM wakeup code
the stack pointer r1, sdata base r13 and sdata2 base r2.
Moreover it is necessary to disable the Software Watchdog and to jump to the code in RAM, to be executed. All this code is inserted in a section that is copied in the RAM after boot. RAM Wakeup code function .section ".ROM_code_to_be_copied", "vax" .vle .globl z4_ram_start_code .align 4 z4_ram_start_code: # Enable SPE in MSR mfMSR r6 e_or2is r6, 0x0200 mtMSR r6 #TLB4 = pbridgeA e_lis r3, 0x1004 mtmas0 r3 e_lis r3, 0xC000 e_or2i r3, 0x0800 mtmas1 r3 e_lis r3, 0xC000 e_or2i r3, 0x000A mtmas2 r3 e_lis r3, 0xC000 e_or2i r3, 0x003F mtmas3 r3 tlbwe #TLB6 = Peripheral Bridge and BAM #0x6 0xC0000600 0xFFC00028 0xFFC0003F e_lis r3, 0x1006 mtmas0 r3
e_lis r3, 0xC000 e_or2i r3, 0x0600 mtmas1 r3 e_lis r3, 0xFFC0 e_or2i r3, 0x0028 mtmas2 r3 e_lis r3, 0xFFC0 e_or2i r3, 0x003F mtmas3 r3 tlbwe # re-Configure MMU SRAM - extend from 4K to 256K. e_lis r3, 0x1000 mtmas0 r3 e_lis r3, 0xc000 e_or2i r3, 0x0400 # 256 KB mtmas1 r3 e_lis r3, 0x4000 e_or2i r3, 0x0028 mtmas2 r3 e_lis r3, 0x4000 e_or2i r3, 0x003f mtmas3 r3 tlbwe #disable_watchdog e_lisr6, 65524 e_add16ir6, r6, -32752 e_lir7, 50464 se_stwr7, 0(r6) ##SWT.SR.R = 0x0000d928; /* key */ e_lisr7, 65524 e_add16ir7, r7, -32752
e_lir6, 55592 se_stwr6, 0(r7) ##SWT.CR.R = 0xC000010A; /* disable WEN */ e_lisr6, 65524 e_add16ir6, r6, -32768 e_lisr7, 0xc000 e_add16ir7, r7, 0x010A se_stwr7, 0(r6) e_lis r1, __SP_INIT@h # Initialize stack pointer r1 to e_or2i r1, __SP_INIT@l # value in linker command file. e_lis r13, _SDA_BASE_@h # Initialize r13 to sdata base e_or2i r13, _SDA_BASE_@l # (provided by linker). e_lis r2, _SDA2_BASE_@h # Initialize r2 to sdata2 base e_or2i r2, _SDA2_BASE_@l # (provided by linker). e_stwu r0,-64(r1) # Terminate stack. #TLB2 = 1M Internal flash e_lis r3, 0x1002 mtmas0 r3 e_lis r3, 0xC000 e_or2i r3, 0x0500 mtmas1 r3 e_lis r3, 0x0000 e_or2i r3, 0x0020 mtmas2 r3 e_lis r3, 0x0000 e_or2i r3, 0x003F mtmas3 r3 tlbwe e_lis r3, return_from_standby_code_in_FLASH@h e_or2i r3, return_from_standby_code_in_FLASH@l mtlr r3 here: se_blr # branch to code in flash
3.3 Conclusions
STANDBY mode allows maximizing power saving. During the STANDBY mode, all memories that are not powered down in this mode, enter in a power saving state. This increases the power saving and the data in the memories are retained. This application note has described how to manage the STANDBY exit from FLASH to RAM, using the Z4 core of the device. This is the lowest power consumption mode and also the fastest for wakeup process because it does not need wait for FLASH initialization. It is possible (see Figure 8), modifying the RGM init function, to switch from Flash to RAM or from FLASH to FLASH and to decide which core is used. In case of usage of Z0 core at STANDBY exit, no MMU configuration is necessary.
Reference documents AN4231 Appendix A Reference documents A.1 Reference documents SPC564Bxx, SPC56ECxx 32-bit MCU family built on the embedded Power Architecture (Reference manual, RM0070, Doc ID 18196).
Revision history
Table 3. Revision history 06-May-2013 1 Initial release. 17-Sep-2013 2 Updated Disclaimer.