AN4192 STMICROELECTRONICS | Alldatasheet
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Technical content
Datasheet sections
- 1 Synchronous buck converter: a brief introduction
- 2 High-side MOSFET selection
- 2.0.1 Q G,SW and fSW impact on the efficiency
- 2.0.2 Q G,SW impact on the HS switching behavior
- 2.1 R DS(on) and conduction losses minimization
- 2.2 Gate drive network optimization
- 3 Low-side FET selection
- 3.1 RDS(on) and conduction losses minimization
- 3.2 C GD (Miller capacitance)
- 3.3 LS body-drain diode Q rr (reverse recovery charge)
- 3.4 R G and LS gate-source bouncing
- 3.5 RC snubber network settings
- 3.6 Phase node spike - V
- 4 Conclusion
- 5 Bibliography
- 6 Revision history
November 2012 Doc ID 023820 Rev 1 1/47 AN4192 Application note Power MOSFETs: best choice guide for VRM applications By Filadelfo Fusillo, Filippo Scrimizzi Introduction In the latest generation of CPUs for modern desktop and notebook platforms, the VRMs (voltage regulator modules) must have some specific features in order to reach high performance in terms of power management. This target can be reached by analyzing all the design parameters and their optimization, with a particular focus on the MOSFET electrical characteristics and configuration. The power stage must deliver very low core voltage (typically 1.2 V - 1.3 V) to the CPU at high current levels (up to 160 A), with ever-increasing switching frequencies (up to 500 - 700 kHz). In order to match these requirements, the basic topology used in the VRMs is the “multiphase synchronous buck converter”, which typically steps down to 12 V input voltage, providing the desired core voltage.
1 Synchronous buck converter: a brief introduction
and C are the output filters. Figure 1. Synchronous buck converter simplified schematic strong reduction of the ON-state losses is guaranteed. FETs are in the OFF-state (deadtime).
Figure 2. HS/LS gate-source voltages re-flows through the LS body diode (deadtime) and then another switching cycle begins.
- High switching frequencies working capability
- Ever-increasing output current to be delivered to the load
- Input and output current ripple minimized. To match these requirements, the “multiphase” approach (Figure 3) is universally used, developed by interleaving more single-phase SBCs, connected together in the output capacitor pins. In this way, we obtain some advantages: a) Each phase can manage up to 25 - 30 A (according to the layout and cooling down characteristics): so, it is possible to handle high currents, with improved efficiency. Moreover, the device reliability increases. b) The total load current is given by adding all the phase currents: this causes a strong reduction of the output current ripple. c) Input and output filter component size and dimension can be minimized; the converter working capability at high switching frequencies increases. dIL AM16446V1
Figure 3. Multiphase synchronous buck converter schematic HS or LS FETs in order to minimize some converter power losses.
2 High-side MOSFET selection
- Qg (total gate charge): it impacts the HS switching speed (at turn-on and turn-off) and
frequency oscillations on the phase node at HS turn-on).
- RG,HS (external gate resistance) and gate drive network settings: the right RG,HS value
switching behavior with limited consequences on the efficiency. Figure 4. Gate charge waveform = t0, the gate-source capacitance (Cgs) is charged and the drain current starts to increase. MOSFET is in the ohmic zone, with a constant RDS(on).
SW, the more relevant the switching losses.
- The bigger the Q G,SW (and the slower the HS switching speed), the higher the PSW.
2.0.1 Q G,SW and fSW impact on the efficiency
DSon, BVDSS, etc.) are reported. Figure 5. 2-phase synchronous buck converter schematic
the best efficiency in the overall current range, due to the switching losses reduction. solution in high frequency VRM applications.
2.0.2 Q G,SW impact on the HS switching behavior
Figure 8. MOSFET equivalent circuit during Miller plateau 2.2 Ω, RG,LS = 2.2 Ω), whereas no RC snubber network is used.
increase MOSFET reliability).
2.1 R DS(on) and conduction losses minimization
(0.1% - 0.2%), this term is not the most important in converter performance enhancement. lower RDSon high-side FET is used. Figure 11. Single-phase synchronous buck converter schematic
1.25 V, IOUT,MAX = 20 A, fSW = 270 kHz, 1 x HS, 1 x LS) is shown, where two different high-
MOSFET electrical parameters are reported in Table 2. Figure 12. Efficiency comparison @ V out = 1.25 V efficiency results, due to its lower RDS(on) (+0.8% at full load). conduction and switching losses.
2.2 Gate drive network optimization
HS switching behavior optimization and phase node ringing reduction (high RG,EXT). snubber network settings): however, it depends also on the HS turn-on speed. Table 2. MOSFET electrical parameters
Figure 20. Efficiency comparison @ V out = 1.26 V number of devices (one resistor + one Schottky diode) and the cost increase.
Low-side FET selection AN4192 20/47 Doc ID 023820 Rev 1
3 Low-side FET selection
The low-side FET performance can be enhanced by properly choosing the following MOSFET electrical parameters: 1. RDS(on) (ON-state drain-source resistance): as the LS FET is in the ON-state for a longer time, the conduction losses, strictly related to the RDS(on) value, are the most important power dissipation contribution. Based on the converter layout and the output current requirements, one or more paralleled LS FETs can be used. 2. C GD (Miller capacitance): it affects the LS switching behavior, in terms of phase node spike and dVphase/dt. On the other hand, too high CGD values increase the LS “switching charge” (QG,SW): in high frequency applications or when more LS FETs are paralleled to reduce the RDSon, this may increase the switching and gate drive losses, even if the LS switches at nearly ZVS (due to its body diode conduction). 3. Q RR (LS body-drain diode reverse recovery charge): during the deadtime (when the HS and LS are in the HOLD state), the load current flows through the body-drain diode (forward biased). When the HS turns on, the excess charge stored in the LS body diode RR) must be removed before the phase node turns high. 4. RG (external and intrinsic gate resistance): when no additional smoothing effects are present (i.e. snubber network), the higher the RG, the lower the Vphase,max. The drawback is the LS G-S spurious ringing that may induce the LS spurious turn-on again. Furthermore, the LS FET performance is also influenced by the RC snubber network setting, connected between LS drain and source, which helps to smooth the phase node noise. Another important aspect is the spurious LS gate-source bouncing, induced by the fast rising edge of the phase node through the Miller capacitance; it is analyzed with a particular focus on the different solutions to reduce these parasitic oscillations. Finally, the converter output voltage (and the converter duty cycle) affects the phase node noise behavior: the higher the V OUT, the lower the phase node overshoot, during the HS turn-on.
3.1 R DS(on) and conduction losses minimization
The LS conduction losses are given by: Equation 4 As the converter duty cycle (for typical VRM applications) is very low (0.1 - 0.2%), the LS FET is in the ON-state for a longer time: the conduction losses are the most important power dissipation term. The R DS(on) minimization is crucial for the optimization of the LS performance. Bigger die sizes are preferred, even though the device cost is a constraint. If the output current to be delivered to the load is high, more LS can be used in parallel. To better understand the impact of the R DS(on) on the converter efficiency, two LS FETs are compared in a 3-phase buck converter (VIN = 12 V, VOUT = 1.25 V, fSW = 300 kHz, 2 x HS, 2 x LS, IOUT = 75 A; see Figure 21). External gate resistances are connected to HS (2.2 Ω) and LS (2.2 Ω) FETs. An RC snubber network (RSNUB = 2.2 Ω, CSNUB = 4.7 nF) is used to smooth the phase node. PCOND,LS RDS on() TI D 2 1D–()⋅⋅=
In the following table the main electrical parameters of the two tested LS FETs are reported. The high-side FET used is called “HS”. LS1, due to its slightly lower Qg and then switching/gate drive losses, has higher efficiency. Figure 21. Efficiency vs. I out @ Vout = 1.25 V
3.2 C GD (Miller capacitance)
The Miller capacitance (Cgd) plays a crucial role in the LS switching behavior improvement. diode (deadtime) (Figure 22, green trace, I2). Table 3. Main electrical parameters
Figure 24. Low-C RSS LS FET phase node waveform @ 80 A
Figure 25. High-C RSS LS FET phase node waveform @ 80 A vs. 30.7 V of the low-CRSS FET). a) Low-side FET intrinsic slow-down. the reverse recovery process stresses.
3.3 LS body-drain diode Q rr (reverse recovery charge)
Figure 31. LS with monolithic Schottky diode waveforms @ 20 A HS (2.2 Ω) and LS (2.2 Ω) FETs. No snubber network is mounted on the board. reverse recovery losses, the solution with LS+Sch. has higher efficiency (+1.5% at full load).
3.4 R G and LS gate-source bouncing
(major losses contribution), particularly at high fSW. depends also on the HS switching speed). Figure 34. LS FET during HS turn-on
Figure 39. 2-phase synchronous buck converter waveforms of the two LS FETs tested at full load conditions (IOUT = 44 A) are compared.
3.5 RC snubber network settings
components surrounding the LS FET. Figure 46. LS FET with RC snubber network
Figure 47. Phase node waveform and f RING evaluation maximum phase node spike is 33.6 V.
achieved (30.1 V). In Figure 50, the waveforms at full load conditions are reported. effect (“Configuration 3”). The gate resistors are unmodified (Figure 51). Figure 50. R G,HS(EXT) = 2.2 Ω - RG,HS(EXT) = 1.8 Ω/ original snubber waveforms @ 20 A
3.6 Phase node spike - V CORE relationship
CSNUB = 4.7 nF) is used to smooth the phase node. Figure 53. 3-phase synchronous buck converter voltage, from 2.5 V to 3.3 V. In Figure 54 and 55, the relevant waveforms are reported.
Figure 56. Phase node spike - V OUT chart
4 Conclusion
5 Bibliography
- Section 1: Synchronous buck converter: a brief introduction a) C.S.Mitter, device considerations for high current, low voltage synchronous buck converter. b) Fairchild Semiconductor AN6005, Synchronous buck converter power losses calculation. c) STMicroelectronics AN2170, MOSFET device effects on phase node ringing in VRM power converters. 2. Section 2: High-side MOSFET selection a) K.S.Oh (Fairchild Semiconductor AN9010), MOSFET Basics. simulation of LV MOSFETs in synchronous rectifier buck-converter applications. c) Fairchild Semiconductor AN6005, Synchronous buck converter power losses calculation. d) T.Wu, Cdv/dt induced turn-on in synchronous buck regulators. 3. Section 3: Low-side FET selection a) STMicroelectronics AN2170, MOSFET device effects on phase node ringing in VRM power converters. simulation of LV MOSFETs in synchronous rectifier buck-converter applications. c) STMicroelectronics AN2239, Maximizing synchronous buck converter efficiency with standard STripFETsTM with integrated Schottky diodes. d) S.Mappus, dV/dt immunity improved in synchronous buck converter. e) F .Wu,H.Gao,Li Sun,K.Zhao, Suppression of gate oscillation of Power MOSFET with bridge topology. characterization of LV Power MOSFETs in synchronous-rectifier buck-converter applications. g) Q.Zhao,G.Stojcic, Characterization of CdV/dt induced power losses in synchronous buck DC-DC converters. h) O.Djekic,M.Brkovic,A.Roy, High frequency synchronous buck converter for LV applications. i) S.Havanur (A&O Semiconductor AN100-1), Snubber design for noise reduction in switching circuits.
6 Revision history
Table 5. Document revision history 13-Nov-2012 1 Initial release.