AN4150

AN4150 STMICROELECTRONICS | Alldatasheet

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Technical content

Datasheet sections

• 1 Synchronous buck converter description
• 1.1 T opology and theory of operation
• 1.2 Low-side switching transients analysis
• 2 Synchronous buck converter testing demonstration board
• 2.1 Power MOSFET selection for comparative tests
• 3 Bench tests and simulation results overview
• 4 Conclusion
• 5 References
• 6 Revision history

October 2012 Doc ID 023526 Rev 1 1/20 AN4150 Application note Power MOSFET technology gate current needs in a synchronous buck converter Introduction High frequency converters and applications require the best driver-MOSFET trade-off in terms of dynamic parameters to optimize the turn-on and turn-off transients. Power MOSFET technology also plays an important role in minimizing dynamic losses and improving system efficiency. In this document, the full characterization of Power MOSFET gate current is realized by bench tests and OrCAD ® simulation results, focusing on the impact of Power MOSFET technology on gate current behavior. Ever increasing system switching frequency pushes designers and converter engineers to optimize semiconductor technology, improving device switching behavior and system efficiency. In fact, the higher the switching frequency, the larger the switching and dynamic losses; in these conditions, the best trade-off between the driver and Power MOSFET is mandatory to enhance the overall converter performance. Power MOSFET gate current behavior during switching transients plays an important role in establishing a good trade-off between Power MOSFET and driver performance. In this document, Power MOSFET gate current characterization is performed through bench tests and simulations (by Cadence ® OrCAD Capture) on a single-phase synchronous buck converter, allowing a full understanding of the impact of the silicon technology on device gate current.

1 Synchronous buck converter description

1.1 Topology and theory of operation

signal on the low-side drain (so-called phase node). regulated when line or load changes occur. and protection (overcurrent, overvoltage, undervoltage, etc.…). signals are low and the body-drain diode is forward-biased, allowing the load current flow. Figure 1. Single phase synchronous buck converter topology

power losses, especially when the converter switching frequency rises up. reduction, improving the converter performance.

1.2 Low-side switching transients analysis

the load current flows from source to drain. Figure 2. HS/LS waveforms during LS turn-off

Synchronous buck converter description AN4150 6/20 Doc ID 023526 Rev 1 In these conditions, it is interesting to analyze the switching transients. In Figure 2, the HS and LS waveforms during LS turn-off are reported. The top half of the image shows HS VGS (purple trace) and ID (grey trace), while the bottom half shows LS VGS (red trace), VDS (blue trace), IG (light blue trace) and ID (light green trace). The main LS turn-on steps are analyzed in detail, as follows: 1. Low-side FET is in an ON state (in this case, V GG = 5 V), with load current flowing from source to drain (green trace). At the end of (1), the driver begins to turn off the FET. 2. V GS goes down from VGG to Vth and the gate current becomes negative and starts to remove the charge stored in the device intrinsic capacitances. At the end of (2), the gate-source voltage becomes equal to the threshold voltage (VGS = Vth): so, the gate current is dropped to low values (intrinsic caps are discharged) and the load current diverts from the Power MOSFET channel to the body-drain diode. 3. During deadtime, the LS FET is in an OFF state (V GS = 0), VDS becomes negative (VDS = -VF, D I O D E) and the load current flows through the body-drain diode. As a consequence, minority excess charge in both diode regions is created. 4. The LS current decreases linearly, while the HS current increases linearly in direct proportion to the fall of the LS FET current. To completely turn off the LS device, the excess stored charge in its body diode must be removed: so, the reverse recovery process generates an extra-current (I RR), which adds to the HS current. The maximum HS current peak is, therefore, given by: I D,HS = ILOAD + IRR The spurious bouncing on the LS gate signal is caused by the voltage drop across package parasitic inductances (especially, source inductance), related to negative dl/dt (the current is falling to zero). Obviously, the bigger the parasitic inductance (package, wire bonding and layout) the higher the bouncing amplitude. At the same time, the low- side V DS is fixed by the parasitic inductance and dlD,LS/dt. During device turn-off, the gate current is negative, because of the Power MOSFET intrinsic capacitances discharge process. The current is sunk by the driver, with a speed linked to the gate voltage level and overall gate resistance (R G,TOT = RG,INT + RDR,SINK). It is important to underline that, at LS turn-off, the driver, external and intrinsic FET gate resistance should be as low as possible in order to minimize the device shoot-through risks, caused by high dv/dt across drain-source, coupled to the gate signals through Miller capacitance in Figure 3.

2 Synchronous buck converter testing demonstration

1.25 V as output; the converter switching frequency is 300 kHz, fixed by an internal

oscillator, while the maximum output current is 20 A. conduction phenomenon during device turn-off. Cadence OrCAD Capture model of the converter (including driver and Power MOSFETs). packages and high switching frequency. Figure 5. Testing demonstration board schematic

highly linear even at very high current levels.

2.1 Power MOSFET selection for comparative tests

Figure 7 gives the cross sections of the two above mentioned devices. Figure 6. Rogowski coil package for I gate measurement Table 1. Power MOSFET electrical parameters

AN4150 Synchronous buck converter testing demonstration board Doc ID 023526 Rev 1 11/20 For a planar structure, L is the gate electrode width while the pitch is the cell-to-cell distance. In a trench device, L* is the trench width and h is the trench depth. Qg/A (gate charge per area) links the Power MOSFET dynamic performance to the device geometry, providing a good tool for a technology comparison: Equation 3 Equation 4 Equation 3 is valid for a planar device, while 4 is valid for trench. For modern silicon technology, the following considerations are valid: Equation 5 L*<< 2 h Equation 6 L < 2 h So, merging Equation 3, 4, 5 and 6 and considering that (pitch)A > (pitch)B: Equation 7 Equation 8 In other words, the intrinsic capacitive contribution of planar technology is lower than that of trench. This is of basic importance when the system/application requires switching performance improvement. The specific capacitance difference between devices A and B shown in Figure 8 is reflected into dissimilar gate charge curves: all the components of the gate charge are much larger for dev.B (red curve). Qg pitch() A Qg pitch() A Qg planar Qg trench Cxx planar Cxx trench

Figure 9. Gate charge comparison

3 Bench tests and simulation results overview

–t r: low-side VGS rise time, measured from 10% to 90% of VGS. G (total gate charge) to fully turn on the FET. Figure 10. Device A gate waveforms Figure 11. Device B gate waveforms

on and off and maintenance current. Figure 12. Device A vs. device B (experimental results) Table 2. Percentage variation (experimental results)

time. Furthermore, the trend is confirmed also for the other switching values. Figure 17. Device A vs. device B (simulation results) Table 3. Percentage variation (simulation results)

4 Conclusion

Starting from a single-phase synchronous buck converter topology, the impact of silicon technology on low-side Power MOSFET gate current has been thoroughly analyzed, by bench tests and Cadence OrCAD Capture simulations. Trench technologies, which are preferable in high efficiency DC-DC converters due to their very competitive figure of merit (FOM = R DS(on) * QG) values, have higher specific capacitance values (Cxx/A) compared to planar ones; this affects the overall device switching performance. This also means different gate current behavior, with bigger maximum and minimum gate current peaks and longer rise/fall times. These different device characteristics should be monitored particularly when application features (switching frequency, number of paralleled devices, etc.…) are more critical for switching behavior, making driver-MOSFET matching optimization mandatory. Two examples can be given to enforce the previous statements. When more FETs are paralleled, to minimize the overall R DS(on) and the conduction losses, the driver must charge and discharge a bigger equivalent capacitance to switch on and off the devices. So, to minimize the gate drive losses, the driver must have special features, in terms of sink/source current and resistance, particularly when driving trench Power MOSFETs. Similarly, in hard-switching applications, where larger losses occur during switching transients, proper driver choice is needed when higher (Cxx/A) Power MOSFETs must be turned on and off, improving gate current source and sink and reducing the switching losses.

5 References

• Power Electronics Handbook, M. H. Rashid, 2001
• Fundamentals of Power Electronics, R. W. Erickson, 2000

6 Revision history

Table 4. Document revision history 12-Oct-2012 1 Initial release.