AN4149

AN4149 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 CCM PFC using FOT control
• 2 Designing a CCM FOT-controlled PFC
• 2.1 Input specification
• 2.2 Operating conditions
• 2.3 Power section design
• 2.3.1 Bridge rectifier
• 2.3.2 Input capacitor
• 2.3.3 Output capacitor
• 2.3.4 Boost inductor
• 2.3.5 Power MOSFET selection and power dissipation calculation
• 2.3.6 Boost diode selection
• 3 L4984D biasing circuitry
• 3.1 Feedback and OVP
• 3.2 Current sense resistor
• 3.3 Mult divider and VFF
• 3.4 Gate driver (GD) and VCC pins
• 4 FOT PFC boost control loop
• 5 Layout hints
• 6 Design example using the L4984D-CCM PFC excel spreadsheet
• 7 References
• 8 Revision history

CCM PFC using FOT control AN4149

1 CCM PFC using FOT control

Fixed-frequency PWM is not the only alternative when CCM operation is desired. An additional approach that couples the simplicity and affordability of TM operation with the high-current capability of CCM operation can be a solution to the problem. Fixed-frequency PWM modulates both switch ON and OFF times (their sum is constant by definition), and a given converter operates in either CCM or DCM depending on the input voltage and the loading conditions. Exactly the same result can be achieved with FOT approach: a conventional "peak" current mode control, where the ON-time T ON of the external power switch is determined by the peak inductor current reaching the programmed value and the OFF-time T OFF is determined by a special Fixed-off-time (FOT) modulator in such a way that the resulting switching period is constant as long as the boost converter is operated in CCM (i.e. the current in the boost inductor remains greater than zero in a switching cycle). In Figure 3 a block diagram of an FOT-controlled CCM PFC pre-regulator is shown. An error amplifier (VA) compares a portion of the boosted output voltage V out with a reference VREF and generates an error signal VC proportional to their difference, a DC voltage by hypothesis, which is fed into an input of the multiplier block and multiplied by a portion of the rectified input voltage V MULT. The multiplier output (VCSREF) is a rectified sine wave whose amplitude is proportional to that of VMULT and to VC, and is used as a reference for PWM modulation. The multiplier output is fed into the inverting input of a PWM comparator that, on the non-inverting input, receives the voltage VCS from the sense resistor Rsense, proportional to the current flowing through the switch M (typically a MOSFET) and the inductor L during the ON-time of M. When the two voltages are equal, the comparator resets the PWM latch and M is turned off. As a result, the multiplier output determines the peak current through the switch and the inductor, and as, it is a rectified sinusoid, the inductor peak current is also enveloped by a rectified sinusoid. When VCSREF and VCS are equal the PWM latch output Q going high activates the timer that, after a predetermined time in which T OFF has elapsed, sets the PWM latch, therefore turning the switch on and starting another switching cycle. If TOFF is such that the inductor current does not fall to zero, the system operates in CCM. For the CCM PFC controller, please refer to Figure 4. To understand how TOFF needs to be modulated to achieve a fixed switching frequency independent of the instantaneous line voltage and the load, it is useful to consider the V·s balance equation for the boost inductor under the assumption of CCM operation: Equation 1 where Vpk is the peak line voltage, V out is the regulated output voltage, and θ is the instantaneous phase angle of the line voltage. Solving for TON we get: Equation 2 () θ−=θ sinVpkVoutTsinVpkT OFFON OFFON TsinVpk VoutT   −θ= 1

Figure 3. Block diagram of an FOT-controlled PFC preregulator

characteristics" section of the L4984D datasheet. current tends to become discontinuous starting from the region around the zero-crossings. Figure 6. Boundary between DCM and CCM

AN4149 CCM PFC using FOT control inductor current envelope. The brown waveform is relevant to V in=190 Vac, which is the condition where CCM operation no longer occurs at zero-crossings (this voltage value, for a given power level, depends on the inductance value of the boost inductor); a certain degree of distortion is already visible. The waveform relevant to V in = 264 Vac shows the highest degree of distortion and the largest portion of the line cycle where the boost inductor operates in discontinuous mode (DCM). However, its harmonic content, shown in Figure 9 and 10, is still so low that is not an issue for EMC compliance. Almost all the distortion is concentrated in the third harmonic, whose amplitude is 17% of the fundamental one, while the THD is 17.7%. Figure 11. Line-modulated, FOT controlled boost PFC: input current harmonic

contents

The compliance with conducted EMI emission regulations is also facilitated by the voltage ripple appearing across the output capacitor C O , at twice the line frequency fL, which has peak amplitude ΔVout proportional to the output current IOUT. As a consequence, fsw is not constant but is modulated at 2fL, spreading the spectrum of the electrical noise injected back into the power line. The relative frequency change due to the output voltage ripple is: Equation 11 where ΔVout can be found with the following expression: Equation 12 AM13310v1 Vin = 264Vac THD = 17.7% Harmonic order (n) % Harmonic amplitude (normalized to fundamental) Vin = 264Vac THD = 17.7% Harmonic order (n) % Harmonic amplitude (normalized to fundamental) Vout Vout Vout Vout f f sw sw Δ Coutf IoutVout Lπ

Designing a CCM FOT-controlled PFC AN4149

2 Designing a CCM FOT-controlled PFC

2.1 Input specification

The following is a possible design procedure for a CCM FOT-controlled PFC using the L4984D. This first part is a detailed specification of the operating conditions of the circuit that is needed for the calculations of the design steps in the following sections. In this example a 350 W wide-input range mains PFC circuit has been considered. Some design criteria are also given. Mains voltage range (V acrms) : Equation 13 Minimum mains frequency: Equation 14 Rated output power (W): Equation 15 Typically the output for a boost PFC output voltage is 400 Vdc as it has to be higher than the maximum rectified input voltage: Equation 16 In cases where the maximum AC input voltage VACmax is higher than 265 V, as typical in ballast applications, the output voltage must be set higher accordingly. As a rule of thumb the output voltage must be set 6 or 7% higher than the maximum input voltage peak. Regulated DC output voltage (V dc): Equation 17 The target efficiency and PF are set for the following calculations based on the operating condition of the PFC, here at minimum input voltage and maximum load. An efficiency of 92%, at minimum input voltage and maximum load, could be a starting point for a typical PFC. Expected efficiency (%): Equation 18 VV AC 90mi n = VV AC 265max = Hzf l 47= WPout 350= max2 ACV⋅ VVout 400= out in P 92%Pη ==

AN4149 Designing a CCM FOT-controlled PFC Expected power factor: Equation 19 Because of the narrow loop voltage bandwidth of the E/A to reject the ripple at twice the line frequency on the E/A output, the PFC output may experience overvoltage at startup or during load transients. In order to protect the controller from excessive output voltage that can overstress the output components and the load, in the L4984D a pin (PFC_OK, pin #6) has been dedicated to monitor the output voltage with a separate resistor divider. The divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value (V OVP) larger than the maximum Vout that can be expected, also including worst-case load/line transients. Maximum output voltage (Vdc): Equation 20 The output voltage has a ripple Vout at twice the line frequency (2fL), and whose amplitude is proportional to the load and depends on the impedance of the output capacitor. The ripple amplitude determines the AC current flowing into the output capacitor and the ESR. The value of the maximum output voltage ripple accepted should be below a certain level to keep the output voltage far from the V OVP limit during normal operating conditions, to increase hold-up time, and to reduce the AC losses on the output capacitor. The peak-to- peak voltage ripple V out is usually selected in the range between 2-8% of the output voltage. Here a ratio of 5% is chosen for the output voltage ripple, that is 20 V. Maximum output low frequency ripple (peak-to-peak): Equation 21 The desired ripple on the output voltage is not the only parameter used to select the bulk capacitor. The hold-up time, if requested, should also be taken into account. The hold-up time is defined as the duration of time that a power supply's output will remain above a minimum level in case of mains dips. The hold-up time (t Hold) is measured from the time when the line voltage disappears to the time when the output voltage reaches the required minimum voltage value (Voutmin). A hold- up time of 10-20 ms is often required for today’s offline power supplies. Values of 300 V and 15 ms for the minimum output voltage after line drop and hold-up time, respectively, are chosen here: Minimum output voltage after line drop (V dc): Equation 22 Hold-up time (ms): Equation 23 99.0=PF VVOVP 430= VVout 20=Δ VVout 300min = mst Hold 15=

Designing a CCM FOT-controlled PFC AN4149 The design will be done on the basis of a maximum admitted ripple factor Kr , that is the ratio of the maximum peak-to-peak current ripple amplitude to the inductor peak current, at minimum line voltage and rated load. In the continuous conduction mode converters, the acceptable current ripple factor is typically fixed in a range between 20% and 35%. Low values for the K r keep the peak-to-peak ripple current and the input current distortion low, but lead to larger inductor physical size. Choosing higher values for K r , the inductor size can be smaller, but the input current distortion is increased. For this design, the maximum specified current ripple factor is chosen equal to 27%, as a trade-off between the inductor size and the input current distortion. Ripple factor: Equation 24 In order to properly select the power components of the PFC and size the heat sinks, the maximum operating ambient temperature around the PFC circuitry must be known. Please note that this is not the maximum external operating temperature of the entire equipment, but it is the local temperature at which the PFC components are working. The power dissipation leading to a temperature rise combined with the ambient temperature must not result in any temperature exceeding the operating temperature rating of the components. Maximum ambient temperature ( °C): Equation 25

2.2 Operating conditions

The first step is to define the main parameters of the circuit, using the specifications given in Section 2.1. Rated DC output current: Equation 26 Maximum input power: Equation 27 27.0=rK CTambx °= 50 out out out V PI = A V WI out 875.0 400 350 == η out in PP = WWPin 4.38010092 350 =⋅=

AN4149 Designing a CCM FOT-controlled PFC The maximum value of the RMS current circulating in the boost cell at the minimum line voltage of the selected range is equal to: Maximum RMS input current: Equation 28 In order to describe the energy and relevant equations concerning a boost PFC, the ratios of the voltage inputs of the boost converter to the regulated output voltage are defined. In particular k min and kmax refer to the ratio of the minimum and the maximum input voltage to the output voltage, respectively. Equation 29 Combining equation 28 and equation 29 the maximum line peak current can be found. Maximum line peak current: Equation 30 Maximum inductor peak current: Equation 31 Inductor peak-to-peak ripple current : Equation 32 In order to calculate the losses of the switches, the RMS current flowing through the MOSFET and through the boost output diode are found. Maximum RMS switch current: PFVAC PI in in mi n A Vac WI in 27.4 99.090 4.380 = outV VACk min min 2= outV VACk max max 2= 32.0 400 902max == V Vack 94.0 400 2652max == V Vack out in PK Vk PI mi n max 2 A V WI PK 98.5 40032.0 4.3802 max =  +⋅ min max r AC in PK K PFV PIL A V WILPK 85.6 27.01 99.090 4.3802 max =  +⋅ maxmax PKrPK ILKIL ⋅=Δ AAIL PK 85.185.627.0max =⋅=Δ

Designing a CCM FOT-controlled PFC AN4149 Equation 33 Maximum RMS diode current: Equation 34 It is worth reminding that the accuracy of the equations developed here is quite good at low line voltage and worsens at high line and as the power throughput is reduced. As the current stresses of the switches are calculated at maximum load and minimum line voltage, the previous expressions are acceptable for design purposes.

2.3 Power section design

2.3.1 Bridge rectifier

The input rectifier bridge can use standard slow recovery, low-cost devices. Typically a 600 V device is selected in order to have good margin against mains surges. An NTC resistor limiting the current at turn-on is required to avoid overstressing the bridge diodes. The rectifier bridge power dissipation can be calculated starting from the input RMS current and the input average current through the bridge diodes. Equation 35 Equation 36 The power dissipated on a D15XB60 bridge can be estimated combining equation 35 and equation 36 with the threshold voltage (V th) and dynamic resistance (Rdiode) of a single diode of the bridge, the values of which can be found in the datasheet of the diode. Equation 37 162 min min k PFV PISW AC in rms ⋅−⋅ A V WISW rm s 65.3 318.0162 99.0902 4.380 =⋅−⋅ π min min k PFV PID AC in rms A PFV WIDrms 22.2 32.016 902 4.380 =⋅⋅ π AAII in br idgerm sin 02.3 36.42 __ =⋅=⋅= AAII in br id geavgin 92.136.422 __ =⋅=⋅= ππ avginthinrmsdi odebridge IVIRP _ 2 44 ⋅⋅+⋅⋅=

AN4149 Designing a CCM FOT-controlled PFC From this number and the given maximum ambient temperature Tambx the total maximum thermal resistance required to keep the junction temperature below 125 °C is: Equation 38

2.3.2 Input capacitor

The input filter capacitor, Cin, is placed across the output of the bridge diodes. This capacitor must smooth the high-frequency ripple and must sustain the maximum instantaneous input voltage. In a typical application an EMI filter is placed between the mains and the PFC circuit. In this application the EMI filter is reinforced by a differential mode Pi-filter after the bridge to reject the differential noise coming from the whole switching circuit. The design of the EMI filters (common mode and differential mode) is not described here. For wide-range operation the minimum value of the input filter capacitor can be calculated as follows, using a practical formula based on the output power that the PFC delivers at full load: Equation 39 The maximum value of this capacitor has to be not much higher than the minimum value to avoid the distortion of the input mains current, due to the residual voltage retained by the capacitor that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. The selected value for the input filter capacitor of this design is 1 μF.

2.3.3 Output capacitor

The output bulk capacitor (CO) selection depends on the regulated DC output voltage, the output power, the RMS current into the capacitor, the output voltage ripple and hold-up time (if requested). The value of the output capacitor to meet the output voltage ripple requirements can be defined using the following expression (equation 40). ΔVout has to be intended as twice the mains frequency peak-to-peak voltage ripple, function of the capacitor impedance and the peak capacitor current. The contribution of the ESR (equivalent series resistance) is neglected here as the capacitive reactance is dominant. Equation 40 where f l is the minimum line frequency. Although ESR usually does not affect the output ripple, it should be taken into account for power loss calculation. The total capacitor RMS ripple current, including the mains frequency and switching frequency components, is: bridge ambx th P TCR −°= 125 W C W CCR th °=°−°= 92.11 29.6 50125 outin P W FC ⋅⋅⋅= − μ3105.2 nFW W FC in 875350105.2 3 =⋅⋅⋅= − μ ou toutl ou t ou tl ou t o VVf P Vf VVHz WC o μπ 1.148 20400472 350 = ⋅⋅⋅

Designing a CCM FOT-controlled PFC AN4149 Equation 41 Reading the ESR value of the datasheet of the output capacitor chosen, the power losses associated to this ripple current can be easily calculated by: Equation 42 If the PFC stage has to guarantee a specified hold-up time, the calculation of the output capacitor is different. The value of the capacitor when the line voltage drops out, needed to deliver the output power for a certain time (t Hold) until the output voltage reaches the required minimum voltage value (Voutmin), depends on the load and the value of the ripple. When Voutmin is reached, a 'power fail' is detected, stopping the downstream system supplied by the PFC. The worst case for the hold-up time is at minimum input voltage and full load, with the line drop starting at the valley of the sine-varying ripple of the output voltage. Equation 43 Considering a 20% tolerance on the electrolytic capacitors, a value of 200 μF has been chosen, using two capacitors of commercial value of 100 μF placed in parallel. The actual hold-up time and ripple voltage with the selected value are: Actual hold-up time: Equation 44 Peak-to-peak output voltage ripple: Equation 45

2.3.4 Boost inductor

As indicated in the specs in Section 2.1: Input specification, the maximum current ripple factor Kr , that is the ratio of the maximum peak-to-peak current ripple amplitude to the outrmsCrms IIDI 22 −= AAAICrms 04.2)87.0()22.2( 22 =−= ESRIP CrmsCrms ⋅= mi n out out out Ho ldout o VVV tPC  Δ− ⋅⋅= () ( ) F VVV msWC o μ169 30010400 153502 22 = ⋅⋅= out out out ou to Hold P VVVC t  Δ−⋅ min () ( )[] msW VVVFtHold 183502 30010400200 22 −−⋅= μ ol out out Cf IV ⋅⋅⋅=Δ π2 VFHz AVout 81.14200472 87.0 =⋅⋅⋅=Δ μπ

AN4149 Designing a CCM FOT-controlled PFC inductor peak current at minimum line voltage and rated load, is 27%, as a trade-off between the inductor size and the stress on the switches. This choice led to the inductor peak-to-peak ripple current (IL PK) equal to 1.89 A (equation 32). The value of the inductance L required for the boost inductor can be calculated starting from the volt-second balance of the inductor. The minimum value of L is then a function of the duration of the OFF-time, the voltage across the inductor during T OFF, and the inductor peak-to-peak ripple current. Equation 46 The latter expression should be calculated at low line and the value found is the minimum inductance value of the PFC inductor. To find the value of L, first TOFF needs to be calculated. In a fixed-off-time control using the L4984D, the off-time (TOFF) is changed proportionally to the instantaneous line voltage in order to make the switching frequency (fSW) constant. The switching frequency is determined by a capacitor connected between the TIMER pin and ground, charged by an accurate internal generator (I TIMER) of 156 μA (typ.), during the OFF- time, generating a voltage ramp. When the voltage ramp equals the voltage on the MULT pin, connected through a resistive divider to the rectified mains to get a sinusoidal voltage reference, the OFF-time of the power MOSFET is terminated, the gate driver (GD) pin is driven high and the ramp resets at zero. The timing capacitor C T is then selected with the following formula: Equation 47 where fsw is the switching frequency and kp the maximum required divider ratio, calculated considering the maximum value of the multiplier input, that is, the voltage measured on the MULT pin at maximum mains voltage. According to the datasheet of the L4984D, the linear operating range is between 0 to 3 V, so the maximum value of the multiplier input MULTmax) is equal to 3 V. The maximum required divider ratio kp can be now found as: Equation 48 ACOFF ACpk ACout VT VIL VVL ⋅ Δ ⋅−= SWoutp TIMER T fVk IC ⋅⋅= max max 108 2652 00.3 −⋅= Vac V VAC Vk MULT p

Designing a CCM FOT-controlled PFC AN4149 The switching frequency chosen for this design is around 70 kHz, so the capacitor on the TIMER pin needed to obtain the desired frequency is (equation 47): Equation 49 A commercial value of 680 pF has been selected. An NP0 capacitor has to be used. Now TOFF can be finally calculated. Along a line half-cycle, TOFF varies from nearly zero to the maximum value, occurring at the MULT peak voltage. To calculate the boost inductor the value at the MULT peak should be considered, found simply from the product of the maximum required divider ratio k p and the peak of the rectified input voltage at low mains voltage (Vpkmin). The maximum OFF-time at VACmin is then: Equation 50 The value of the inductance L required for the boost inductor at VACmin can now be calculated with equation 46. Equation 51 The value chosen for the inductor is 700 μH.

2.3.5 Power MOSFET selection and power dissipation calculation

The selection of the MOSFET concerns mainly RDS(on), that should be low in order to minimize conduction losses, without increasing the switching losses due to the MOSFET 's equivalent output capacitance C oss. To achieve high efficiency both RDS(on) and Coss have to be taken into account, and the trade-off between cost vs. performance must also be considered. The MOSFET breakdown voltage is needed, considering the PFC nominal output voltage and adding some margin (20%) to guarantee reliable operation. Therefore, a minimum voltage rating of 500 V (1.2 · V out = 480 V) is selected. In this 350 W CCM PFC application, two STF21N65M5 (placed in parallel) have been chosen, to improve robustness against surges and burst tests, and 650 V MOSFETs have been chosen, having a good balance between R DSon and Coss. In order to calculate the contribution of the MOSFETs to the total efficiency of the system, the power losses have been calculated, which are mainly the sum of the conduction, switching and capacitive losses. pF kHzV AC T 695 70400108 156 3 = ⋅⋅⋅ = − μ sV A pFVT ACOFF μμ 4.4902108 156 680)( 3 )()( 2)( min min min min ACOFF ACpk ACout VTVIL VVVACL ⋅Δ ⋅−= Hs A VVVACL μμ 6544.4 85.1 902400)( min =⋅⋅−=

AN4149 Designing a CCM FOT-controlled PFC The conduction losses at maximum load and minimum input voltage are calculated by: Equation 52 Because normally in a MOSFET datasheet RDS(on) is given at ambient temperature (25 °C), in order to properly calculate the conduction losses at 100 °C (typical MOSFET junction operating temperature), a factor K TEMP between 1.5 to 2, which can be found in the device datasheet, should be taken into account. In the case of the STF21N65M5, looking at the normalized ON resistance vs. temperature graph, a factor of 1.7 should be considered at 100 °C. Equation 53 where the RDS on value is divided by two since two MOSFETs are placed in parallel. The maximum RMS switching current, at minimum VAC, has been found from equation 33. Now, from equation 52 and equation 53, and considering that two MOSFETs in parallel have been used, the maximum conduction losses at low line and full load can be calculated as: Equation 54 The switching losses are difficult to predict as they depend on the particular switching waveform, determined by many factors (driving current, gate resistors, MOSFET gate internal resistance, Vth, gate charge, total capacitance on the drain node including parasitic capacitances etc.). A good approximation to determine the generic switching losses due to the MOSFET commutation occurring at turn-on and turnoff can be basically expressed by: Equation 55 where V DS is the drain-to-source of the MOSFET, ID the average drain current and trise and tfall refer to the rising and the falling edge of VDS . To estimate the rising and falling times of the drain voltage, datasheet values of the switching performance of the MOSFET can be used. First the average rising times of the drain voltage can be calculated considering the total drain node capacitance and the average value of the peak current flowing through the inductor. () 2 )()( VACISWRDSVACP rm soncond ⋅= Ω=⋅Ω=⋅= ° 152.07.1 179.0 ___ 25_@ 100_@ TEMP Con CDSon K MOSFETsparalleledofNum RDS R () ( ) 2 100_@ )(VACISWRVACP rmsCDS o ncond ⋅= ° () ( ) WAVPcond 02.265.3152.090 =⋅Ω= () () swfallriseDDSsw fttIVVACP ⋅+⋅⋅⋅= 2

Designing a CCM FOT-controlled PFC AN4149 The exact value of the MOSFET's COSS is indicated in the datasheet looking at the graph representing COSS vs. VDS. At VDS equal to 400 V, COSS is 40 pF. This value should be multiplied by two as two MOSFETs have been used in parallel, and adding a rough 100pF of all other contributions, C D can be found: Equation 56 Then the average rising time of the drain voltage is: Equation 57 However, the average falling time depends on the driving current IG (limited by the resistor placed on the gate), the MOSFET's total gate charge QG and the driving voltage Vdr, supposed here equal to VCC (for example, 15 V) applied for simplicity. In the resistor calculation the intrinsic gate resistance should also be considered. In the case of the STF21N65M5, R G is 2.5 Ω which has to be added to the externally placed resistor R Gext (3.3 Ω in this design). Equation 58 Finally, the MOSFET’s switching losses can be estimated with equation 55: Equation 59 To estimate the capacitive losses, that is, the losses due to the discharge of the total drain capacitance through the MOSFET at turn-on, this simple expression can be considered: Equation 60 pFpFpFCCC strayOSSD 1801004022 =+⋅=+⋅= ns IL VC I VCt pk DSD D DSD rise 17 max ⋅=⋅= π π nsV nC RR V Q I Qt GGext dr G G G Cfall 19 5.23.3 50 ≈ Ω+Ω () () WkHznsnsAVVPSW 2.270191736.4400 190 =⋅+⋅⋅⋅= )(2 1)( VACfVCVACP swDSDcap ⋅⋅⋅= () WkHzVpFVPcap 1704001802 1)90( =⋅⋅⋅=

Designing a CCM FOT-controlled PFC AN4149

2.3.6 Boost diode selection

Following criteria similar to those used for the calculation of the MOSFET losses, the output rectifier can be properly selected. A minimum breakdown voltage of 1.2·(V out) and a minimum current rating higher than 5·I out (equation 26) can be considered for an initial rough selection of the rectifier. The correct selection is then confirmed by the thermal calculation, as the diode junction temperature must be below 125 °C. Since this circuit operates in the continuous current mode, reverse recovery is experienced by the diode, and the MOSFET at turn-on has to carry also the boost diode minority carrier charge. Then, to minimize the recovery losses, an ultra-fast diode with low t rr (reverse recovery time, the time required to deplete the stored charge) and Q rr (reverse recovery charges, the charge that must be dissipated on the MOSFET) or a SiC rectifier has to be selected. In this 350 W application the STTH8S06 (600 V, 8 A) has been selected and shows very fast reverse recovery time, 12 ns typical (measured for IF =1 A). The rectifier AVG (equation 26) and RMS (equation 33) current values, the V th (rectifier threshold voltage) and Rd (dynamic resistance) given in the datasheet allow calculating the rectifier losses. From the STTH8S06 datasheet, Vth is 1.2 V, and Rd is 0.087 Ω, the conduction losses are equal to: Equation 63 Since the converter is working in continuous conduction mode the losses in the MOSFETs due to the recovery of the boost diode have to be taken into account. The energy loss due to the reverse recovery effect of the diode is: Equation 64 Where V R is the reverse voltage across the output diode, when it stops conducting, that is

400 V, and Qrr the reverse recovery charges, the charge that must be dissipated through the

MOSFET. On the datasheet the graph of Qrr vs. dIF/dt is represented. Following the 0.5 xIF(AV) curve at Tj = 125 °C a value of 80 nC is found assuming the typical case of 200 A/us. Then the recovery energy is: Equation 65 And the reverse recovery losses are: Equation 66 =⋅Ω+⋅= rrRrr QVE ⋅= JnCVE rr μ3280400 =⋅= WkH zJfEP swrrrr 24.27032 =⋅=⋅= μ

AN4149 Designing a CCM FOT-controlled PFC If a single heatsink for the MOSFETs and diode is used, the maximum total losses of the switches should be considered: Equation 67 From this number and the given maximum ambient temperature, the total maximum thermal resistance required can be found as: Equation 68 In this design in order to keep the junction MOSFET temperature below 100 °C (around 90 °C measured on the package) and to ensure a higher degree of reliability, the thermal resistance has been chosen equal to: Equation 69 WWWWPVPVPP rrdiodelossswitch 56.924.248.184.5)90()90( =++=++= switch ambx th P TCR −°= 125 W C W CCRth °=°−°= 85.7 56.9 50125 W C W CCRth °=°−°= 23.557.9 50100

L4984D biasing circuitry AN4149

3 L4984D biasing circuitry

The following sections describe the selection of the circuitry around the L4984D.

3.1 Feedback and OVP

Pin 1 (INV): this pin is connected both to the inverting input of the E/A and to the OVP circuitry. A resistive divider has to be connected between the boost regulated output voltage and this pin. The internal reference on the non-inverting input of the E/A is 2.5 V (typ.), the output voltage (V out) of the PFC pre-regulator is set at the nominal value by the resistor ratio of the feedback output divider. RoutH and RoutL will be then selected considering the desired nominal output voltage and the desired output power dissipated on the output divider. For example for a 25 mW output divider dissipation: Equation 70 Please note that for RoutH a resistor with a suitable voltage rating (> 400 V) is needed, or more resistors in series have to be used. Here three 2.2 M Ω resistors in series have been selected. Equation 71 Equation 72 For RoutL a value of 160 kΩ in parallel to a 56 kΩ has been selected. Pin 2 (COMP): this pin is the output of the E/A that is fed to one of the inputs of the multiplier. A feedback compensation network is placed between this pin and INV. It has to be designed in with a narrow bandwidth in order to avoid that the system rejects the output voltage ripple (100 Hz) that would bring high distortion of the input current waveform. A theoretical criterion to define the compensation network value is to set the E/A bandwidth (BW) below 20 Hz. The compensated two-pole feedback network selection for this 350 W FOT PFC has been described in detail in Section 4: FOT PFC boost control loop. Pin 6 (PFC_OK - Feedback failure protection): PFC_OK pin has been dedicated to monitor the output voltage of a separate resistor divider. This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value (Vovp), usually larger than the maximum V out that can be expected, also including worst-case load/line transients. For a maximum output voltage Voutmax of 430 V and selecting a 50 μA current flowing in to the divider: mW VVR out outH 5.2 () Ω=−= M mW VVRoutH 320.6 5.2400 2 5.2 V V R R out outL outH 15915.2 400 =−= V V R R outL outH 159 out outL VR = Ω=Ω= kMRoutL 7.39 159 6.6

AN4149 L4984D biasing circuitry Equation 73 By selecting a commercial value of 56 kΩ: Equation 74 Three resistors 3.3 MΩ in series provide the calculated value for the PFC_OK high resistor. Notice that both feedback dividers connected to the L4984D pin #1 (INV) and pin #6 (PFC_OK) can be selected without any constraints. The unique criterion is that both dividers have to sink a current from an output bus which needs to be significantly higher than the current biasing the error amplifier and the PFC_OK comparator. The OVP function handles "normal" overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at startup. In case the overvoltage is generated by a feedback failure, for instance when the upper resistor of the output divider (R1) fails open, eventually the error amplifier output (COMP) will saturate high and the voltage on its inverting input (INV) will drop from its steady-sate value (2.5 V). An additional comparator monitors the voltage on pin INV, comparing it against a reference located at 1.66 V. When the voltage on pin PFC_OK exceeds 2.5 V and, simultaneously, the voltage on pin INV falls below 1.66 V, the FFD function is triggered: the gate drive activity is immediately stopped, the device is shut down and its quiescent consumption reduced. This condition is latched and in order to restart the L4984D it is necessary to recycle the input power, so that the V cc voltage falls below 6 V (VCCrestart). The pin PFC_OK doubles its function as a non-latched IC disable: a voltage below 0.23 V shuts down the L4984D, reducing its consumption below 2.2 mA. To restart simply let the voltage on the pin rise above 0.27 V. Note that these functions offer complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a pin PFC_OK floating will result in shutting down the L4984D and stopping the pre-regulator. divider OKPF CREF L I VR = Ω== kA VRL 5050 5.2 μ  −⋅= 1 OKPFCREF MA XOU T LH V VRR Ω=   −⋅Ω= MV VkRH 623.915.2 43056

L4984D biasing circuitry AN4149

3.2 Current sense resistor

Pin 4 (CS): The pin #4 is the inverting input of the current sense comparator. Through this pin, the L4984D senses the instantaneous inductor current, converted in a proportional voltage by an external sensing resistor (R S). As this signal crosses the threshold set by the multiplier output, the PWM latch is reset and the power MOSFET is turned off. The threshold is defined by: Equation 75 where: CS (multiplier output) is the reference for the current sense (V CS_OFFSET is its offset). –k m=0.23 (typ.) is the multiplier gain. –V COMP is the voltage on pin 2 (E/A output). –V MULT is the voltage on pin 3. –V FF is the second input to the multiplier for 1/V2 function. It compensates the control loop gain dependence on the mains voltage. The voltage at this pin is a DC level equal to the peak voltage on pin MULT (pin 3). The sense resistor value (R S) can be calculated as follows. For the 350 W PFC it will be: Equation 76 Where: –I Lpk is the maximum peak current in the inductor, calculated with –V csm in = 0.84 V is the minimum value of the L4984D current sense reference clamp (VCSclamp in the datasheet). According to the result, three parallel resistors of 0.33 Ω with 1 W of power rating have been selected. Because the internal current sense clamping sets the maximum current that can flow in the inductor, the maximum peak of the inductor current will be calculated considering the maximum V csclamp admitted on the L4984D: Equation 77 The calculated ILpkx will be the value at which the boost inductor shall not saturate and it will be used for calculating the inductor number of turns and air gap length. The power dissipated by R S is given by: Equation 78 )5.2( FF MULTCOMP mOFFSE TCSCS V VVVkVV ⋅−⋅+= Ω=< 12.00.7 84.0 A VRs AVIL pkx 45.811.0 93.0 =Ω= rm sss ISWRP ⋅= () WPs 53.173.311.0 =⋅Ω=

3.3 Mult divider and VFF

resistive divider, to the rectified mains to get a sinusoidal voltage reference. the inner current control loop. Figure 13. Multiplier characteristics Figure 14. Multiplier characteristics

L4984D biasing circuitry AN4149 In this way a change of the line voltage will cause an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles, the amplitude of the multiplier output will be halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain will be constant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. Actually, with other PFC embedding the voltage feed-forward, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small, the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF). If it is too large, there will be a considerable delay in setting the right amount of feed-forward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a trade- off was required. The L4984D implements an innovative voltage feed-forward which, with a technique that makes use of just two external parts, overcomes this time constant trade-off issue whichever voltage change occurs on the mains, both surges and drops. A capacitor C FF and a resistor RFF, both connected from the pin VFF (pin #5) to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (pin #3). In this case following values have been selected: Equation 80 In this way, in case of sudden line voltage rise, C FF will be rapidly charged through the low impedance of the internal diode. In case of line voltage drop, an internal "mains drop" detector enables a low impedance switch which suddenly discharges C FF avoiding a long settling time before reaching the new voltage level. Consequently, an acceptably low steady-state ripple and low current distortion can be achieved without any considerable undershoot or overshoot on the preregulator's output like in systems with no feed-forward compensation. This pin is internally connected to a comparator in order to provide the brownout (AC mains undervoltage) protection. A voltage below 0.8 V shuts down (does not latched ) the L4984D and brings its consumption to a considerably lower level. The L4984D restarts as the voltage at the pin rises above 0.88 V. These data have to be considered during the MULT divider selection, setting the minimum operating voltage. Please find here following the procedure to set properly the operating point of the multiplier and the divider resistor values. Supposing a 60 uA (I MULT) current flowing into the multiplier divider, the lower resistor value can be calculated: Equation 81 A commercial value of 51 kΩ for the lower resistor is selected. The upper resistor value can now be calculated: Equation 82 FCFF μ1= Ω= MRFF 1 Ω=== kA V I VR MULT MULT multL 5060 00.3max μ Ω=Ω⋅⋅ MkRk kR mu ltL p p multH 944.656108 10811

AN4149 L4984D biasing circuitry In this application example a RmultH = 6.9 MΩ and a RmultL = 51 kΩ have been selected. Please note that for RmultH a resistor with a suitable voltage rating (> 400 V) is needed, or more resistors in series will have to be used. The voltage on the multiplier pin with the selected component values re-calculated at minimum line voltage is 0.93 V and at maximum line voltage is 2.74 V, so the multiplier will work correctly within its linear region. Finally, depending on the MULT resistors the brownout functions also have to be checked, calculating the V START and VSTOP voltages: Equation 83 Equation 84 Start and stop PFC voltages are suitable for correct operation by the PFC; the MULT divider has to be set considering these two voltages, in order to disable the PFC with an anomalous input low mains voltage that could cause an overheating of the PFC due to the higher input mains current. In order to set the required voltage startup threshold reiterations could be required by selecting MULT resistors and checking the actual PFC start voltage.

3.4 Gate driver (GD) and VCC pins

Pin 8 (GND): this pin acts as the current return both for the signal internal circuitry and for the gate drive current. When laying out the printed circuit board, these two paths should run separately. Pin 9 (GD): is the output of the driver. The pin is able to drive an external MOSFET with 600 mA source and 800 mA sink capability. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages in case the pin is supplied with a high V cc. To avoid undesired switch-on of the external MOSFET because of some leakage current when the supply of the L4984D is below the UVLO threshold, an internal pull-down circuit holds the pin low. The circuit guarantees 1.1 V maximum on the pin (at I sink=2mA), with Vcc > VCC_ON. This allows omitting the "bleeder" resistor connected between the gate and the source of the external MOSFET used for this purpose. Pin 10 (V CC): is the supply of the device. This pin will be externally connected to the startup circuit (usually, one resistor connected to the rectified mains) and to the self-supply circuit. Whatever the configuration of the self-supply system, a capacitor will be connected between this pin and ground. To start the L4984D, the voltage must exceed the startup threshold (12 V typ.). Below this value the device does not work and consumes around 65 µA (typ.) from V CC. This allows the use of high value startup resistors (in the hundreds of k Ω), which reduces power consumption and optimizes system efficiency at low load, especially in wide- range mains applications. When operating, the current consumption (of the device only, not considering the gate drive current) rises to a value depending on the operating conditions but never exceeding 6 mA. The device keeps on working as long as the supply voltage is over the UVLO threshold (13 V max). If the V CC voltage exceeds 22.5 V, an internal Zener multL mult LmultH STA RT R RRVV +⋅= 88.0 Vk kMVVSTART 29.7756 569.6 88.0 =Ω Ω+Ω⋅= multL mult Lmu lt H STOP R RRVV +⋅= 80.0 Vk kMVVSTOP 2.7051 519.6 80.0 =Ω Ω+Ω⋅=

the device is below the minimum clamping voltage of the pin.

4 FOT PFC boost control loop

Figure 15. Small signal model of a PFC stage with a constant-power load (DC-DC

AN4149 FOT PFC boost control loop where the unity gain factor Go is given by the following expression regardless of the control method and the characteristics of the control IC: Equation 86 In the previous expression Vc is the error signal of the voltage control loop (voltage on the COMP pin for the L4984D), that is, the output of the error amplifier, and VCO the "zero- power" level of the control voltage, that is, the burst mode threshold of COMP voltage (2.4 V, typ.). The effective control voltage V comp - VC0, can be expressed for the L4984D starting from the expression of the variation of signal out from the modulator with respect to the E/A output (COMP) change, using the formula indicated in the datasheet of the L4984D (equation 87). Equation 87 Where k m is the small signal multiplier gain assumed here equal to the large single gain k m (typ. 0.304). From this expression, replacing: Equation 88 and rewriting equation 31 which describes the maximum inductor peak current as: Equation 89 the effective control voltage Vcomp-VCO can be found: Equation 90 Then this expression can be used to find the unity gain factor (equation 86): oCCou t out o CVVV PG ⋅−⋅ )( 0 4.2 FF MULTCOMP mO FFSETCSCS V VVVkVV ⋅−⋅+= pACFF KVV ⋅⋅= 2 LpkSCS IRV ⋅=  +⋅⋅⋅ ⋅⋅= 212 r AC outout pk K PFV VIIL η r m inpS CCOMP K K PKRVV

AN4149 FOT PFC boost control loop The transfer function of the compensated error amplifier is: Equation 92 In order to calculate the values of the components of the compensation network, the Venable K-Factor calculation is used, starting from the amount of phase margin needed at the crossover frequency and the desired maximum 3 rd harmonic distortion level D3. Phase margin is defined as the difference between 180 ° and the actual phase lag at the frequency where the open-loop gain is unity. The higher the phase margin, the more over- damped the system is. As rule of thumb, to ensure fast transient response with a good level of ringing, a phase margin of 60 ° has to be chosen. The Venable K-factor is defined as: Equation 93 The required E/A gain (at 2f L) in order to keep the distortion below the desired maximum 3rd harmonic distortion (D3) is: Equation 94 while the unity frequency gain is: Equation 95 The frequency of the zero and the pole of the compensation network can be found with the following two expressions, where Go is the unity gain factor (equation 91). ⋅⋅⋅ ++⋅ ⋅⋅+ 212 1_ 1 1)( CCRs CCs CRs CR sG HINV EA %23 =D °=Φ 60m 732.3 180cos 180sin1  ⋅  ⋅+ m m K φπ φπ )(2 out r m inpS out CCOMP f V K k PkR D V VVDH Δ  +⋅ ⋅⋅⋅ −⋅⋅= 018.0281.14 27.0123.0 4.380108011.0202.02 2 = V W H f 2min_ K Hf H fLINE ⋅⋅ π 763.0 732.3 018.0474 20 =⋅⋅= HzH π

Then the values of the components can be calculated as follows. A value of 22 nF has been selected for the parallel feedback capacitor. A value of 220 nF has been selected for the series feedback capacitor. A value of 330 kΩ has been selected for the series feedback resistor. Figure 18. Bode plots of a type II amplifier's transfer function

Figure 19. Bode plots of the closed-loop transfer function Finally all the parameters describing the actual closed-loop transfer function are calculated.

5 Layout hints

350W PCB layout as a reference (Figure 23). converter must be connected to this return point. boost rectifier and the output capacitor. – Keep signal components as close as possible to each relevant pin of the L4984D. – Connect heatsinks to power GND. – Add an external shield to the boost inductor and connect it to power GND. PFC_OK and MULT dividers close to pin 8 (GND) of the L4984D. (GND) of the L4984D. Connect this point to the RTN star point (see rule 1). Figure 22. EVL4984-350W PCB layout (SMT side view)

6 Design example using the L4984D-CCM PFC excel

boost CCM PFC pre-regulator using the L4984D. Figure 23. Excel spreadsheet design specification input table Figure 24. Other design data following the calculation procedure described in this document .

Figure 25. CCM PFC schematic based on the L4984D

Figure 26. Excel spreadsheet BOM

350 W FOT PFC BASED ON L4984D

7 References

– L4984D, CCM PFC controller", datasheet. – A new continuous-time model for current-mode control with constant frequency, constant On-time and constant Off-time, in CCM and DCM", IEEE power electronics specialists conference record, San Antonio, Texas, pp. 382-389, 1990. – Current mode control, venable technical paper #5, www.venableind.com. – Fixed-Off-Time control of PFC pre-regulators", 10 th European conference on power electronics and applications, EPE2003, Toulouse France, paper 382. – A systematic approach to frequency compensation of the voltage loop in boost PFC pre-regulator", abstract.

8 Revision history

Table 1. Document revision history 07-Mar-2013 1 Initial release. 06-Jun-2013 2 Updated title in cover page and Figure 26: Excel spreadsheet BOM.