AN4149 FAIRCHILD | Alldatasheet

Document overview

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Technical content

  1. Step-by-step Design Procedure

Figure 2. Flow Chart of Design Procedure

  • Maximum output power (Po).

applications, the typical efficiency is 80~83%. control in normal operation.

  1. Define the system specifications
  2. Determine DC link capacitor (CDC)
  3. Determine the reflected output voltage
  4. Determine the proper core and the
  5. Determine the number of turns for each
  6. Choose proper FPS considering input
  7. Determine the transformer primary side
  8. Determine the startup resistor
  9. Determine the wire diameter for each
  10. Design the voltage drop circuit for burst
  11. Design the feedback control circuit
  12. Design the synchronization network
  13. Determine the output capacitors
  14. Choose the secondary side rectifier diodes

2 Pin 1D ch–()⋅

Figure 9. Burst operation in standby mode amplifier and an opto-coupler to regulate the output voltage. PSR is used, set Vcc to 32.5V . Figure 10 shows the typical st artup circuit for KA5Q-series. charged up to the start voltage and FPS will fail to start up. startup current (200uA) of FPS.

22 Vstart Vline

winding based on the RMS current of each output. output defined in equation (2). severe eddy current losses as well as to make winding easier. where Ac is the actual conductor area and KF is the fill factor. applications and 0.15~0.2 for multiple output applications. min) as can be seen in equation (7) and (10). secondary side based on the voltage and current ratings. average forward current of the diode. maximum reverse recovery time. Table 3. Fairchild Diode Quick Selection Table

©2003 Fairchild Semiconductor Corporation [STEP-11] Determine the output capacitors considering the voltage and current ripple. The ripple current of th e n-th output capacitor ( Co(n)) is obtained as where Io(n) is the load current of the n-th output and ID(n) rms is specified in eq uation (23). The ripple current should be smaller than the maximum ripple current specification of the capacitor. The voltage ripple on the n-th output is given by where Co(n) is the capacitance, Rc(n) is the effective series resistance (ESR) of the n-th output capacitor, KL(n), Dmax and Ids peak are specified in equations (2), (6) and (8) respectively, VRO is specified in STEP-3, Io(n) and Vo(n) are the load current and output voltage of the n-th output, respectively and V F(n) is the diode (DR(n)) forward voltage drop. Sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high ESR of the electrolytic capacitor. In thos e cases, additional L-C filter stages (post filter) can be us ed to reduce the ripple on the output. [STEP-12] Design the synchronization network. KA5Q-series employs a quasi resonant switching technique to minimize the switching noise as well as switching loss. In this technique, a capacitor ( C r) is added between the MOSFET drain and source as shown in Figure 11. The basic waveforms of a quasi-resonant converter are shown in Figure 12. The external capacitor lowers the rising slope of drain voltage, which reduces the EMI caused by the MOSFET turn-off. To minimize the MOSFET switching loss, the MOSFET should be turned on when the drain voltage reaches its minimum value as shown in Figure 12. The optimum MOSFET turn-on time is indirectly detected by monitoring the Vcc winding voltage as shown in Figure 11 and 12. The output of the sync detect comparator (CO) becomes high when the sync voltage ( V sync) exceeds 4.6V and low when the Vsync reduces below 2.6V . The MOSFET is turned on at the falling edge of the sync detect comparator output (CO). Figure. 11 Synchronization Circuit The peak value of the sync signal is determined by the voltage divider network RSY1 and RSY2 as Choose the voltage divider RSY1 and RSY2 so that the peak value of sync voltage ( Vsync pk) is lower than the OVP threshold voltage (12V) in order to avoid triggering OVP in normal operation. Typically, V sync pk is set to 8~10V . To synchronize the Vsync with the MOSFET drain voltage, choose the sync capacitor ( CSY) so that TF is same as TQ as shown in Figure 12. TF and TQ are given, respectively, as where Lm is the primary side inductance of the transformer, Ns and Na are the number of turns for the output winding and Vcc winding, respectively and Ceo is the effective MOSFET output capacitance (Coss+Cr). Icap n() rms IDn() rms() Ion() 2–= (26) ∆Von() Ion() Dmax Con() fs peak VRO RCn() KLn() Vcc Ca Da GND Cr Drain Ids Rcc RSY1 RSY2 Sync Vo1 CSY Vds Ns1Np Lm CO 4.6/2.6V DSY Na KA5Q-series Vsync Sync comparator Vsync pk RSY2 TF π Lm Ceo⋅⋅= (29) TQ RSY2 CSY Vcc ⎛⎞ln⋅⋅= (30)

voltage, which is typically 2.5V . Figure 15. Control Block Diagram coupler and R1, RD, RF, CF and CB are shown in Figure 15. Figure 16. QR Flyback Converter Control-to Output

Figure 17. QR Flyback Converter Control-to Output varies according to the operating conditions. zero is lowest at low input voltage and full load condition. voltage condition under universal input condition. cancel the control-to-output gain at fc. (c) Place a compensator zero (fzc) around fc/3. (d) Place a compensator pole (fpc) around 3fc. Figure 18. Compensator Design where Vo1 is the reference output voltage. B determine the shutdown time. Figure 19. Delayed Shutdown

2.5 R 1⋅

©2005 Fairchild Semiconductor Corporation (c) The resistors Rbias and RD used together with the opto- coupler H11A817A and the shunt regulator KA431 should be designed to provide proper operating current for the KA431 and to guarantee the fu ll swing of the feedback voltage for the FPS device chosen. In general, the minimum values of cathode voltage and current for the KA431 are 2.5V and 1mA, respectively. Therefore, R bias and RD should be designed to satisfy the following conditions: where Vbias is the KA431 bias voltage as shown in Figure 16 and VOP is opto-diode forward voltage drop, which is typically 1V . IFB is the feedback current of FPS, which is typically 1mA. Vbias VOP– 2.5– RD VOP Rbias

©2005 Fairchild Semiconductor Corporation Design Example I (KA5Q0765RT) Schematic Application Device Input Voltag e Output Power Output Voltage (Rated Current) Color TV KA5Q0765RT 85-265Vac (60Hz) 82W 125V (0.4A) 20V (0.5A) 16V (1.0A) 12V (0.5A) C104 47uF 50V EER3540 20V, 0.5A C210 1000uF 35V D201 EGP20D LF101 C101 330nF 275VAC F101 FUSE 250V 3.0A C102 220uF 400V RT101 5D-9 BD101 D103 1N4937 R107 5.1Ω 0.25W R106 680Ω 0.25W24 GND Drain SYNC FB Vcc D106 1N4148 IC101 KA5Q0765RT C109 47nF 50V R105 470Ω 0.25W C105 3.9nF 50V ZD101 4.7V 0.5W C103 100nF 50V C107 1nF 1kV L101 BEAD D105 1N4937 C212 470pF 1kV L204 BEAD 12V, 0.5A D205 EGP20D C208 1000uF 35V C207 470pF 1kV L203 BEAD 125V, 0.4A D203 EGP20J C214 100uF 160V C206 470pF 1kV L202 BEAD C215 47uF 160V 16V, 1A D202 EGP20D C202 1000uF 35V C205 470pF 1kV L201 BEAD PC301 817A R201 1kΩ 0.25W C203 22nF 50V C108 2.2nF Q201 KA431 R204 39kΩ 0.25W R203 1kΩ 0.25W R206 220kΩ 0.25W R205 4.7kΩ 0.25W VR201 30kΩ D201 VR202 30kΩ Q202 KSC945 R208 5.1kΩ 0.25W R207 5.1kΩ 0.25W SW 201 R104 68kΩ 0.5WR103 68kΩ 0.5W

©2005 Fairchild Semiconductor Corporation Transformer Specifications Transformer Schematic Diagram Winding Specifications

Electrical Characteristics

Core & Bobbin Core : EER 3540 Bobbin : EER3540 Ae : 109 mm No Pin (s →f) Wire Turns Winding Method Np1 1 - 3 0.6 φ × 1 35 Center Winding N125V/2 16 - 15 0.6 φ × 1 28 Center Winding N16V 18 - 17 0.4 φ × 2 8 Center Winding N12V 12 - 13 0.5 φ × 1 6 Center Winding Np2 3 - 4 0.6 φ × 1 35 Center Winding N125V/2 15 - 14 0.5 φ × 1 28 Center Winding N20V 11 - 10 0.5 φ × 1 10 Center Winding Na 7 - 6 0.3 φ × 1 11 Center Winding Pin Specification Remarks Inductance 1 - 4 565uH ± 5% 1kHz, 1V Leakage Inductance 1 - 4 10uH Max 2 nd all short EER3540 N16V Na N125V /2 N12 V N20 V Np1 N p2 91 0 N125V /2 N125V/2 Np2 N12V N125V/2 N16V Np1 N20V Na

©2005 Fairchild Semiconductor Corporation Design Example II (KA5Q1265RF) Schematic Application Device Input Voltag e Output Power Output Voltage (Rated Current) Color TV KA5Q1265RF 85-265Vac (60Hz) 154W 125V (0.8A) 20V (0.5A) 16V (2.0A) 12V (1.0A) C104 47uF 50V EER4242 20V, 0.5A C210 1000uF 35V D201 EGP20D LF101 C101 330nF 275VAC F101 FUSE 250V 5.0A C102 470uF 400V RT101 10D-9 BD101 D103 1N4937 R107 5.1Ω 0.25W R106 680Ω 0.25W24 GND Drain SYNC FB Vcc D106 1N4148 IC101 KA5Q1265RF C109 47nF 50V R105 470Ω 0.25W C105 2.7nF 50V ZD101 4.7V 0.5W C103 100nF 50V C107 1.5nF 1kV L101 BEAD D105 1N4937 C212 470pF 1kV L204 BEAD 12V, 1A D205 EGP20D C208 2200uF 35V C207 470pF 1kV L203 BEAD 125V, 0.8A D203 EGP30J C214 220uF 200V C206 470pF 1kV L202 BEAD C215 100uF 200V 16V, 2A D202 EGP30D C202 2200uF 35V C205 470pF 1kV L201 BEAD PC301 817A R201 1kΩ 0.25W C203 22nF 50V C108 2.2nF Q201 KA431 R204 39kΩ 0.25W R203 1kΩ 0.25W R206 220kΩ 0.25W R205 4.7kΩ 0.25W VR201 30kΩ D201 VR202 30kΩ Q202 KSC945 R208 5.1kΩ 0.25W R207 5.1kΩ 0.25W SW 201 R104 68kΩ 0.5WR103 68kΩ 0.5W

©2005 Fairchild Semiconductor Corporation Transformer Specifications Transformer Schematic Diagram Winding Specifications Core & Bobbin Core : EER 4242 Bobbin : EER4242 Ae : 234 mm No Pin (s →f) Wire Turns Winding Method Np1 1 - 3 0.5 φ × 2 22 Center Winding N125V/2 16 - 15 0.5 φ × 2 18 Center Winding N16V 18 - 17 0.5 φ × 2 5 Center Winding N12V 12 - 13 0.4 φ × 2 4 Center Winding Np2 3 - 4 0.5 φ × 2 22 Center Winding N125V/2 15 - 14 0.5 φ × 2 18 Center Winding N20V 11 - 10 0.5 φ × 1 6 Center Winding Na 7 - 6 0.3 φ × 1 7 Center Winding Pin Specification Remarks Inductance 1 - 4 385uH ± 5% 1kHz, 1V Leakage Inductance 1 - 4 10uH Max 2 nd all short N125V/2 Np2 N12V N125V/2 N16V Np1 N20V Na EER4242 N16V Na N125V /2 N12 V N20 V Np1 N p2 91 0 N125V /2

©2005 Fairchild Semiconductor Corporation Design Example III (KA5Q1565RF) Schematic Application Device Input Voltag e Output Power Output Voltage (Rated Current) Color TV KA5Q1565RF 85-265Vac (60Hz) 217W 125V (1.0A) 20V (1.0A) 16V (3.0A) 12V (2.0A) C104 47uF 50V EER5345 20V, 1A C210 1000uF 35V D201 EGP20D LF101 C101 330nF 275VAC F101 FUSE 250V 5.0A C102 470uF 400V RT101 10D-9 BD101 D103 1N4937 R107 5.1Ω 0.25W R106 680Ω 0.25W24 GND Drain SYNC FB Vcc D106 1N4148 IC101 KA5Q1565RF C109 47nF 50V R105 470Ω 0.25W C105 2.7nF 50V ZD101 4.7V 0.5W C103 100nF 50V C107 2nF 1kV L101 BEAD D105 1N4937 C212 470pF 1kV L204 BEAD 12V, 2A D205 EGP30D C208 2200uF 35V C207 470pF 1kV L203 BEAD 125V, 1A D203 FFPF05U60S C214 330uF 200V C206 470pF 1kV L202 BEAD C215 220uF 200V 16V, 3A D202 FFPF05U20S C202 2200uF 35V C205 470pF 1kV L201 BEAD PC301 817A R201 1kΩ 0.25W C203 22nF 50V C108 2.2nF Q201 KA431 R204 39kΩ 0.25W R203 1kΩ 0.25W R206 220kΩ 0.25W R205 4.7kΩ 0.25W VR201 30kΩ D201 VR202 30kΩ Q202 KSC945 R208 5.1kΩ 0.25W R207 5.1kΩ 0.25W SW 201 R104 68kΩ 0.5WR103 68kΩ 0.5W

©2005 Fairchild Semiconductor Corporation Transformer Specifications Transformer Schematic Diagram Winding Specifications Core & Bobbin Core : EER 5345 Bobbin : EER5345 Ae : 318 mm No Pin (s →f) Wire Turns Winding Method Np1 1 - 3 0.6 φ × 2 21 Center Winding N125V/2 16 - 15 0.6 φ × 2 17 Center Winding N16V 18 - 17 0.6 φ × 3 5 Center Winding N12V 12 - 13 0.6 φ × 2 4 Center Winding Np2 3 - 4 0.6 φ × 2 21 Center Winding N125V/2 15 - 14 0.6 φ × 2 17 Center Winding N20V 11 - 10 0.5 φ × 1 6 Center Winding Na 7 - 6 0.3 φ × 1 7 Center Winding Pin Specification Remarks Inductance 1 - 4 325uH ± 5% 1kHz, 1V Leakage Inductance 1 - 4 10uH Max 2 nd all short EER5345 N16V Na N125V/2 N12 V N20 V Np1 Np2 91 0 N125V /2 N125V/2 Np2 N12V N125V/2 N16V Np1 N20V Na

9/20/05 0.0m 002 © 2005 Fairchild Semiconductor Corporation DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPROATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Hangseok Choi, Ph.D Power Conversion Team / Fairchild Semiconductor Phone : +82-32-680-1383 Facsimile : +82-32-680-1317 E-mail : hangseok.choi@fairchildsemi.com