AN4146 FAIRCHILD | Alldatasheet

Document overview

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Technical content

  1. Step-by-step Design Procedure

Figure 2. Flow Chart of Design Procedure

  • Maximum output power (Po).

applications, the typical efficiency is 80~83%. control in normal operation.

  1. Define the system specifications
  2. Determine DC link capacitor (CDC)
  3. Determine the reflected output voltage
  4. Determine the proper core and the
  5. Determine the number of turns for each
  6. Choose proper FPS considering input
  7. Determine the transformer primary side
  8. Determine the startup resistor
  9. Determine the wire diameter for each
  10. Design the voltage drop circuit for burst
  11. Design the feedback control circuit
  12. Design the synchronization network
  13. Determine the output capacitors
  14. Choose the secondary side rectifier diodes

2 Pin 1D ch–()⋅

©2005 Fairchild Semiconductor Corporation Figure. 11 Startup and Vcc Auxiliary Circuit - Startup resistor (R str) : The average of the minimum current supplied through the startup resistor is given by where Vline min is the minimum input voltage, Vstart is the start voltage (15V) of FPS and Rstr is the startup resistor. The startup resistor should be chosen so that Isup avg is larger than the maximum startup current ( 50uA). If not, Vcc can not be charged up to the start voltage and FPS will fail to start up. The maximum startup time is determined as Where Ce is the effective Vcc capacitor ( Ca1+Ca2) and Istart max is the maximum startup current (50uA) of FPS. Once the startup resistor ( Rstr) is determined, the maximum approximate power dissipation in Rstr is obtained as where Vline max is the maximum input voltage, which is specified in STEP-1. The startup resistor should have a proper dissipation rating based on the value of P str. [STEP-9] Determine the wire diameter for each winding based on the RMS current of each output. The RMS current of the n-th secondary winding is obtained as where Dmax and Ids rms are specified in equations (6) and (9), Vo(n) is the output voltage of the n-th output, V F(n) is the diode ( DR(n)) forward voltage drop, VRO is specified in STEP-3 and KL(n) is the load occupying factor for n-th output defined in equation (2). The current density is typically 5A/mm 2 when the wire is long (>1m). When the wire is short with a small number of turns, a current density of 6-10 A/mm 2 is also acceptable. Avoid using wire with a diamet er larger than 1 mm to avoid severe eddy current losses as well as to make winding easier. For high current output, it is recommended using parallel windings with multiple strands of thinner wire to minimize skin effect. Check if the winding wi ndow area of the core, A w (refer to Figure 6) is enough to accomm odate the wires. The required winding window area (Awr) is given by where Ac is the actual conductor area and KF is the fill factor. Typically the fill factor is 0.2~0.25 for single output applications and 0.15~0.2 for multiple outputs applications. If the required window (A wr) is larger than the actual window area (Aw), go back to th e STEP-6 and change the core to a bigger one. Sometimes it is impossible to change the core due to cost or size constrai nts. In that case, reduce V RO in STEP-3 or increase fs min, which reduces the primary side inductance ( Lm) and the minimum number of turns for the primary (Np min) shown in equation (7) and (10). [STEP-10] Choose the proper rectifier diodes in the secondary side based on the voltage and current ratings. The maximum reverse voltage and the rms current of the rectifier diode (DR(n)) of the n-th output are obtained as where KL(n), VDC max, Dmax and Ids rms are specified in equations (2), (4), (6) and (9), respectively, VRO is specified in STEP-3, Vo(n) is the output voltage of the n-th output and VF(n) is the diode ( DR(n)) forward voltage drop. The typical FSCQ-series Rstr Vcc Ca1 Da Isup AC line CDC Ca2 VcoRCC Vz (18V) Isup avg 2V line min⋅ Vstart ⎛⎞ 1 Rstr ⋅= 22() Tstr max Ce Vstart Isup avg Istart max–() Pstr Rstr Vline max ⎛⎞ 2 Vstart

22 Vstart Vline

max⋅⋅ ⋅= 24() I n()sec rms Ids rms 1D max– Dmax VRO KLn()⋅ Awr Ac KF⁄= (26) VDn() Von() VDC max Von() VFn()+()⋅ VRO IDn() rms Ids rms 1D max– Dmax VRO KLn()

average forward current of the diode. maximum reverse recovery time. Table 3. Fairchild Diode Quick Selection Table the voltage and current ripple. F(n) is the diode (DR(n)) forward voltage drop. stages (post filter) to reduce the ripple on the output. [STEP-12] Design the synchronization network. Figure 13. The external capacito r lowers the rising slope of voltage reaches its minimum value as shown in Figure 13.

normal is the Vcc auxiliary voltage in normal mode. output capacitance (Coss+Cr). Figure 14. Typical Feedback Circuit to Drop Output

than 2.5V , which increases the current through the opto LED. switching with a predeter mined peak drain current. where VZB is the zener breakdown voltage of Dz. Figure 15. Burst Operation Waveforms [STEP-14] Design the feedback control circuit. voltage, which is typically 2.5V . Figure 16. Control Block Diagram is specified in STEP-1 and K is specified in equation (38).

©2005 Fairchild Semiconductor Corporation When determining the feedback circuit component, there are some restrictions as described below: (a) Design the voltage divider network of R1 and R2 to provide 2.5V to the reference pin of the KA431. The relationship between R 1 and R2 is given as where Vo1 is the reference output voltage. (b) The capacitor connected to feedback pin (CB) is related to the shutdown delay time in an overload condition by where VSD is the shutdown feedback voltage and Idelay is the shutdown delay current. Typical values for V SD and I delay are 7.5V and 5uA, respectivel y. In general, a 20 ~ 50 ms delay is typical for most applications. Because CB also determines the high frequency pole (wpc) of the compensator transfer function as shown in equation (40), too large a CB can limit the control bandwidth by placing wpc at too low a frequency. Typical value for CB is 10-50nF. (c) The resistors Rbias and RD used together with the opto- coupler H11A817A and the shunt regulator KA431 should be designed to provide proper operating current for the KA431 and to guarantee the full swing of the feedback volt- age for the FPS device chosen. In general, the minimum cathode voltage and current for the KA431 are 2.5V and 1mA, respectively. Therefore, R bias and RD should be designed to satisfy the following conditions. where Vbias is the KA431 bias voltage as shown in Figure 16 and VOP is opto-diode forward voltage drop, which is typically 1V . IFB is the feedback current of FPS, which is typically 1mA.

2.5 R 1⋅

Tdelay VSD 2.5–()=C B⋅ Idelay⁄ (42) Vbias VOP– 2.5– RD VOP Rbias

©2005 Fairchild Semiconductor Corporation 3. Design Example Using FPS Design Assistant - It is assumed that the efficiency is 83% at the minimum input voltage and full load condition. - Since the maximum input power is 101.2W, the DC link capacitor is set to be 220uF by 2uF/Watt. - VRO is set to be 126V so that Vds nom should be about 77% of BVdss Application Device Input Voltag e Output Power Output Voltage (Rated Current) Ripple Spec Color TV FSCQ0765RT 85-265Vac (60Hz) 83W 125V (0.4A) 24V (0.5A) 18V (0.5A) 12V (1.0A) ±5% ±5% ±5% ±5% FPS Design Assistant for AN4146 Ver 1.00 by H.S. Choi Blue cells are the input parameters Red cells are the output parameters 1. Define the system specifications Minimum Line voltage (V line min)8 5 V . r m s Maximum Line voltage (V line max) 265 V.rms Line frequency (f L)6 0 H z Vo(n) Io(n) Po(n) KL(n) 1st output (Vo1) ; regulated by feedback 125 V 0.40 A 50 W6 0 % 2nd output (Vo2) 24 V 0.50 A 12 W1 4 % 3rd output (Vo3) 18 V 0.50 A 9 W1 1 % 4th output (Vo4) 12 V 1.00 A 12 W1 4 % 5th output (Vo5) V A 0 W0 % Maximum output power (P o) = 83.0 W Estimated efficiency (E ff)8 2 % Maximum input power (P in) = 101.2 W 2. Determine DC link capacit or and DC link voltage range DC link capacitor (C DC) 220 uF Minimum DC link voltage (V DC min) = 91 V Maximum DC link voltage (V DC max)= 375 V 3. Determine the reflected output (V RO) Output voltage reflected to primary (V RO) 126 V Maximum nominal Drain voltage (V ds nom) = 501 V

©2005 Fairchild Semiconductor Corporation - Considering the tolerance of 12%, FSCQ0765RT is chosen, whose pulse-by-pulse current limit is 5A (typical). - EER3540 core is chosen, whose cross sectional area is 109mm2. 4. Determine transformer primary side inductance (Lm) Drain voltage falling time (T F)2 . 3 u s Minimum Switching frequency of FPS (f s_min)2 4 k H z Maximum duty cycle (D max) = 0.55 Primary side inductance (L m) = 514 uH Maximum peak drain current (I ds peak) = 4.05 A RMS drain current (I ds rms) = 1.73 A 5. Choose the proper FPS considering the input power and current limit Typical current limit of FPS (ILIM)5 . 0 0 A Minimum ILIM considering tolerance 4.40 A >A ->O.K. 4.05 6. Determine the proper core and the minimum primary turns Maximum flux density swing in normal mode ( ∆ 0.30 T --> Np> 63.69 T Maximum flux density in transient (B sat)0 . 3 8 T --> Np> 62.07 T Cross sectional area of core (A e)1 0 9 m m 2 Minimum primary turns (N p min)= 63.7 T 7. Determine the number of turns for each output and Vcc drop circuit Vo2 in standby mode (Vo2 stby)8 . 0 V Vo2= 24 V in normal mode Vcc auxiliary voltage drop ratio (Kdrop) = 0.37 Minimum Va in standby mode (Va stby)1 3 . 0 V Va in normal mode (Va normal) = 37.7 V VF(n) # of turns Winding for Va (37.7V) 1.2 V 19.7 => 20 T Winding for Vo1 (125V) 1.2 V 64 => 64 T Winding for Vo2 (24V) 1.2 V 12.8 => 13 T Winding for Vo3 (18V) 1.2 V 9.7 => 10 T Winding for Vo4 (12V) 1.2 V 6.7 => 7 T Winding for Vo5 (V) V 0.0 => 0 T Number of turns for primary winding (Np)= 64 T > 63.7 T --->enough turns Ungapped AL value (AL) 3130 nH/T2 Gap length (G) ; center pole gap = 1.04337 mm

©2005 Fairchild Semiconductor Corporation - In standby mode, V o2 is reduced from 24V to 8V . In order to prevent Vcc under voltage lockout in standby mode, V a in standby mode is designed as 13V . Then, Va would be 37.7V in normal mode. -Assuming that the maximum switching frequency is 90kHz, th e maximum current consumed by FPS is 9mA. Vcc resistor is determined as 1.5kΩ. - For each winding, the diameter of wire is determined so that the current density should be about 5A/mm2 - For EER3540 core, the winding window area is 223mm2. Assuming a fill factor of 0.2, this core is enough to accommodate the wires. Maximum operating current of FPS (Iop)6 m A MOSFET input capacitance (Ciss)1 8 4 0 p F Breakdown voltage of Vcc zener diode 18 V Current consummed by FPS (Icc) = 9.0 mA at 90 kHz Vcc drop resistor (Rcc) 1.5 kΩ <2 kΩ Power dissipation of Rcc = 0.3 W 8. Determine the startup resistor Maximum Startup current of FPS (Istart)5 0 u A Startup resistor 240 kΩ <6 1 6 kΩ Effective Vcc capacitor (Ce) 20 uF Maximum dissipation in startup resistor = 0.13 W at 265 Vac Maximum startup time (Tstr max) = 3.83 s at 85 Vac 9. Determine the wire diameter for each winding Diameter Parallel ID(n) rms (A/mm2) Primary winding 0.6 mm × 1 1.7 A6 . 1 Winding for Vcc (37.7V) 0.3 mm × 1 0.1 A1 . 4 Winding for Vo1 (125V / 0.4A) 0.5 mm × 1 0.9 A4 . 8 Winding for Vo2 (24V / 0.5A) 0.4 mm × 2 1.1 A4 . 5 Winding for Vo3 (18V / 0.5A) 0.4 mm × 2 1.1 A4 . 5 Winding for Vo4 (12V / 1A) 0.5 mm × 2 2.2 A5 . 5 Copper area (Ac) = 40.56 mm2 Fill factor (KF)0 . 2 Required window area (Awr) 202.78 mm2

©2005 Fairchild Semiconductor Corporation - Since the output capacitance of MOSFET is 100pF (typical), external capacitor (Cr) of 1nF is used. - Zener diode with a breakdown voltage of 5.1V is chosen. Vcc winding 1N4937 Ultra fast recovery Vo1 (125V) EGP20J (600V/2 A) Ultra fast recovery Vo2 (24V) EGP20D (200V/2A) Ultra fast recovery Vo3 (18V) EGP20D (200V/2A) Ultra fast recovery Vo4 (12V) EGP20D (200V/2A) Ultra fast recovery 10. Choose the rectifier diode in the secondary side VD(n) ID(n) rms Rectifier diode for Vcc 153 V0 . 1 0 A Rectifier diode for Vo1 (125V / 0.4A) 500 V0 . 9 5 A Rectifier diode for Vo2 (24V / 0.5A) 99 V1 . 1 4 A Rectifier diode for Vo3 (18V /0.5A) 75 V1 . 1 2 A Rectifier diode for Vo1 (12V /1A) 51 V2 . 1 7 A Rectifier diode for Vo5 (V /A) 0 V ##### A 11. Determine the output capacitor Co(n) RC(n) Icap(n) ΔVo(n) Output capacitor for Vo1 (125V / 0.4A) 100 uF 100 mΩ 0.9 A0 . 3 V Output capacitor for Vo2 (24V / 0.5A) 1000 uF 100 mΩ 1.0 A0 . 3 V Output capacitor for Vo3 (18V / 0.5A) 1000 uF 100 mΩ 1.0 A0 . 3 V Output capacitor for Vo4 (12V / 1A) 1000 uF 100 mΩ 1.9 A0 . 6 V Output capacitor for Vo5 (V / A) uF mΩ ##### A #### V 12. Design the synchronization network Peak value of Sync voltage (Vsync pk)9 . 0 V 4.6 < Vsync pk < 12V (VOVP) Sync voltage divider resistor (Rsy1)1 5 0 0 Ω Sync voltage divider resistor (Rsy2) 470 Ω Effective output capacitance of MOSFET 1.0 nF ( Coss + Cr ) Sync capacitor (Csy)3 . 9 n F 13. Design voltage drop circuit for the burst operation Vo2 in standby mode (Vo2 stby) 8.0 V Breakdown voltage of zener diode, Dz 5.0 V

©2005 Fairchild Semiconductor Corporation 14. Design the feedback control circuit Control-to-output DC gain = 50 Control-to-output zero (wz) = 100.0 krad/s => fz=H z Control-to-output RHP zero (wrz)= 136.0 krad/s => frz=H z Control-to-output pole (wp)= 82 rad/s => f p=H z Voltage divider resistor (R1)1 0 0 ㏀ Voltage divider resistor (R2)= 2.0 ㏀ Opto coupler diode resistor (RD)1 ㏀ KA431 Bias resistor (Rbias)1 . 2 ㏀ Feeback pin capacitor (CB) = 47 nF Feedback Capacitor (CF) = 22 nF Feedback resistor (RF) = 39 ㏀ Current transfer ratio of opto coupler (CTR) 100 % Feedback integrator gain (wi) = 1273 rad/s => f i=H z Compensator zero (wzc)= 1166 rad/s => f zc=H z Compensator pole (wpc)= 7599 rad/s => f pc= Hz 203 186 1,210 15,924 21,650 vo1 RD iD Rbias ibias CB vFB CTR:1 FPS vo2 CF RF KA431 -60 -40 -20 100 1 10 100 1000 10000 frequency (Hz) Gain (dB) control-to-output Compensator Closed loop gain (T)

©2005 Fairchild Semiconductor Corporation - The control bandwidth (crossover frequency) is about 600Hz with a phase margin of 50 degrees. -180 -150 -120 -90 -60 -30 1 10 100 1000 10000 frequency (Hz) Phase (degree) Control-to-output Compensator Closed loop gain (T)

  • High efficiency (>80% at 85Vac input)
  • Wider load range through the extended quasi-resonant operation
  • Low standby mode power consumption (<1W)
  • Low component count
  • Enhanced system reliability through various protection functions
  • Internal soft-start (20ms) Key Design Notes
  • 24V output is designed to drop to around 8V in standby mode
  • Zener diode ZD102 is used for a safety test such as UL. When the drain pin and feedback pin are shorted, the zener diode fails and remains short, which causes the fuse (F1) to pop and prevents explosion of the opto-coupler (IC301). This zener diode also increases the immunity against line surge. 1. Schematic

Figure 20. Schematic of Design Example

©2005 Fairchild Semiconductor Corporation 2. Transformer Specifications Figure 21. Transformer Schematic Diagram

Electrical Characteristics

Core & Bobbin Core : EER 3540 Bobbin : EER3540 Ae : 109 mm No Pin (s →f) Wire Turns Winding Method Np1 1 - 3 0.6 φ × 1 32 Center Winding N125V/2 16 - 15 0.5 φ × 1 32 Center Winding N24V 18 - 17 0.4 φ × 2 13 Center Winding N12V 12 - 13 0.5 φ × 2 7 Center Winding Np2 3 - 4 0.6 φ × 1 32 Center Winding N125V/2 15 - 14 0.5 φ × 1 32 Center Winding N18V 11 - 10 0.4 φ × 2 10 Center Winding Na 7 - 6 0.3 φ × 1 20 Center Winding Pin Specification Remarks Inductance 1 - 3 514uH ± 5% 1kHz, 1V Leakage Inductance 1 - 3 10uH Max 2 nd all short EER3540 N24V N a N125V /2 N12V N18V Np1 Np2 91 0 N125V /2 N125V/2 Np2 N12V N125V/2 N24V Np1 N18V Na

Figure 30. Measured Efficiency

9/20/05 0.0m 002 © 2005 Fairchild Semiconductor Corporation DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPROATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com by Hang-Seok Choi / Ph. D Power Conversion Team / Fairchild Semiconductor Phone : +82-32-680-1383 Facsimile : +82-32-680-1317 E-mail : hangseok.choi@fairchildsemi.com