AN4142 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Why migrate from revi sion 13 to revision 14 of
- 2 Embedded memory
- 2.1 Flash memory
- 2.1.1 STM32W108xx FLASH bit and register overview
- 2.2 Memory controller
- 2.2.1 STM32W108xx MEM bits and registers overview
- 3 System modules
- 3.1 Resets
- 3.1.1 STM32W108xx RST bits and registers overview
- 3.2 Clocks
- 3.2.1 STM32W108xx CLK o scillators overview
- 3.2.2 STM32W108xx CLK bits and registers overview
- 3.3 System timers
- 3.3.1 STM32W108xx watchdog timer overview
- 3.3.2 STM32W108xx Sleep timer Overview
- 3.3.3 STM32W108xx MAC Timer Overview
- 3.4 Power management
- 3.4.1 STM32W108xx Power Overview
- 4 General-purpose input/output s
- 4.1 Standard General-purpose input/output
- 4.1.1 STM32W108xx GPIO Overview
- 4.2 External interupt
- 4.2.1 STM32W108xx EXTI Overview
- 4.3 Debug management
- 4.3.1 STM32W108xx DBG Overview
- 5 Serial interfaces
- 5.1 STM32W108xx Serial control Overview
- 6 General-purpose timers
peripheral the bit and register naming between them. Regarding the hardware, revisions 13 and 14 of the STM32W108xx datasheet are identical. Revision 14 differs from revision 13 version in terms of documentation level. guideline for STM32W108xx microcontroller applications based on the HAL. This application note applies to the products listed in Table 1. Table 1. Applicable products Table 2. Color coding
AN4142 Why migrate from revision 13 to revision 14 of datasheet STM32W108xx? Doc ID 023458 Rev 1 5/38
1 Why migrate from revision 13 to revision 14 of
datasheet STM32W108xx? The revision 14 of the STM32W108xx datasheet is an updated version of revision 13 of the datasheet that supports the standard naming (clocks oscillators, bits, registers...) used inside the STM32Fxx standard microcontrollers documentations. This revision 14 of the STM32W108xx is an aligned version with the available firmware STM32W108xx_StdPeriph_Lib_V1.0.0. In this version, the missing registers that are used in the old HAL and not documented in the revision 13 of the datasheet are added. In addition the structures for the available registers are re-organized to be compatible with the StdLib and the memory mapping is added for each peripheral.
2 Embedded memory
14 of the STM32W108xx datasheet.
2.1 Flash memory
aligned with the standard naming except for the FLASH control registers (FPEC_CLK_REQ and FPEC_CLK_STAT registers).
2.1.1 STM32W108xx FLASH bit and register overview
Table 3 gives the list of the changes (renaming) made in the FLASH bits and registers. Table 3. FLASH memory bits and registers overview
Table 3. FLASH memory bits and registers overview (continued)
2.2 Memory controller
2.2.1 STM32W108xx MEM bits and registers overview
Table 4 gives the memory controller bits and registers naming. Table 4. Memory controller bi ts and registers overview
3 System modules
13 to revision 14 of the STM32W108xx datasheet.
3.1 Resets
For the RST IP , there are no updates in term for structure but the only updates are related to the bits and registers naming.
3.1.1 STM32W108xx RST bits and registers overview
Table 5 gives the list of the changes (renaming) made in the RST bits and registers. Table 5. RST bits and registers overview
3.2 Clocks
The clock IP is completely updated in term of clock oscillators naming and in term of bits and registers naming.
3.2.1 STM32W108xx CLK oscillators overview
The STM32W108xx integrates four oscillators and to be in line with STM32F families the clocks oscillators naming convention is updated as follows:
- The High frequency RC oscillator (12MHz RC) is renamed by the High Speed Internal clock (HSI).
- The 24 MHz crystal oscillator (24MHz XTAL) is renamed by the High Speed External clock (HSE)
- The 10 KHz RC oscillator (10kHz RC) is renamed by the Low Speed Internal 10 KHz clock (LSI10K)
- The 32.768 KHz crystal oscillator(32kHz XTAL) is renamed by the Low Speed External clock (LSE) Note: The CLK1K clock is generated from the 10 KH z RC oscillator, so this clock is renamed by Low Speed Internal 1 KHz clock (LSI1K).
3.2.2 STM32W108xx CLK bits and registers overview
In the revision 13 of the STM32W108xx datasheet, the clock peripheral is not fully documented:
- The LSI10KCR, LSI1KCR, HSICR, PERIODCR and PERIODSR registers are required to calibrate the internal clocks (HSI and LSI) are missing.
- The HSECR1 register is required to configure the bias trim, the value should be reset to full bias at power up.
- The HSECOMPR register is required to check the 24MHz oscillator comparator outputs status.
- The DITHERCR register is required to enable disable the clock dither.
- The PCTRACECR register is required to select the PC_TRACE source.
- The new name for the SLEEPTMR_CLKEN register is SLEEPCR register; this register is removed from the sleep timer section and added in the clock section. Table 6 gives the list of the changes made in the CLK bits and registers naming.
Table 6. CLK bits and registers overview
3.3 System timers
13 to revision 14 of the STM32W108xx datasheet.
3.3.1 STM32W108xx watchdog timer overview
changes made in the WDG bits and registers naming.
3.3.2 STM32W108xx Sleep timer Overview
and the second one is related to the bits and registers naming.
- The sleep timer force register SLPTMR_IFR is required in low power modes: if the dedicated sleep timer interrupt (WRAP , CMPA or CMPB) is enabled and configured as wake event, in this case the interrupt will not be generated when the CPU
Table 7. WDG bits and registers overview
used to wake up the CPU then force the dedicated interrupt in the sleep timer force register SLPTMR_IFR.
- The Sleep timer clock enables register SLEEPTMR_CLKEN is renamed by the sleep control register CLK_SLEEPCR and moved to the clock section. Table 8 gives the list of the changes made in the Sleep Timer bits and registers.
Table 8. SLPTMR bits and registers overview
3.3.3 STM32W108xx MAC Timer Overview
The MAC Timer IP can be used to measure the timing, this timer is not documented in the revision 13 of datasheet STM32W108xx. Table 9 gives the MAC timer bits and registers mapping.
3.4 Power management
descriptions for this IP are missing in the revision 13 of the STM32W108xx datasheet.
3.4.1 STM32W108xx Power Overview
Table 10 gives the list of the power bits and registers mapping. Table 9. WDG bits and registers overview
2088 Reserved
16/38 Doc ID 023458 Rev 1Table 10. Power bits and registers overview Offset Register Bit[31:16] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STM32W108xx PWR bits/registers naming overview 0x0004 PWR_DSLEE PCR1 Reserved LVFR EEZE Reserved 0x008- 0x0010 Reserved 0x0014 PWR_ DSLEEPCR2 Reserved MODE 0x0018 PWR_ VREGCR Reserved 1V8EN Res. 1V8TRIM Res. 1V2EN Res. 1V2TRIM 0x001C Reserved 0x0020 PWR_ WAKECR1 Reserved CSYSPWR UPREQ CPWRR UPREQ CORE WRAP COMPB COMPA IRQD SC2 SC1 WAKEEN 0x0024 PWR_ WAKECR2 Reserved COREWA KE Reserved 0x0028 PWR_ WAKESR Reserved CSYSPWR UPREQ CPWRR UPREQ CORE WRAP COMPB COMPA IRQD SC2 SC1 GPIOPIN 0x002C- 0x0030 Reserved 0x0034 PWR_CPWR UPREQSR Reserved REQ 0x0038 PWR_CSYSP WRUPREQSR Reserved REQ 0x003C PWR_CSYSP WRUPACKSR Reserved ACK 0x0040 PWR_CSYSP WRUPACKCR Reserved INHIBIT 0x0044 - 0xBC04 Reserved
Table 10. Power bits and registers overview
4 General-purpose input/outputs
- Standard General-purpose input/output : GPIO
- External interrupt: EXTI
- Debug management: DBG The GPIO_PAWAKE, GPIO_PBWAKE, GPIO_PCWAKE and GPIO_WAKEFILT registers are renamed respectively PWR_WAKEPAR, PWR_WAKEPBR, PWR_WAKEPCR and PWR_WAKEFILTR registers. These registers are required to manage the GPIO wake up resources from low power modes and will be presented in the low power mode section.
4.1 Standard General-purpose input/output
This part will contain only the GPIO configurations and status registers.
4.1.1 STM32W108xx GPIO Overview
Table 11 gives the list of the changes (renaming) made in the GPIO bits and registers. Table 11. GPIO bits and registers overview
4.2 External interupt
This part will contain the GPIO external interrupts configurations and status registers.
4.2.1 STM32W108xx EXTI Overview
Table 12 gives the list of the changes (renaming) made in the EXTI bits and registers. Table 12. EXTI bits and registers overview
4.3 Debug management
This part will contain the required registers for the debug mode.
4.3.1 STM32W108xx DBG Overview
The GPIO PC trace control register GPIO_PCTRACECR is added to selects PC trace source on baseband debug GPIO pins. Table 13 gives the list of the changes (renaming) made in the DBG bits and registers. Table 13. WDG bits and registers overview
5 Serial interfaces
- Serial Controller common registers
- Serial peripheral interface registers
- Inter-Integrated circuit registers
- Universal Asynchronous Receiver/Transmitter registers (available for SC1 only)
- Direct memory access registers
5.1 STM32W108xx Serial control Overview
Table 14 gives the list of the changes (renaming) made in the SC bits and registers. Table 14. SC bits and registers overview
6 General-purpose timers
timer interrupts (INT_TIMxCFG, INT_TIMxFLAG and INT_TIMxMISS registers).
6.1 STM32W108xx Timers Overview
Table 15. TIM bits and registers overview
7 Analog-to-digital converter
For the ADC IP , there are no updates in term for structure but the only updates are related to the bits and registers naming.
7.1 STM32W108xx ADC Overview
Table 16 gives the list of the changes (renaming) made in the ADC bits and registers. Table 16. ADC bits an d registers overview
8 Interrupts
8.1 STM32W108xx NVIC Overview
one in the Cortex-M3 programming manual. Table 17. NVIC bits and registers overview
8.2 Management interrupt
The HSE COMP high level and HSE COMP low level interrupts can be managed separately using the management interrupt IP . Table 18 gives the MGMT bits and registers mapping. Table 18. MGMT bits and registers overview
9 Revision history
Table 19. Document revision history 23-Aug-2012 1 Initial release.