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implementing constant current / constant voltage control. the validity of the design procedure. Table 1. FPS lineup for a battery charger Figure 1. Basic Battery charger Using FPS

  1. Step-by-step Design Procedure

Figure 2. Flow chart of design procedure

  • Maximum output power (Po).

min and fL are specified in step-1. Figure 3. DC Link Voltage Waveform

  1. Determine the system specifications
  2. Determine DC link capacitor (CDC)
  3. Determine the reflected output voltage
  4. Determine the proper core and the
  5. Determine the number of turns for each
  6. Determine the wire diameter for each
  7. Choose the proper rectifier diode for each
  8. Determine the output capacitor
  9. Choose proper FPS considering input
  10. Determine the transformer primary side

2 Pin 1D ch–()⋅

turns, a current density of 6-10 A/mm 2 is also acceptable. severe eddy current losses as well as to make winding easier. with multiple strands of thinner wire to minimize skin effect. where Ac is the actual conductor area and KF is the fill factor. side based on the voltage and current ratings. voltage drop in the output current sensing resistor. average forward current of the diode. Table 3. Fairchild Diode quick selection table considering the voltage and current ripple. voltage drop in the output current sensing resistor. post filter at around 1/10~1/5 of the switching frequency. (11) STEP-11 : Design the RCD snubber.

capacitors are unacceptable due to these reasons. Figure 10. Circuit diagram of the snubber network ripple of the selected capacitor voltage is reasonable. respectively and fs is the FPS switching frequency. and Rsn is the snubber resistor. Figure 11. MOSFET drain voltage and snubber max is specified in equation (3).

2 Vsn

discharge of the inductor nor stray capacitance is considered. than the designed value due to this effects. Figure 12. MOSFET drain voltage and snubber capacitor (12) STEP-12 : Design the Control circuit. control circuits shown in Figure 15 should be used. Figure 13. Transistor and KA431 CC/CV control where Vo is the output voltage. full swing of the feedback voltage for the FPS device chosen. Rd should be designed to satisfy the following conditions.

2.5 R 1⋅

are determined as 56Ω and 510Ω, respectively. Figure 14. Current control circuit in detail forward voltage drop, which is typically 1V . and Vsense is determined to be 0.650V . where Io is SMPS output current.

©2003 Fairchild Semiconductor Corporation (36), the resistance of the thermistor at 75 °C to keep the same output current is given by NTC thermistor 103Χ 2 from DSC is chosen for the compen- sation, whose resistance is 10k Ω at 25 °C and 1.92k Ω at 75°C. (b) OP amp and shunt regulator (KA431) scheme Figure 15 shows a 4.2 V , 0.8A CC/CV control circuit using the LM358 dual op amp shunt regulator (KA431). This circuit provides higher accuracy compared with the simple transistor circuit. Power loss is lower and efficiency is better because smaller resistance values can be used for sense resistor R sense. The shunt regulator (KA431) is used as a voltage reference for an accurate control. Constant voltage (CV) control : The Output voltage is sensed by R1 and R2 and then compared by OP amp LM358B to reference of 2.5V . The output of the OP amp drives current through D 2 and R d into the LED of the opto- coupler. The voltage divider network of R1 and R2 should be designed to provide 2.5V to the reference pin of the KA431. The relationship between R 1 and R2 is given by where Vo is the output voltage. By choosing R1 to be 680Ω , R2 is obtained as CF2, RF2, and R6 compensate the voltage control loop. Constant Current (CC) control : The voltage drop across the sensing resistor (Rsense) is given by It is typical to set Vsense as 0.1-0.2V . Since the inverting input of OP amp is virtually grounded, the relationship between R4 and R5 is given by By choosing R5 as 33kΩ, R4 is obtained as 2.1kΩ. C F2, RF2, and R6 compensate the current control loop. 0.508V 0.65V 0.508V– 2.5 680⋅ Vsense IoRsense=3 8 () Vsense R5⋅

Figure 15. CC/CV control using OP amp and shunt regulator

©2002 Fairchild Semiconductor Corporation - Summary of symbols - Aw : Winding window area of the core in mm2 Ae : Cross sectional area of the core in mm2 Bsat : Saturation flux density in tesla. Co : Output capacitor Dmax : Maximum duty cycle ratio Eff : Estimated efficiency fL : Line frequency fs : Switching frequency of FPS Ids peak : Maximum value of peak current through MOSFET at the minimum input voltage condition Ids2 peak : Maximum value of peak current through MOSFET at the maximum input voltage condition Ids rms : RMS current of MOSFET Ids2 : Maximum peak drain current at the maximum input voltage condition. Iover : FPS current limit level. Ise rms : RMS current of the secondary winding ID rms : Maximum rms current of the output rectifier diode Icap rms : RMS Ripple current of the output capacitor Io : Output load current KRF : Current ripple factor Lm : Transformer primary side inductance Llk : Transformer primary side leakage inductance Losssn : Maximum power loss of the snubber network in normal operation Np min : The minimum number of turns for the transformer primary side to avoid saturation Np : Number of turns for primary side winding Ns : Number of turns for the output winding Na : Number of turns for the Vcc winding Po : Maximum output power Pin : Maximum input power Rc : Effective series resistance (ESR) of the output capacitor. Rsn : Snubber resistor RL : Effective total output load resistor of the controlled output Vline min : Minimum line voltage Vline max : Maximum line voltage VDC min : Minimum DC link voltage VDC max : Maximum DC line voltage Vds nom : Maximum nominal MOSFET voltage Vo : Output voltage VF : Forward voltage drop of the output rectifier diode. Vcc * : Nominal voltage for Vcc VFa : Diode forward voltage drop of Vcc winding VD : Maximum voltage of the output rectifier diode VRO : Output voltage reflected to the primary Vsn : Snubber capacitor voltage under minimum input voltage and full load condition Vsn2 : Snubber capacitor voltage under maximum input voltage and full load condition Vds max : Maximum voltage stress of the MOSFET

©2002 Fairchild Semiconductor Corporation ☞The estimated efficiency (Eff) is set to be 0.65, considering the low output voltage and the loss in the current sensing resistor. Design example using FPS Design Assistant ±±±± 5% Ripple spec 5.2V (0.65A)85V-265VAC3.4WFSD210Battery charger Output voltage (Max Current)Input voltageOutput PowerDeviceApplication ±±±± 5% Ripple spec 5.2V (0.65A)85V-265VAC3.4WFSD210Battery charger Output voltage (Max Current)Input voltageOutput PowerDeviceApplication ☞Since the input power is 5.2 W, the DC link capacitor is set to be 9.4uF by 2uF/Watt. (4.7uF××××2) ☞VRO is set to be 70V so that Vds nom would be about 70% of 650V. 1. Define the system specifications1. Define the system specifications1. Define the system specifications1. Define the system specifications Minimum Line voltage (Vline min)8 5 V . r m s Maximum Line voltage (Vline max)2 6 5 V . r m s Line frequency (fL)6 0 H z VVVVo(n)o(n)o(n)o(n) IIIIo(n)o(n)o(n)o(n) PPPPo(n)o(n)o(n)o(n) Output 5.2 V 0.65 A 3333 WWWW Maximum output power (PMaximum output power (PMaximum output power (PMaximum output power (Poooo) =) =) =) =3 . 4 3.43.43.4 WWWW Estimated efficiency (Eff)6 5 % Maximum input power (PMaximum input power (PMaximum input power (PMaximum input power (Pinininin) =) =) =) =5 . 2 5.25.25.2 WWWW 2. Determine DC link capacitor and DC link voltage range2. Determine DC link capacitor and DC link voltage range2. Determine DC link capacitor and DC link voltage range2. Determine DC link capacitor and DC link voltage range DC link capacitor (CDC)9 . 4 u F Minimum DC link voltage (VMinimum DC link voltage (VMinimum DC link voltage (VMinimum DC link voltage (VDCDCDCDC minminminmin) =) =) =) =8 4 848484 VVVV Maximum DC link voltage (VMaximum DC link voltage (VMaximum DC link voltage (VMaximum DC link voltage (VDCDCDCDC maxmaxmaxmax)=)=)=)= 375 375375375 VVVV 3. Determine Maximum duty ratio (Dmax) 3. Determine Maximum duty ratio (Dmax) 3. Determine Maximum duty ratio (Dmax) 3. Determine Maximum duty ratio (Dmax) Output voltage reflected to primary (VRO)= 70 V Maximum duty ratio (Dmax) 0.4560.4560.4560.456 Max nominal MOSFET voltage (VMax nominal MOSFET voltage (VMax nominal MOSFET voltage (VMax nominal MOSFET voltage (Vdsdsdsds nomnomnomnom) =) =) =) =4 4 5 445445445 VVVV 4. Determine transformer primary inductance (Lm)4. Determine transformer primary inductance (Lm)4. Determine transformer primary inductance (Lm)4. Determine transformer primary inductance (Lm) Switching frequency of FPS (fs) 134 kHz Ripple factor (KRF)0 . 6 6 Primary side inductance (LPrimary side inductance (LPrimary side inductance (LPrimary side inductance (Lmmmm) =) =) =) = 1597159715971597 uHuHuHuH Maximum peak drain current (IMaximum peak drain current (IMaximum peak drain current (IMaximum peak drain current (Idsdsdsds peakpeakpeakpeak) =) =) =) =0 . 2 3 0.230.230.23 AAAA RMS drain current (IRMS drain current (IRMS drain current (IRMS drain current (Idsdsdsds rmsrmsrmsrms) =) =) =) =0 . 100.100.100.10 AAAA 63 Maximum DC link voltage in CCM (VMaximum DC link voltage in CCM (VMaximum DC link voltage in CCM (VMaximum DC link voltage in CCM (VDCDCDCDC CCMCCMCCMCCM)))) 143143143143 VVVV I∆ EDCI EDC RF I IK 2 )(1 )(1 CCMK DCMK RF RF

©2002 Fairchild Semiconductor Corporation ☞ Ferrite core EE1616 is chosen (Ae=19.4 mm2) ☞ The voltage drop in the sensing resistor (0.7V) is included in the diode voltage drop of the output diode. ☞ Since the winding for 5.2V is short with small number of turns, relatively large current density (> 5A/mm2) is allowed. 7. Determine the number of turns for each output7. Determine the number of turns for each output7. Determine the number of turns for each output7. Determine the number of turns for each output VVVVo(n)o(n)o(n)o(n) VVVVF(n)F(n)F(n)F(n) # of turns# of turns# of turns# of turns VF : Forward voltage drop of rectifier diode Primary turns (NPrimary turns (NPrimary turns (NPrimary turns (Npppp)=)=)=)= 99999999 TTTT --->enough turns--->enough turns--->enough turns--->enough turns Ungapped AL value (AL) 1150 nH/T2 Gap length (G) ; center pole gap =Gap length (G) ; center pole gap =Gap length (G) ; center pole gap =Gap length (G) ; center pole gap =0 . 130.130.130.13 mmmmmmmm Schottky Barrier DiodeSB260 (60V/2A, VF=0.55V) output (5.2V) Ultra Fast Recovery DiodeUF4003 (200V /1A, VF=1V)Vcc winding Schottky Barrier DiodeSB260 (60V/2A, VF=0.55V) output (5.2V) Ultra Fast Recovery DiodeUF4003 (200V /1A, VF=1V)Vcc winding 5. Choose the proper FPS considering the input power and current limit5. Choose the proper FPS considering the input power and current limit5. Choose the proper FPS considering the input power and current limit5. Choose the proper FPS considering the input power and current limit Typical current limit of FPS (Iover)0 . 3 2 A Minimum IMinimum IMinimum IMinimum Ioveroveroverover considering tolerance of 12% considering tolerance of 12% considering tolerance of 12% considering tolerance of 12% 0.280.280.280.28 AAAA >>>> AAAA 6. Determine the proper core and the minimum primary turns6. Determine the proper core and the minimum primary turns6. Determine the proper core and the minimum primary turns6. Determine the proper core and the minimum primary turns Saturation flux density (Bsat)0 . 3 0 T Cross sectional area of core (Ae) 19.4 mm2 Minimum primary turns (NMinimum primary turns (NMinimum primary turns (NMinimum primary turns (Npppp minminminmin)=)=)=)= 87.8 87.887.887.8 TTTT 0.230.230.230.23 8. Determine the wire diameter for each winding 8. Determine the wire diameter for each winding 8. Determine the wire diameter for each winding 8. Determine the wire diameter for each winding DiameterDiameterDiameterDiameter ParallelParallelParallelParallel IIIID(n)D(n)D(n)D(n) rmsrmsrmsrms (A/mm(A/mm(A/mm(A/mm2222)))) Copper area (ACopper area (ACopper area (ACopper area (Acccc) =) =) =) =3 . 8 4 3.843.843.84 mmmmmmmm2222 Fill factor (KF)0 . 15 Required window area (ARequired window area (ARequired window area (ARequired window area (Awrwrwrwr)))) 25.6225.6225.6225.62 mmmmmmmm2222 9. Choose the rectifier diode in the secondary side9. Choose the rectifier diode in the secondary side9. Choose the rectifier diode in the secondary side9. Choose the rectifier diode in the secondary side VVVVD(n)D(n)D(n)D(n) IIIID(n)D(n)D(n)D(n) rmsrmsrmsrms Vcc diodeVcc diodeVcc diodeVcc diode 80808080 VVVV0 . 100.100.100.10 AAAA 1st output diode1st output diode1st output diode1st output diode 39393939 VVVV 1.181.181.181.18 AAAA

©2002 Fairchild Semiconductor Corporation Since the output voltage ripple exceeds the ripple spec of ±±±± 5%, additional LC filter stage should be used. 330uF capacitor together with 3.9uH inductor are used for the post filter. ☞ The snubber capacitor and snubber resistor are chosen as 1nF and 94k ΩΩΩΩ (47kΩΩΩΩ××××2), respectively. The maximum voltage stress on the MOSFET is below 80% of BVdss (700V) 10. Determine the output capacitor 10. Determine the output capacitor 10. Determine the output capacitor 10. Determine the output capacitor ΔVΔVΔVΔVo(n)o(n)o(n)o(n) CCCCo(n)o(n)o(n)o(n) RRRRC(n)C(n)C(n)C(n) IIIIcap(n)cap(n)cap(n)cap(n) 11. Design RCD snubber11. Design RCD snubber11. Design RCD snubber11. Design RCD snubber Primary side leakage inductance (Llk)5 0 uH Maximum Voltage of snubber capacitor (Vsn) 170 V Maximum snubber capacitor voltage ripple 9 % Snubber resistor (RSnubber resistor (RSnubber resistor (RSnubber resistor (Rsnsnsnsn)=)=)=)= 99.6 99.699.699.6 ㏀㏀㏀㏀ Power loss in snubber resistor (PPower loss in snubber resistor (PPower loss in snubber resistor (PPower loss in snubber resistor (Psnsnsnsn)=)=)=)= 0.3 0.30.30.3 WWWW (In Normal Operation)(In Normal Operation)(In Normal Operation)(In Normal Operation) Peak drain current at VPeak drain current at VPeak drain current at VPeak drain current at VDCDCDCDC maxmaxmaxmax (I (I (I (Ids2ds2ds2ds2) =) =) =) =0 . 2 2 0.220.220.22 AAAA Max Voltage of Csn at VMax Voltage of Csn at VMax Voltage of Csn at VMax Voltage of Csn at VDCDCDCDC max max max max (V(V(V(Vsn2sn2sn2sn2)=)=)=)= 167167167167 VVVV Max Voltage stress of MOSFET (VMax Voltage stress of MOSFET (VMax Voltage stress of MOSFET (VMax Voltage stress of MOSFET (Vdsdsdsds maxmaxmaxmax)=)=)=)= 542542542542 VVVV

©2002 Fairchild Semiconductor Corporation Design Summary

Features

  • High efficiency (>60% at Universal Input)
  • Low power consumption (<100mW at 240Vac) with no load
  • Low component count
  • Enhanced system reliability through various protection functions
  • Internal soft-start (3ms)
  • Frequency Modulation for low EMI Key Design Notes
  • The constant voltage (CV) mode control is implemented with resistors, R8, R9, R10 and R12, shunt regulator, U2, feedback capacitor, C9 and opto-coupler, U3.
  • Even though FSD210 has an internal soft start, C10 is employed to provide longer soft start time. Since C10 reduces the feedback gain, a relatively small resistor is used for R9 in order to compensate it.
  • The constant current (CC) mode control is realized with resistors, R8, R9, R15, R16, R17 and R19, npn transistor, Q1 and NTC, TH1. When the voltage across current sensing resistors, R15,R16 and R17 is 0.7V , the npn transistor turns on and the current through the opto coupler LED increases. This reduces the feedback voltage and duty ratio. Therefore, the output voltage decreases and the output current is kept constant.
  • The NTC (negative thermal coefficient) is used to compensate the temperature characteristics of the transistor Q1.

Figure 16. The final schematic of the flyback converter

Figure 24. Burst mode Waveforms

3/24/04 0.0m 002  2003 Fairchild Semiconductor Corporation DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPROATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com by Hang-Seok Choi / Ph. D Power Supply Group / Fairchild Semiconductor Phone : +82-32-680-1383 Facsimile : +82-32-680-1317 E-mail : hschoi@fairchildsemi.co.kr