AN4073 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Overview of parameters impacting the ADC accuracy
- 2 Firmware techniques for im proving the conversion accuracy
- 2.1 Averaging
- 2.1.1 Averaging of N ADC samples
- 2.1.2 Averaging of N-X ADC samples
- 2.2 Additional recommendation
- 3 STM32F2 and STM32F4 practical measurement s
- 3.1 Measurement conditions
- 3.1.1 Hardware setup
- 3.1.2 Firmware setup
- 3.2 Results
- 3.2.1 ADC measurements when ART is ON
- 3.2.2 ADC measurements when ART is OFF
- 3.2.3 ADC measurements when (Data+Inst ruction) cache ON + prefetch OFF15
- 3.3 Timing considerations
- 3.4 Measurement conclusion
- 4 STM32F4 ADC accuracy opti ons
- 4.1 Configuration options for ADC accuracy
- 4.1.1 Option
- 4.1.2 Option
- 4.2 Practical measurements
- 4.2.1 Hardware Setup
- 4.2.2 Common firmware setup
- 4.2.3 Results
- 4.3 Measurement conclusions
conversions for applications using the STM32F2xx and STM32F4xx microcontrollers. and gives some general tips on writing firmware for better ADC accuracy. in a lab under typical conditions (unless specified otherwise) and not tested in production. Table 1 lists the microcontrollers concerned by this application note. Table 1. Applicable products
Table 4. Distribution of ADC codes when (Dat a+Instruction) cache ON + prefetch OFF
Overview of parameters impacting the ADC accuracy AN4073
1 Overview of parameters impacting the ADC accuracy
The accuracy of an analog to digital conversion has an impact on the overall system quality and efficiency. To improve the accuracy, you need to understand the errors associated with the ADC and the parameters affecting them. The ADC, itself, cannot ensure the accuracy of results. It depends on your overall system design. For this reason, you need to do some careful preparation before starting your development. Many parameters impact the ADC accuracy, depending on the application. Some of these factors are: PCB layout, voltage source, I/O switching and analog source impedance. For more details about ADC errors, please refer to AN2834: How to get the best ADC accuracy in STM32F10xxx devices and to AN3137: A/D converter on STM8L devices application notes.
2 Firmware techniques for improving the conversion
2.1 Averaging
analog input or a wrong conversion.
2.1.1 Averaging of N ADC samples
memory needed to execute a division algorithm (in Cortex-Mx, this takes 1 CPU cycle). Figure 1. Graphical representation of averaging technique
Figure 2. Averaging of N sample algorithm Total conversion time = (number of samples * ADC conversion time) + computation time. average by dividing the total by the number of samples. average, depending on the analog signal variations and the time available for computation. Note: Refer to Appendix A for more details about the code source used.
2.1.2 Averaging of N-X ADC samples
value (or the reverse) and deleting the dispersed X samples. It is recommended to choose N and X as multiples of 2. execution time and the conversion accuracy.
Figure 3. Averaging of N-X ADC sample algorithm Total conversion time = (number of samples * ADC conversion time) + computation time. average by dividing the total by N-X. Note: Refer to Appendix B for more details about the code source used.
Firmware techniques for improving the conversion accuracy AN4073
2.2 Additional recommendation
ADC conversion results are the ratio of the input voltage to the reference voltage. If there is noise in the reference voltage, then the results may not be accurate. Both hardware and firmware design are responsible for reducing the noise. The execution of code generates some non-negligible noise on the internal power supply network of the microcontroller. To filter this noise, the V DDA (or VREF) and VSSA analog supply pins are available on the microcontroller package; you can connect a capacitor filter to these power supply pins to filter a high frequency noise. Here are some general firmware design tips for reducing system noise in order to achieve a better ADC conversion accuracy: 1. Avoid starting transmission on any communication peripheral just before starting the ADC conversion. The toggling of the I/Os may create some noise in the supply voltage. 2. Avoid toggling high-sink I/Os which cause noise ripples in the power supply. 3. Avoid toggling digital outputs on the same I/O port as the A/D input is being converted. This can introduce switching noise into the analog inputs. 4. It is recommended to configure the STM32F2/F4 ART with data cache + Instruction cache enable and to disable the prefetch. This will avoid extra CPU accesses to the Flash memory causing an additional noise which can significantly decrease the ADC accuracy in some applications.
AN4073 STM32F2 and STM32F4 practical measurements
3 STM32F2 and STM32F4 practical measurements
This section only applies to all STM32F2xx, STM32F405, STM32F415, STM32F407 and STM32F417 microcontrollers. This section gives some ADC accuracy measurements, putting the previously described methods into practice.
3.1 Measurement conditions
3.1.1 Hardware setup
STM32F407ZGT6 soldered on a test board (with only a minimum number of other hardware components) Ambient temperature: 25°C 3 power supplies are applied to the MCU: VDD/VSS, VDDA/VSSA, VREF+/VREF- Power supply range: VDD=VDDA=VREF+ = 3.3 V, fADC = 36 MHz Clock source: external clock (8 MHz) provided by a generator, PLL is enabled, fCPU = 144 MHz Three fixed analog input voltages are tested: 0.3 V, 1.65 V and 3 V
3.1.2 Firmware setup
ADC channel 2 is used in single conversion mode 50000 acquisitions were taken for each fixed analog input voltage Five firmware methods were used to examine the ADC converted data: – Raw data (without averaging) – Averaging of 4 ADC samples – Averaging of 6 ADC samples – Averaging of 8 ADC samples – Averaging of 8 ADC samples and deleting the 4 most dispersed samples Note: All tests were done with f ADC = 36 MHz, sampling time = 3 ADC cycles and ADC resolution = 12 bits in order to achieve the fastest ADC conversion (2.4 Msps).
3.2 Results
These measurements have been done based on a characterization of the ADC and are confirmed by further investigations (about 100 tests), where many parameters were evaluated to analyze the impact of each one. The following measurements were considered while evaluating the impact of three different ART configurations on the ADC accuracy: ART ON: (data cache + instruction cache + prefetch) ON ART OFF: (data cache + instruction cache + prefetch) OFF (Data cache + instruction cache) ON + prefetch OFF
occurred the most in the histogram (see Figure 4). Figure 4. Histogram graphical representation versus code dispersion
3.2.1 ADC measurements when ART is ON
Table 2 and Figure 5 show the ADC code distribution when ART is ON. Table 2. Distribution of ADC codes when ART is ON (units in LSB)
- Worst case found in a total of more than 100 tests
Figure 5. Distribution of ADC codes when ART is ON and VIN = 0.3 V
3.2.2 ADC measurements when ART is OFF
Table 3 and Figure 6 show the ADC code distribution when ART is OFF. Table 3. Distribution of ADC codes when ART is OFF (units in LSB)
- Worst case found in a total of more than100 tests
Figure 6. Distribution of ADC codes when ART is OFF and VIN = 1.65 V
3.2.3 ADC measurements when (Data+ Instruction) cache ON+prefetch OFF
(Data+Instruction) cache is ON and prefetch is OFF. Figure 7. Distribution of ADC codes when (D+I) cache ON + prefetch OFF VIN = 0.3 V Table 4. Distribution of ADC codes when (Data+Instruction) cache ON + prefetch OFF
Figure 8. Distribution of ADC codes when (D+I) cache ON + prefetch OFF VIN = 1.65 V Figure 9. Distribution of ADC codes when (D+I) cache ON + prefetch OFF VIN = 3 V
3.3 Timing considerations
(Data+Instruction) cache ON, Prefetch OFF, which results in the best ADC noise immunity.
3.4 Measurement conclusion
internal noise generated by the Flash. accuracy and the required A/D conversion speed. Table 5. Time needed to compute averaging
- Computation = time taken to add the N samples and divide them by N.
- Computation = time taken to sort the 8 ADC samples, delete the 4 dispersed ones, add the other 4
algorithm is based on successive permutation, which is not optimized for speed).
- CPU frequency is 144 MHz, as described in Section 3.1.1.
STM32F4 ADC accuracy options AN4073
4 STM32F4 ADC accuracy options
This section only applies to STM32F42x/F43x microcontrollers. Before describing the STM32F42x and STM32F43x ADC evaluation results, the silicon configurable options embedded on these products to enhance the ADC accuracy will be detailed.
4.1 Configuration opti ons for ADC accuracy
By default, on these products, noise filtering techniques are activated internally between the ADC analog block and other microcontroller blocks. These techniques will reduce the power supply noise, the signal crosstalk and the EMI-induced noise. For more details about practical ADC results in this condition, please refer to section 4.2.3. To further improve the ADC accuracy, two configurable options are available. The following names are used throughout the document: Default: The default STM32 configuration which is always active out of reset. Option 1: The first configurable option which can be activated by firmware. Option 2: The second configurable option which can be activated by firmware.
4.1.1 Option 1
This option can be activated or not by firmware. By default, it is not active. When activated by firmware, it continuously masks the extra flash access generated by the prefetch mechanism which can produce random noise impacting the ADC accuracy. This could be activated by setting the ADCDC1 (bit 13) in the PWR_CR register. Warning: This bit can only be set at the following conditions: - Prefetch must be OFF. - VDD voltage ranges from 2.4 V to 3.6 V. - This bit must not be set when the ADCxDC2 bit in SYSCFG_PMC register is set. For more details about the exact firmware sequence to enable Option 1, please refer to Section C.1: Option 1. The ADC accuracy results when activating this option, will be detailed in next section.
4.1.2 Option 2
This option can be activated or not by firmware. By default, it is not active. When activated by firmware, it masks the internal flash noise during the last ADC sampling cycle. This will improve the ADC immunity versus internal spurious flash noise.
- Minimum ADC clock is 30MHz.
- ADC resolution should be equal to 12 bits.
flexibility to enable or not this option for each ADC separately. The ADC accuracy when activating this option will be detailed in the next section.
4.2 Practical measurements
Table 6. ADCxDC2 usage versus ADC mode
- When two or three ADCs are activated separately and each one is configured in single mode, only one ADCxDC2 bit
- Some or all ADCxDC2 bits could be used in case the same sampling time is used for all ADCs.
- Some or all ADCxDC2 bits could be used in case the start of conversion triggers are controlled to set up an interval
between each ADC end of sampling equal to or greater than 15 ADC cycles.
4.2.1 Hardware Setup
Section 3.1.1: Hardware setup, with the use of STM32F43x.
4.2.2 Common firmware setup
4.2.3 Results
- ADC measurements when ART is ON
Table 7. Distribution of ADC codes when ART is ON
0.3 V 7 0%
- Option 1 is not applicable since Prefetch is ON in this case.
1.65 V 9 0% 6 0%
Figure 10. Distribution of ADC codes when ART is ON and VIN = 0.3 V (refer to Table 2) while, in this case, the maximum dispersion is 9 LSB. about 75 % when Option 2 is active.
- ADC measurements when ART is OFF
different conditions: Default STM32 configuration, Option 1 and Option 2 are active. Table 8. Distribution of ADC codes when ART is OFF
0.3 V 9 0% 5 0% 5 0%
1.65 V 10 0% 7 0% 7 0%
Figure 11. Distribution of ADC codes when ART is OFF and VIN = 1.65 V to Table 3) while, in this case, the maximum dispersion is 10 LSB. about 75 % when one of the options is active.
- ADC measurements when (Data+Instruction) cache ON + Prefetch OFF
Option 1 and Option 2 are active. Table 9. Distribution of ADC codes when (Data+Instruction) cache ON + prefetch OFF
5 LSB
0.3 V 7 0% 4 0% 4 0%
1.65 V 8 0% 6 0% 6 0%
about 75 % when one of the options is active. Figure 12. Distribution of ADC codes when (D+I) cache ON + Prefetch OFF VIN=0.3 V
AN4073 STM32F4 ADC accuracy options
4.3 Measurement conclusions
Based on these measurements and comparing to STM32F2xx and STM32F405/F415/F407/ F417 measurements, we can conclude that ADC accuracy options embedded on these products allow an improvement of the ADC code dispersion up to 75 %. For the applicable products, you can choose either to work with the default configuration or to enable one of the options; It depends on the ADC precision required by the application. Based on these typical measurements, to achieve the best ADC accuracy with these products, you need to know that: For the Default configuration: Prefetch OFF + Data cache ON + Instruction cache ON gives a maximum of 8 codes of dispersion. When activating Option 1: Prefetch OFF + Data cache ON + Instruction cache ON gives a maximum of 6 codes of dispersion. When activating Option 2: Prefetch ON + Data cache ON + Instruction cache ON gives a maximum of 6 codes of dispersion. However, Options 1 and 2 should only be applied in specific conditions as detailed above (refer to Section 4.1) to avoid any MCU malfunction.
Averaging of N ADC samples: source code AN4073 Appendix A Averaging of N ADC samples: source code /** * @brief Get the average of N ADC samples * @param Numbre of ADC samples to be averaged * @retval The average value uint16_t ADC_GetSampleAvgN(uint8_t N) uint32_t avg_sample =0x00; uint16_t adc_sample[8]={0,0,0,0,0,0,0,0}; uint8_t index=0x00; /* Get the N ADC samples */ for (index=0x00; index<N; index++) /* ADC start conv */ ADC_SoftwareStartConv(ADC1); /* Wait end of conversion */ while(ADC_GetFlagStatus(ADC1,ADC_FLAG_EOC) == RESET); /* Store ADC samples*/ adc_sample[index] = ADC_GetConversionValue(ADC1); /* Add the N ADC samples */ for (index=0; index<N; index++) avg_sample += adc_sample[index]; /* Compute the average of N ADC samples */ avg_sample /= N; /* Return average value*/ return avg_sample;
AN4073 Averaging of N-X ADC samples: source code Appendix B Averaging of N-X ADC samples: source code /** * @brief Get the average of N-X ADC samples * @param Numbre of ADC samples to be averaged * @param Numbre of ADC samples to be averaged * @retval The average value uint16_t ADC_GetSampleAvgNDeleteX(uint8_t N , uint8_t X) uint32_t avg_sample =0x00; uint16_t adc_sample[8]={0,0,0,0,0,0,0,0}; uint8_t index=0x00; for (index=0x00; index<N; index++) /* ADC start conv */ ADC_SoftwareStartConv(ADC1); /* Wait end of conversion */ while(ADC_GetFlagStatus(ADC1,ADC_FLAG_EOC) == RESET); /* Store ADC samples */ adc_sample[index] = ADC_GetConversionValue(ADC1); /* Sort the N-X ADC samples */ Sort_tab(adc_sample,N); /* Add the N ADC samples */ for (index=X/2; index<N-X/2; index++) avg_sample += adc_sample[index]; /* Compute the average of N-X ADC sample */ avg_sample /= N-X; /* Return average value */ return avg_sample; /**
Averaging of N-X ADC samples: source code AN4073 * @brief Sort the N ADC samples * @param ADC samples to be sorted * @param Numbre of ADC samples to be sorted * @retval None void Sort_tab(uint16_t tab[], uint8_t lenght) uint8_t l=0x00, exchange =0x01; uint16_t tmp=0x00; /* Sort tab */ while(exchange==1) exchange=0; for(l=0; l<lenght-1; l++) if( tab[l] > tab[l+1] ) tmp = tab[l]; tab[l] = tab[l+1]; tab[l+1] = tmp; exchange=1;
AN4073 Firmware sequence to activate Option 1 and Option 2 Appendix C Firmware sequence to activate Option 1 and Option 2 C.1 Option 1 /** * @brief Enables or disables the ADC Option_1 configuration. * @param NewState: new state of the ADCDC1 bit. * This parameter can be: ENABLE or DISABLE. * @retval None void SET_ADCOption1 (FunctionalState NewState) /* ENABLE PWR clock */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR,ENABLE); if (NewState != DISABLE) /* Set ADCDC1 bit */ PWR->CR |= ((uint32_t)PWR_CR_ADCDC1); else /* Reset ADCDC1 bit */ PWR->CR &= (uint32_t)(~PWR_CR_ADCDC1);
Firmware sequence to activate Option 1 and Option 2 AN4073 C.2 Option 2 /** * @brief Enables or disables the ADCx Option_2 configuration. * @param ADCxDC2: The ADCxDC2 bit to be used. * This parameter can be one of the following values: * @arg SYSCFG_PMC_ADCxDC2: All ADCxDC2 bits * @arg SYSCFG_PMC_ADC1DC2: ADC1DC2 bit * @arg SYSCFG_PMC_ADC2DC2: ADC2DC2 bit * @arg SYSCFG_PMC_ADC3DC2: ADC3DC2 bit * @param NewState: new state of the ADCxDC2 bit. * This parameter can be: ENABLE or DISABLE. * @retval None void SET_ADCOption2 (uint32_t ADCxDC2, FunctionalState NewState) /* Enable the SYSCFG clock*/ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG,ENABLE); if (NewState != DISABLE) /* Set the ADCxDC2 */ SYSCFG->PMC |= (uint32_t)ADCxDC2; else /* Reset the ADCxDC2 */ SYSCFG->PMC &=(uint32_t)(~ADCxDC2);
Revision history
Table 10. Document revision history 19-Mar-2012 1 Initial release. 21-Mar-2012 2 Inserted missi ng text on page 9. dedicated to STM32F42x/F43x products.