AN4039

AN4039 Freescale-Semiconductor,-Inc | Alldatasheet

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© 2010 Freescale Semiconductor, Inc. All rights reserved. This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC and QorIQ processor reference manuals. The applicable device reference manual defines the function of each field in the programmable registers. This document focuses on why and when to select certain configurations of the register bits and fields to achieve efficient DDR programming. To obtain a comprehensive understanding of the memory controller functionality and the basic operation of the DDR3 memory, see the following recommended documentation:

• Applicable reference manual  Applicable device errata  Processor revision conversion guides (if applicable)  Manufacturer data sheet on the memory selected Many of the PowerQUICC documents are available at the Freescale website listed on the back cover of this document. Document Number: AN4039 Rev. 2, 09/2010

Contents

DDR3 SDRAM Controller Register Setting Considerations by Networking and Multimedia Group Freescale Semiconductor, Inc. Austin, TX

PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations, Rev. 2

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1 Configuration Guidelines

When selecting values for the memory controller registers, use the following steps: 1. Obtain the data sheet for the DDR SDRAM chip (or DIMM) used. 2. Using the values provided in the DDR data sheet, configure the register values per corresponding parameters. Values can be stated in the following ways in the DDR data sheet: — As the number of memory clocks, and it can be directly used for configuring the registers — In units of fractions of a second, and the valu e must be divided by the memory clock period to obtain the number of clocks. If the memory frequency clock is lower than the DDR data sheet rating, the actual memory frequency should be used to calculate the memory clock period. For example, if a DDR3-1067 data sheet provides a value of 15 ns for a given parameter (for example tRP min = 15 ns), and the memory clock operates at 333.5 MHz (or a data rate of

667 Mbps), then the number of clocks is calculated by first finding the operating memory

period (1/333.5 MHz = 3.0 ns) and next dividing the value by period 15 ns/3.0 ns = 5 clk. As indicated, a higher-rated memory can operate in lower frequencies. The DDR3-1067 is a common DDR3 memory, but per the JEDEC specification, DDR3-1067 (or any other JEDEC-compliant DDR3 DRAM) can operate at a data rate down to 600 Mbps. 3. Set the remaining memory register settings as specified in the applicable device reference manual and per additional information provided in this application note. Based on the most commonly observed user-error in the memory controller register setting for DDR3, special attention must be paid to the following items:  Selecting and validating the following fields: — DDR_SDRAM_CLK_CNTL[CLK_ADJUST] — DDR_WRLVL_CNTL[WRLVL_START] — TIMING_CFG_5[R/WODT_ON, R/WODT_OFF]  Selecting and verifying CAS latency, write latency, and additive latency  Confirming that all DDR mode register values match DDR controller configuration registers, especially the CAS latency, additive latency, burst type and write recovery settings  V erifying whether the registered or unbuffered DIMMs are used  V erifying the minimum value of 4 clock cycles are observed for the tWTR, tRRD, and tRTP fields 4. Disable the clocks that are not used via the DDRCLKDR register. By default, all clocks are operational, but not all clock signals are used in a given application. Therefore, by disabling the unused clocks, it first lowers the power consumption and then lowers the unused switching activity in the part. DDRCLKDR is not a part of the memory controller register set; it is located in the global utility register section.

Table 1 lists the memory controller programmable registers in this document. Table 1. Summary of Register Settings

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2 Register Definitions

This section describes the registers and settings discussed in this application note.

2.1 Chip-Select n Memory Bounds Register (CSn_BOUNDS)

are based on the size, and starting and ending values of selected memory. Table 2 describes the CSn_BOUNDS register fields. Figure 1. Chip-Select n Memory Bounds Register (CS n_BOUNDS) Table 2. CSn_BOUNDS Register Field Descriptions 0x9_C000_0000, which is represented by 0x9C0 in this field. than the “starting address + DRAM size,” it works, but the unassigned memory space remains unused. unassigned memory space remains unused.

2.2 Chip-Select Configuration Register (CS n_CONFIG)

sets the number of row and column bits used for this chip-select. Table 3 describes the CS_n CONFIG register fields. Figure 2. Chip-Select Configuration Register (CS n_CONFIG) Table 3. CS_n CONFIG Register Field Descriptions

2 INTLV_EN Memory controller interleave enable

bit to enable interleaving between the two or four memory controllers. Interleaving for PowerQUICC and QorIQ Processors (AN3939).

8 AP_ n_EN Chip-select n auto-precharge enable

interval field (DDR_SDRAM_INTERVAL[BSTOPRE] = 0) are cleared. DDR_SDRAM_INTERVAL[BSTOPRE]).

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2.3 Chip-Select n Configuration 2 Register (CS n_CONFG_2)

The chip-select n configuration 2 register (CSn_CONFG_2) is shown in Figure 3. see the Micron technical note “tn_41_08” available on their website. Micron technical note “tn_41_08” available on their web site. sheet. For DDR3, eight banks are typically selected. The number of rows is obtained from the memory manufacturer’s data sheet. The number of columns is obtained from the memory manufacturer’s data sheet. Figure 3. Chip-Select n Configuration 2 Register (CS n_CONFG_2) Table 3. CS_n CONFIG Register Field Descriptions (continued)

Table 4 describes the CSn_CONFG_2 register fields.

2.4 DDR SDRAM Timing Configuration 3 Register (TIMING_CFG_3)

of clock cycles between various SDRAM control commands. Table 4. CSn_CONFG_2 Register Field Descriptions DDR2 and DDR3 if the option is available in DRAM. Multiplexing.” For exact selection of values for this field, see the memory manufacturer’s data sheet.

000 Full array

001 Half array (BA[2:0] = 000,001, 010, and 011)

010 Quarter array (BA[2:0] = 000, and 001)

Figure 4. DDR SDRAM Timing Configuration 3 Register (TIMING_CFG_3)

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Table 5 describes the TIMING_CFG_3 register fields. Table 5. TIMING_CFG_3 Register Field Descriptions

7 EXT_ACTTOPRE Extended activate to precharge interval (tRAS)

precharge. Note that a 5-bit value of 0_0000 is the same as a 5-bit value of 1_0000. Both values represent 16 cycles.

19 EXT_CASLAT Extended MCAS latency from READ command

specific. typical value is 0.

2.5 DDR SDRAM Timing DDR SDRAM Timing Configuration 0

of clock cycles between various SDRAM control commands. Table 6 describes the TIMING_CFG_0 register fields. Figure 5. DDR SDRAM Timing Configuration 0 Register (TIMING_CFG_0) Table 6. TIMING_CFG_0 Field Descriptions  CL is the CAS latency rounded up to the next integer.  WL is the programmed write latency. resolve a contention if one is encountered. This field is usually cleared.  CL is the CAS latency rounded down to the next integer.  WL is the programmed write latency. contention if one is encountered. This field is usually cleared. chip selects. Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, 5 cycles is the default. This field is usually cleared.

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2.6 DDR SDRAM Timing Configuration 1 Register (TIMING_CFG_1)

of clock cycles between various SDRAM control commands. chip selects. Extra cycles can be added with this field. Note: If 8-beat bursts are enabled, 4 cycles is the default. This field is usually cleared. For DDR3, this field should be set to tXP value.  If DDR_SDRAM_MODE[PD] = 0 (Slow power down), set this field to tXDLL.  If DDR_SDRAM_MODE[PD] = 1 (Fast power down), set this field to tXP . For DDR3, this field should be set to 3’b001. This field should be based on tMRD. Figure 6. DDR SDRAM Timing Configuration 1 Register (TIMING_CFG_1) Table 6. TIMING_CFG_0 Field Descriptions (continued)

Table 7 describes the TIMING_CFG_1 register fields. Table 7. TIMING_CFG_1 Field Descriptions the best possible performance. This field should be based on tRAS. This field should be based on tRCD. TIMING_CFG_3[EXT_REFREC] should be used to accommodate the difference. corresponding field in DDR_SDRAM_MODE[SDMODE]. This field should be based on tRRD. The minimum value for this field is 4 clock cycles.

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2.7 DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2)

The DDR SDRAM timing configuration 2 register (TIMING_CFG_2) is shown in Figure 7. Table 8 describes the TIMING_CFG_2 register fields. Figure 7. DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2) Table 8. TIMING_CFG_2 Register Field Descriptions Additive latency (AL) can be used to make commands and data buses efficient. can improve efficiency. For DDR3, AL can be selected to be CL –1 or CL –2. memory is expected to be received back and recognized in the memory controller. complete understanding of the CPO value and its calculation. controller automatically determines a correct CPO value for each byte lane. same value applies to all byte lanes. frequency-dependent and provided in the manufacturer’s data sheet.

controller automatically adds to AL to meet the relevant timing requirement. CLK_ADJUST change, a timing skew is added between MCK and DQS. This field should be based on tCKE. This field should be based on tFAW. Table 8. TIMING_CFG_2 Register Field Descriptions (continued)

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2.8 DDR SDRAM Control Configuration Register

The DDR SDRAM control configuration register (DDR_SDRAM_CFG) is shown in Figure 8. Table 9 describes the DDR_SDRAM_CFG register fields. Figure 8. DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) Table 9. DDR_SDRAM_CFG Register Field Descriptions

0 MEM_EN DDR SDRAM interface logic enable

1. Perform POR or an HRESET . From assertion of HRESET , MCKE = 0 until MEM_EN is set.
2. Assert the DDR3 DRAM reset signal. Assertion of DRAM reset can be done with HRESET
3. Wait 200 μs before deasserting DRAM reset.
4. Write all DDR registers in memory controller as described in the applicable device reference

manual and in this application note, except for MEM_EN bit.

1. Wait 500 μs. All DDR registers except the MEM_EN bit must be set before this 500- μs wait.
2. Set MEM_EN = 1. This causes the memory controller to perform the initialization sequence.
3. Once the initialization sequence is complete, the memory controller is ready for normal

1 SREN Self refresh enable

2 ECC_EN ECC enable

must be set to ensure an interrupt is generated. 0 No ECC errors are reported. No ECC interrupts are generated. (ECC is disabled).

3 RD_EN Registered DIMM enable

and 3T timing is not allowed, these fields should be cleared, which means 1T timing should be used. controller of the type of memory with which it is to communicate.

10 DYN_PWR Dynamic power management mode

0 Dynamic power management mode is disabled. SDRAM CKE signal is negated. 0 4-beat bursts are used on the DRAM interface. 1 8-beat bursts are used on the DRAM interface.  If a 32-bit data bus is used, then this field should be set to 1 (8-beat burst).  If a 16-bit data bus option is available and used, this field should be set to 1 (8-beat burst).  This field should be set to 1 (8-beat burst).

14 NCAP Non-concurrent auto-precharge

is supported, this bit should be cleared. Table 9. DDR_SDRAM_CFG Register Field Descriptions (continued)

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If more than one chip-select is used, bank interleaving can be enabled. DRAM chips are used. Each data byte has a dedicated corresponding data strobe. DQ[56:63], and DQS8 is used to capture ECC[0:7]. DQS6 for DQ[48:55], DQS7 for DQ[56:63], and DQS8 is used to capture ECC[0:7]. DQ[0:31], DQS4 is used to capture DQ[32:63], and DQS8 is used to capture ECC[0:7].

27 PCHB8 Precharge bit 8 enable

0 MA[10] is used to indicate the auto precharge and precharge all commands. 1 MA[8] is used to indicate the auto precharge and precharge all commands.

28 HSE Global half-strength override

set based on the selection HSE field. The half-strength drive load value is 40 Ω when DDR3 is used.

30 MEM_HALT DDR memory controller halt

When this field is set. the memory controller does not accept a new transaction until it is cleared. EXTENDED MODE REGISTER SET commands through software.

31 BI Bypass initialization

0 The DDR controller cycles through initialization routine based on SDRAM_TYPE.

2.9 DDR_SDRAM_CFG_2

The DDR SDRAM control configuration register 2 (DDR_SDRAM_CFG_2) is shown in Figure 9. Table 10 describes the DDR_SDRAM_CFG_2 fields. Figure 9. DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2) Table 10. DDR_SDRAM_CFG_2 Field Descriptions

0 FRC_SR Force self refresh

0 The DDR controller operates in normal mode

1 The DDR controller enters self-refresh mode.

2 DLL_RST_DIS DLL reset disable

be disabled by setting this bit during initialization. 0 The DDR controller issues a DLL reset to the DRAMs when exiting self refresh.

1 The DDR controller does not issue a DLL reset to the DRAMs when exiting self

9–10 ODT_CFG ODT configuration refers to the termination at the on-chip I/O (memory controller side). This field should be set to assert ODT to internal IOs only during reads to DRAM.

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can leave pages open longer before closing them and starting the refresh sequence. This field refers to the number of refreshes to be issued each refresh sequence. Therefore, if 8 is set, 8 consecutive refreshes are issued at each refresh sequence. longer than system can tolerate), it would cause a system failure. must be cleared if quad-ranked DIMM is not used. On-the-fly burst chop configuration. programmed into TIMING_CFG_0 and TIMING_CFG_4. correct termination refer to the applicable device design checklist. Table 10. DDR_SDRAM_CFG_2 Field Descriptions (continued)

2.10 DDR SDRAM Mode Configuration Register

As specified in the JEDEC standard, every DDR3 SDRAM has a mode and an extended mode register. extended mode provided applies only to DDR3 SDRAM. Table 11 describes the DDR_SDRAM_MODE fields.

27 D_INIT DRAM data initialization

Figure 10. DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE) Table 11. DDR_SDRAM_MODE Field Descriptions register to provide the same data that was originally written to it.

01 Select the

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3 ESDMODE

0 Enables the output

1 Disables the output

0 Default value

4 ESDMODE

8 ESDMODE

This field determines the DRAM on-die-termination value when DRAM ODT is enabled. TIMING_CFG_5 are used to determine when DRAM ODT is turned on or off. is used to determine when the ODT will be enabled and for how long it is applied. This value should be identical to the value selected for SDRAM_TIMING_2[ADD_LA T].

00 Disabled

01 CL-1

10 CL-2

Depends upon system topology and frequency. There are two selections available. systems (that is, one or two ranks) half drive strength may be used.

15 ESDMODE

to synchronize the internal and external clocks in DDR3 DRAMs.

18 SDMODE Reserved 0 Default value

19 SDMODE

0 Slow PD exit

1 F a s t P D e x i t

23 SDMODE

0 Disable the

24 SDMODE Reserved 0 Default value

DRAM data sheet should be consulted to select the proper CAS latency value. Table 11. DDR_SDRAM_MODE Field Descriptions (continued)

2.11 DDR SDRAM Mode Configuration 2 Register

As specified in the JEDEC standard, every DDR3 SDRAM has a mode register 2 and 3 (MR2 and MR3). extended mode provided here applies only to DDR3 SDRAM. Table 12 describes the DDR_SDRAM_MODE_2 fields.

28 SDMODE

0 Sequential

Figure 11. DDR SDRAM Mode Configuration 2 Register (DDR_SDRAM_MODE_2) Table 12. DDR_SDRAM_MODE_2 Field Descriptions this register to provide the same data that was originally written to it.

10 Select the

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2.12 DDR SDRAM Interval Configuration Register

The DDR SDRAM interval configuration register (DDR_SDRAM_INTERV AL) is shown in Figure 12. place. Simply setting a value for this field will enable this feature in the DDR3 DRAMs.

00 Rtt_wr disabled

01 RZQ/4

10 RZQ/2

11 Reserved

8 ESDMODE2

correspond to operation in 0 C to 85 C degrees.

9 ESDMODE2

to set this field. Default value of 0 corresponds to SRT default value. to select the proper CWL value. this register to provide the same data that was originally written to it.

11 Select the

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Figure 12. DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL) Table 12. DDR_SDRAM_MODE_2 Field Descriptions (continued)

Table 13 describes the DDR_SDRAM_INTERV AL fields.

2.13 DDR SDRAM Clock Register (DDR_SDRAM_CLOCK_CNTL)

The DDR SDRAM clock register (DDR_SDRAM_CLOCK_CNTL) is shown in Figure 13. Table 14 describes the DDR_SDRAM_CLOCK_CNTL fields. Table 13. DDR_SDRAM_INTERVAL Field Descriptions by using tREFI in the DRAM specifications, which may depend upon the operating temperature of the DRAM. cycles stated by this field. Figure 13. DDR SDRAM Clock Register (DDR_SDRAM_CLOCK_CNTL) Table 14. DDR_SDRAM_CLOCK_CNTL Field Descriptions not changed to match the CLK_ADJUST change, an offset is added between MCK and DQS.

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2.14 Configuration 4 Register (TIMING_CFG_4)

number of clock cycles between various SDRAM control commands. Table 15 describes the TIMING_CFG_4 fields. Figure 14. DDR SDRAM Timing Configuration 4 Register (TIMING_CFG_4) Table 15. TIMING_CFG_4 Field Descriptions 1–3 RWT Read-to-write turnaround for same chip select. 4–7 WRT Write-to-read turnaround for same chip select. 8–11 RRT Read-to-read turnaround for same chip select. This field specifies how many cycles are added between reads to the same chip select. selected, then this field should be cleared. 12–15 WWT Write-to-write turnaround for same chip select. This field specifies how many cycles are added between writes to the same chip select. selected, then this field should be cleared. minimum requirement for DDR3.

2.15 DDR SDRAM Timing Configuration 5 Register (TIMING_CFG_5)

number of clock cycles between various SDRAM control commands. Table 16 describes the TIMING_CFG_5 fields. Figure 15. DDR SDRAM Timing Configuration 5 Register (TIMING_CFG_5) Table 16. TIMING_CFG_5 Field Descriptions the read cycle is not used, this field should be cleared.

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2.16 DDR ZQ Calibration Control Register (DDR_ZQ_CNTL)

controls required for ZQ calibration. Table 17 describes the DDR_ZQ_CNTL fields. on-the-fly burst chop mode value of 4 clock cycles should be selected for this field. Figure 16. DDR ZQ Calibration Control (DDR_ZQ_CNTL) Table 17. DDR_ZQ_CNTL Field Descriptions 0 ZQ_EN ZQ Calibration enable. can conduct the calibration. 4–7 ZQINIT POR ZQ calibration time (tZQinit). This field should be based on tZQinit. 12–15 ZQOPER Normal operation full calibration time (tZQoper). This field should be based on tZQoper. Table 16. TIMING_CFG_5 Field Descriptions (continued)

2.17 DDR Write Leveling Control Register (DDR_WRLVL_CNTL)

Table 18 describes the DDR_WRLVL_CNTL fields. 20–23 ZQCS Normal operation short calibration time (tZQCS). This field should be based on tZQCS. Figure 17. DDR Write Leveling Control Register (DDR_WRLVL_CNTL) Table 18. DDR_WRLVL_CNTL Field Descriptions

0 WRL VL_EN Write leveling enable

5–7 WRLVL_MRD First DQS pulse rising edge after margining mode is programmed (tWL_MRD). This field should be based on tWL_MRD. Table 17. DDR_ZQ_CNTL Field Descriptions (continued)

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2.18 DDR Control Words n Register (DDR_SDRAM_RCW_n)

1. The DDR3 registered DIMMs are used (that is, DDR_SDRAM_CFG[RD_EN] = 1)
2. The default values of the register control word s in the DDR3 registered DIMMs are not sufficient

or acceptable for customer-specific application. DDR_SDRAM_RCW_n registers into the corresponding DDR3 DIMM register control words. JEDEC-predefined, and RCW 6, 7, and 12–16 are reserved and could contain vendor-specific information. than a JEDEC timing requirement. DQS/DQS delay after margining mode is programmed (tWL_DQSEN). This field should be based on tWL_DQSEN. should be programmed to (tWLO + 6 clk) cycles. Table 18. DDR_WRLVL_CNTL Field Descriptions (continued)

PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations, Rev. 2 Freescale Semiconductor 29 Register Definitions

2.19 DDR Write Leveling Control 2 or 3 Register

(DDR_WRLVL_CNTL_2 or 3) If available, the DDR write leveling control 2 or 3 register sets adjustment for the DQS for each of the byte lanes individually. In memory controllers where these registers are available, each byte lane can be programmed to have a corresponding start delay for the very first write to the DDR3 DRAM. When write leveling is enabled the first write is used, during the initialization, in determining the skews introduced because of fly-by topology. In memory controllers where these registers are not available, the value in DDR_WRLVL_CNTL[WRLVL_START] will be used for the very first write in all the byte lanes. 2.20 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE_3...8) If available, DDR_SDRAM_MODE_ 3...8 are is a set of six registers used to load the mode configuration values for each individual chip select. This register is useful when different termination values (or perhaps other parameters) are desired for each individual chip select. For controller to use these registers to individually program each chip select DDR_SDRAM_CFG_2[UNQ_MSR_EN] should be set. Caution needs to be practiced not to set the common parameters (such as CAS_LA T) to different values. If this register is not available or not used, the DDR_SDRAM_MODE register will be used to program mode register in all chip selects.

2.21 DDR Control Driver Register 1 (DDRCDR_1)

DDR control driver register 1 (DDRCDR_1), shown in Figure 18, is used for the configuration of the driver strengths and on-die-termination (ODT) in the memory controller. The list of available driver strengths are provided in the applicable device reference manual. The user can directly select and set an impedance driver from the list by writing to software driver calibration to override. Or use calibration to select an impedance driver that matches the value of resistors connected to MDIC[0:1] pins. Calibrate the impedance values by using one of the following methods: 1. Hardware calibration is done automatically by the memory controller during the initialization period by setting DHC_EN = 1. All DDR I/Os are set to the same calibrated value. 2. Software calibration is achieved by following the procedure in the applicable device reference manual. Both hardware and software calibrations use the same process, but the hardware calibration is done automatically and software calibration is done by writing the software. The software calibration process must be done before the memory controller is enabled (that is, before MEM_EN = 1). All DDR I/Os are set to the same calibrated value. If calibration is not used, or values other than calibrated values are desired, the driver strength values can be set in the following ways: 1. Software can be overridden in the DDRCDR. The user can select from the available override impedance values in the DDRCDR to set driver strength. Set the DSO_x_EN fields with the desired value for the corresponding P and N fields. These settings should be set before the memory controller is enabled. The address and commands, data and strobe, and clock can have different driver strength settings.

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1. When DHC_EN, DSO_MDIC_EN. and DSO_x_EN are cleared in the DDRCDR, the value in

DDR_SDRAM_CFG[HSE] determined the driver strength. Table 19 describes the DDRCDR_1 fields. Figure 18. DDR SDRAM Control Driver 1 Register (DDRCDR_1) Table 19. DDRCDR_1 Field Descriptions performed (that is, TIMING_CFG_1[DSO_MDIC_EN] is set). 1 DSO_MDIC_EN Driver software override enable for memory driver impedance calibration. 2–5 DSO_MDICPZ This field is used during the software driver calibration to override p-impedance. 6–9 DSO_MDICNZ This field is used during the software driver calibration to override n-impedance.

10 DSO_MDIC_PZ_OE This field is used during the software driver calibration to enable output to override

11 DSO_MDIC_NZ_OE This field is used during the software driver calibration to enable output to override

order of concatenation is (from left to right) DDRCDR_1[ODT], DDRCDR_2[ODT].

14 DSO_C_EN Driver software override enable for address/command

and command I/O driver strength.

15 DSO_D_EN Driver software override enable for data/strobe/data mask

data/strobe/data mask I/O driver strength. TIMING_CFG_1[DSO_C_EN] is set.

2.22 DDR SDRAM Control Driver 2 Register (DDRCDR_2)

cycles between various SDRAM control commands. Table 20 describes the DDRCDR_2 fields. Figure 19. DDR SDRAM Timing Configuration 1 Register (DDRCDR_2) Table 20. DDRCDR_2 Field Descriptions

0 DSO_CLK_EN Driver software override enable for clock

4–7 DSO_CLKPZ This field is the value of p-impedance driver for clock I/Os when DSO_CLK_EN is set. 8–11 DSO_CLKNZ This field is the value of n-impedance driver for clock I/Os when DSO_CLK_EN is set.

31 ODT ODT termination value for IOs in the memory controller

Table 19. DDRCDR_1 Field Descriptions (continued)

PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations, Rev. 2

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Revision History

3 Revision History

Table 21 provides a revision history for this application note. Table 21. Document Revision History ESDMODE[ODS] (bits 10, 14) so that second encoding is 1. selected.In addition, updated WODT_OFF (bits 21–23) field description. 0 01/2010 Initial public release.

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