AN4009 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 23
Technical content
Datasheet sections
- 1 Electrical characteristics
- 2 Safety precautions
- 3 VNI4140K-32 quad high-side smart power solid-state relay IC
- 4 STEVAL-IFP019V1 demonstration board descr iption
- 4.1 Overview
- 4.2 STEVAL-IFP019V1 schematic
- 4.3 STEVAL-IFP019V1 connectors
- 4.4 STEVAL-IFP019V1 thermal management
- 4.5 EMC immunity test
- 4.5.1 Description
- 4.5.2 Burst immunity test
- 4.5.3 Surge test
- 4.5.4 ESD test
(programmable logic controllers) which drive lamps, valves, relays, and similar loads. thermal behavior, and conformity to inherent IEC standards. Figure 1. STEVAL-IFP019V1 and thermal management results. ■ 10.5 V to 36 V DC power supply voltage range.
1 Electrical characteristics
Table 1. STEVAL-IFP019V1 electrical characteristics
2 Safety precautions
Figure 8. In case of short-circuit, current limiting or hard demagnetization, the STEVAL- IFP019V1 board, or part of it, may reach a very high temperature with consequent dangers. DC voltage applied to it may produce a dangerous explosion. may result from the improper use of this tool.
3 VNI4140K-32 quad high-side smart power solid-state
one side connected to ground. channel), and automatic restart, protect the device against overload.
- Output current: 1 A per channel
- Shorted load protections for each channel
- Junction overtemperature protection
- Case overtemperature protection for thermal independence of the channels
- Thermal case shutdown and restart not simultaneous in each single channel
- Protection against ground disconnection
- Current limitation
- Undervoltage shutdown
- Open drain diagnostic outputs
- 3.3 V CMOS/TTL compatible inputs
- Fast demagnetization of inductive loads
- Conforms to IEC 61131-2.
Figure 2. Block diagram
AN4009 VNI4140K-32 quad high-side smart power solid-state relay IC description Doc ID 022458 Rev 1 7/23 temperature is controlled. If this condition causes the case temperature to reach the case temperature limit (TCSD), overloaded channels (i.e. the ones for which junction temperature has exceeded the junction protection threshold, TjSD, and has not fallen below the junction protection reset threshold, TjR) are turned off. These channels restart, non-simultaneously, only when the case temperature decreases below the case protection reset threshold (TCR). Non-overloaded channels continue to operate normally. The open drain diagnostic outputs indicate related channel overtemperature conditions.
4 STEVAL-IFP019V1 demonstration board description
4.1 Overview
- Opto-isolated interface for input and status signals
- A four-channel self-protect power stage section with STMicroelectronics Transil™ diode protection The demonstration board consists of a double-sided FR4 printed circuit board with 35 µm copper plating. The PCB dimensions are 52 mm x 68 mm. The top and bottom views are shown below.
Figure 3. STEVAL-IFP019V1 top view Figure 4. STEVAL-IFP019V1 bottom view
4.2 STEVAL-IFP019V1 schematic
Figure 5. STEVAL-IFP019V1 schematic
4.3 STEVAL-IFP019V1 connectors
supply voltage connector (M2). communication board (see AN2451) and similar products. Figure 6. J1 connector pinout Figure 7. J5 connector pinout Table 2. J1 and J5 pin description
4.4 STEVAL-IFP019V1 thermal management
are used according to EIA/JESD51-5. Figure 8. STEVAL-IFP019V1 PCB copper heatsink 25 °C. The IC temperature increase is only about a few degrees. 1.2 H loads, 24 V supply voltage and ambient temperature of 25 °C. Figure 9. Thermal map in steady-state Figure 10. Thermal map in demagnetization
In particular, Figure 11 and 12 show 3D thermal modeling of the device.
4.5 EMC immunity test
4.5.1 Description
below) reported in the standards has been used to verify the acceptance of the results.
- Normal performance
- Temporary degradation or loss of function or performance, with automatic return to normal operation
- Temporary degradation or loss of function with of external intervention to recover normal operation
- Degradation or loss of function, need substitution of damaged components to recover normal operation.
4.5.2 Burst immunity test
- Pulse duration: 5 ns +/- 30%
- Pulse duration: 50 ns +/- 30%
- Polarity: positive/negative
- Burst duration (td): 15 ms+/- 20% at 5 kHz
- Burst period (tr): 300 ms+/- 20%
- Duration time T: 1 minute
- Applied to: supply voltage lines, output line through capacitive clamp and directly through embedded coupling capacitor in the generator. Figure 13 below shows the standard timing waveform applied during the burst test.
Figure 11. Steady-state thermal behavior 3D Figure 12. Repetitive demagnetization thermal
Figure 13. Burst timing waveform
2 To reach same results reported in the tables above, it is necessary to replace C7 and C8
with two high voltage capacitors. Note: Outputs loaded by 1 k Ω resistors. Table 3. Application EFT (burst) robustness, applied to supply voltage lines Table 4. Application EFT (burst) robustness, applied to output lines
Figure 14. EFT test set-up according to IEC 61000-4-4
4.5.3 Surge test
Figure 15 shows the standard timing waveform applied on the DUT.
Figure 15. Surge standard timing waveform
- Test signal according the IEC 61000-4-5: – 5 positive and 5 negative surges – Repetition rate: 1 minute – Coupling: 42 Ω/0.5 µF Applied to: – Supply lines (Vcc, GND) – Differential mode (DM), Vcc vs. GND – Common mode (CM), Vcc vs. Earth – OUTPUT lines (OUT1) – Differential mode (DM), Vcc vs. GND – Common mode (CM), Vcc vs. Earth Note: to reach same results reported in the tables above, it is necessary to replace C7 and C8 with two high voltage capacitors.
Table 5. Application test results, surge applied to supply lines Table 6. Application test results, surge applied to supply lines
Figure 16. Surge test set-up on supply voltage lines according to IEC 61000-4-5
4.5.4 ESD test
Figure 17. ESD test set-up according to IEC 61000-4-2
Table 7. Application ESD robustness
Table 8. STEVAL-IFP019V1 demonstration board bill of material
Table 8. STEVAL-IFP019V1 demonstration board bill of material (continued)
- AN1351 application note
Revision history
Table 9. Document revision history