AN3400

AN3400 STMICROELECTRONICS | Alldatasheet

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Datasheet sections

1 Circuit description
2 Startup phase
3 Bipolar transistor o perating modes
4 Principle of self-oscillating op eration
5 Steady-state stage-wise circui t analysis
6 Driving network modeling
7 NPN conduction phase mode ling
8 Modeling of re-circul ating phase preliminary to the NPN conduction
9 NPN storage time phase modeling
10 Modeling of the dead time after the NPN storage time phase
11 Modeling of the re-circulating pha se preliminary to the PNP conduction
12 PNP conduction phase mode ling
13 PNP storage time phase modeling
14 Modeling of the dead time after the PNP storage time phase
15 Experimental results
15.1 Applicative parameters
16 Simulation results with the Matlab tool
16.1 Simulative parameters

November 2011 Doc ID 018840 Rev 1 1/78 AN3400 Application note Analysis and simulation of a BJT complementary pair in a self-oscillating CFL solution Introduction The steady-state oscillation of a novel zero-voltages switching (ZVS) clamped-voltage (CV) self-oscillating resonant driving system for compact fluorescent lamps (CFL), using a complementary pair of bipolar transistors on the half bridge converter section, is analyzed and simulated. One or more auxiliary windings are added on the ballast inductor in series with the lamp in order to generate the periodic signal to supply the bases of the two complementary devices connected to each other in a common emitter half bridge topology. In fact, an LC network filters, with a resonant effect, the voltage generated by the secondary winding of the load transformer, producing a novel, periodic switching signal to accurately control the bases of the transistors. The two bipolars are supplied by a unitary control signal so it is not possible to turn on both devices at once because of their opposing base-emitter junction thresholds. Self-oscillating operation is divided into eight stages according to the variation over a period of the driving voltage signal across the filter capacitor at the output of the transformer secondary windings. Stage-wise circuit analysis shows as the resonant filter action limits the lamp current and dominates the switching frequency of the ballast in steady-state working condition. The half bridge of the power active devices generates a rectangular voltage waveform that drives an opportunely tuned output circuit composed of a parallel loaded RLC output circuit of which the R is the steady-state LAMP resistance. For the inverter self-oscillating condition, the switching frequency is determined by all of the circuit elements related to the oscillation frequency, such as the resonant tank, gas-discharge lamp, driving circuit, and switching devices. Depending on the circuit design, its oscillation frequency is typically around 35 to 48 kHz and can be eventually increased by shortening the storage time of the bipolars. Cost benefits are achieved by the proposed self-oscillating solution that allows to drive the CFL lamp eliminating the saturable core auxiliary transformer, placed in the more traditional standard solution, without sacrificing the performance or reducing the expected life time of the lamps. In this paper, general structure and self-oscillating principle are discussed and verified by laboratory experiment, while analytical results are validated by mathematical simulation using the Matlab tool.

Figure 33. STX83003 (NPN) bipolar transistor during steady-state operation with 230 V input voltage: Figure 34. STX83003 (NPN) bipolar transistor during steady-state operation with 230 V input voltage: Figure 35. STX83003 (NPN) bipolar transistor during turn-on particular in steady-state operation with

230 V input voltage: base current (I

Figure 36. STX83003 (NPN) bipolar transistor during tu rn-off particular in steady-state operation with

230 V input voltage: base current (IB1), collector current (IC1) and collector-emitter voltage

Figure 37. STX93003 (PNP) bipolar transistor during turn-on particular in steady-state operation with

230 V input voltage: base current (I B2), collector current (IC2) and emitter-collector voltage

Figure 38. STX93003 (PNP) bipolar transistor during turn-off particular in steady-state operation with

230 V input voltage: base current (IB2), collector current (IC2) and emitter-collector voltage

Figure 39. Current source signal Is modeling for the simulation on the re-circulating phase before the Figure 48. Driving network simulation results: filter capacitor voltage signal (V Figure 49. Driving network simulation results: NPN base current (I bn) and PNP base current (Ibp) Figure 50. Driving network simulation results: NPN base series capacitor current (I Cn) and PNP base

1 Circuit description

Figure 1 depicts the complementary pair CFL board electrical schematic. Figure 1. Complementary pair circuital topology

AN3400 Circuit description Doc ID 018840 Rev 1 7/78 working frequency and, consequently, the lamp power are influenced by the sizing of both L1 and C2 components. Capacitor C2 has also the function of putting the base current in phase with the collector current. Resistance R2 of the series R-C network has the function of regulating the current level to provide to the bases of both transistors acting on the power lamp. In the proposed driving solution, the two capacitors C3 and C4 are charged with opposite polarity to each other and assuming the same polarity of the base-emitter voltage of the relevant bipolar transistor. In the regular functionality, when a capacitor goes through a charging phase, before or during the conduction time of the relevant bipolar, so the opposite capacitor is discharging contemporarily with a long constant time due to the series with the breakdown resistance R4. So, this resistance R4, inserted between the bases of the two transistors, creating an alternative path for the discharge of each capacitor, also avoids that the oscillation is blocked during startup phase when one of the two capacitors is fully charged. Regulating the discharge time of each capacitor, this resistance allows to fine tune the working frequency and consequently the power supplied to the lamp. Two capacitors C3 and C4 are not totally discharged during a forcing voltage source period but maintain always a residual charge passing from the discharging to the charging transient. Therefore, current across the breakdown resistance R4 flows always in the same direction going from the PNP to the NPN base because the two capacitors maintain always the same polarity during a period of the voltage signal across the C2 filter capacitor. A breakdown resistance with a too high value can increase the working frequency but also can bring the reverse biased base-emitter junction of the inactive device in breakdown condition. And vice versa, a too low value of the breakdown resistance could cause re-conduction peaks in the PNP transistor at the high temperature when the emitter-collector voltage reaches the maximum value. In particular only the PNP device can show the phenomena above mentioned because it has a lower base-emitter breakdown voltage and it has a higher low current h fe than the NPN one. Setting the resistance R4 in order to guarantee a VBEoff value in the range -4 V to -7 V, it is possible to avoid breakdown phenomena for the base-emitter junctions of the bipolars and, at the same time, anomalous re-conduction effects due to unexpected disturbances.

2 Startup phase

The two bipolar transistors should have an appropriately high gain value in order to guarantee the correct ignition of the lamp during the startup phase. Compact fluorescent lamps usually require about 600 V as peak voltage to strike the arc. Once the arc is established about 100 V are enough to sustain it while, electrically, the resistance of the lamp falls from about one mega ohm down to a few hundred ohm (see References 1). Furthermore, the value of the load inductance L of the ballast must be chosen so that it does not saturate at the operative current of the lamp, even at high temperatures. In fact the lamp is ignited by generating an overvoltage across the capacitor C6 in parallel to the tube, through the circuit formed by the series of the ballast transformer primary inductance and C6-C7-C8 capacitors. At startup the lamp is an open circuit and the C6 capacitor imposes the resonant frequency of the circuit as C6 is much smaller than the C7-C8 ones. The imposed overvoltage is high enough to ionize almost instantaneously the gas in the lamp. Once the lamp is lighted, the capacitor C6 is short-circuited by the lamp itself and the natural frequency is determined mainly by the capacitors C7-C8 charged/discharged through the DC-AC converter. The startup network is represented by the only resistor R3, connected between the collector and the base of the high side transistor, since the capacitors in series with the bases act as a high impedance elements during the first instant of the startup.

AN3400 Bipolar transistor operating modes Doc ID 018840 Rev 1 9/78

3 Bipolar transistor operating modes

Bipolars switching in the resonant circuit have three different operating modes in normal working conditions: re-circulating, conduction and transition phases. During the re-circulating phase, the transistor isn't yet in conduction state and passes from a first inactive state in which its B-C junction diode is activated to allow the re-circulation of load inductor demagnetization current ILP shared with the external diode in anti-parallel to the device itself, to a second inactive state in which the external diode is turned off but both of the two B-E and B-C junctions are forward biased in order to complete the residual demagnetization of the Lp inductor until the forcing re-circulating current I LP, that imposes the negative collector current, reaches the zero value. In conduction mode, the two B-E and B-C junctions of the transistor continue to be forward biased and the bipolar transistor conducts a positive magnetization current for the inductive load. The turn-off mechanism occurs in three stages: “storage time”, or time spent to extract the storage in excess and recombine the charge stored on the base, “current fall time”, in which the collector current passes from 90% to 10% of its maximum value, and “rise time” of the collector-emitter voltage. The transition mode occurs during the voltage rise time and represents a sort of “dead time” phase in which both bipolars are substantially inactive since only the B-C and B-E junction capacitances of both devices are interested in being charged/discharged in reverse bias. This phase anticipates the re-circulating phase preliminary to the conduction phase of the complementary device. During the turn-off process, the dynamic operation point of the transistor moves through three different operating regions on the current-voltage I C-VCE characteristic: “hard saturation region”, “quasi saturation region” and “active region”.

Hard saturation region: at the first instance of turn-off switching time, the base-collector junction is forward biased and the base region and collector drift region are both in high-level injection condition. An excess carrier distribution fills the collector drift region and the storage time is just the time required to remove/extract this charge stored in excess. Also the contribution of charge decay due to recombination, depending on the minority-carrier lifetime, influences this phase. During the storage time process the base-emitter voltage does not change immediately from its forward bias value V BESAT, due to the excess minority carriers stored in the base region, and also the collector-emitter voltage remains constant. The extent of storage time is dependent not only on the amount of excess charges remaining in the collector drift region but also on the external driving. Excess minority carriers are removed from the base region and base-collector junction at a constant rate determined by the negative base drive voltage, as well as the base drive resistance, and proportional to the reverse base current I Boff slope. So the excess charge at the base-collector junction begins to reduce due to charge removal to make up for the reverse base current and the collector current continues to increase.
Quasi saturation region: after the storage time, the forward biased base-collector junction is out of high-level injection and the remaining charges stored in the base become insufficient to support the transistor in the hard saturation region. Therefore, at this point the transistor enters quasi saturation region in which the depletion region begins to expand while a voltage appears across it and the collector-emitter voltage starts rising with a small slope. After having removed the charges in the drift region holding the bipolar in the quasi saturation region, the transistor enters the active region.
Active region: crossing the active region, the charges stored in the base region are insufficient to support the full negative base current so the base-emitter voltage starts falling negatively and the negative base current starts reducing. Correspondingly, the stored base charges can no longer support the full load current through the collector so that also the collector current decays exponentially resulting in current fall time required

Bipolar transistor operating modes AN3400 10/78 Doc ID 018840 Rev 1 to remove remaining stored charge in base. Both of the slopes dictated by base current and collector current simultaneously decay with time due to recombination. Collector-emitter voltage increases rapidly towards the rectified voltage upper rail VCC until it is exceeded in order to turn-on the anti-parallel diode of the complementary device at the end of the rise time interval. The increasing voltage is supported across the collector drift region while the expanding depletion region at the base-collector junction sweeps out the excess charge until it totally sustains the bus voltage. To reduce the stress on the devices, and hence the switching losses, the half bridge converter switches under zero voltage (ZVS) conditions, in which turn-on losses are absent and a favorable turn-off trajectory of power transistors can be ensured by the use of a snubber capacitor. In fact, contrary to the hard switching dynamic, in which the voltage rise was a function of the amount of charge in the drift region after the storage phase, with the soft-switching dynamic the rate of voltage rise during turn-off is controlled by the snubber capacitor connected across the device. While the voltage continues to raise, the collector current decays to zero and the load current flows into the snubber capacitor until the device voltage reaches the bus voltage. Therefore, even though turn-off does not occur at exactly zero volts, the stresses on the device are much reduced compared to hard-switching mode. When the collector current reaches the zero value, the bipolar turn-off process is completed and the load current starts to freewheel through the anti-parallel diode of the complementary device.

4 Principle of self-oscillating operation

residual demagnetization current from the load transformer. theoretical working principle of the proposed driving system.

Re-circulating time phases with a time length of “tA” and “tC” respectively for the NPN and PNP transistors
Conduction time phases indicated with “NPN-IBontime” and “PNP-IBontime”
Storage time phases indicated with “NPN-IBstoragetime” and “PNP-IBstoragetime”
Dead time phases with the time length of “tB” and “tD” respectively for the NPN and PNP transistors. As previously described, the “dead time phase” refers to the transient occurring during the voltage rise time and in which both of the bipolars are substantially inactive since only the B-E and B-C junction capacitances on both devices are interested in being charged/discharged in reverse bias. Moreover, from this point on and for the whole steady-state analysis subsequently explained, it is assumed to name, for the sake of simplicity, as storage time the interval including both the effective storage time and fall time of the device.

Figure 2. Steady-state waveforms: filter capacitor voltage signal (V(t)), NPN base

5 Steady-state stage-wise circuit analysis

the successive simulation in Matlab environment.

Stage 1: t0<t<t2 and t12<t<t14: (re-circulating phase before the NPN conduction time: 0<V(t)< VCnpnon-char+VBEsatnpn with ) The re-circulating phase is referred to all the demagnetization transient of the load inductor Lp elapsing until its current ILP reaches the zero value at the end of this stage. This phase, in which both Q1-Q2 switches are inactive, can be subdivided into a further two sub-phases distinguished by the following: – First re-circulating phase before the NPN conduction time (t 0<t<t1 and t12<t<t13): Both Q1-Q2 switches are turned off and the anti-parallel diode D1 of the NPN transistor conducts, sharing with the forward biased B-C NPN bipolar junction, the residual demagnetization current I LP from the load inductor Lp. Voltage across the filter capacitor C increases and charges the capacitor Cn in series to the not yet forward biased NPN base-emitter junction, therefore assuming the same polarity of the relevant V BEnpn-on, whereas the capacitor Cp begins to discharge through the breakdown resistance Rb. In this re-circulating stage, currents and voltages on the driving network are represented by the information in Figure 7.

Figure 7. First stage: first re-circu lating phase before the NPN conduction time

Steady-state stage-wise circuit analysis AN3400 16/78 Doc ID 018840 Rev 1 According to the agreement in Figure 7, the following equations are valid in the driving section during the first re-circulating stage for t0<t<t1 and t12<t<t13: System of equations 1 in which IBCn and VBCn are, respectively, the current signal and voltage signal of the NPN bipolar forward conducting B-C junction diode. During this phase, in general, VBEn(t) voltage is so that 0<VBEn(t)<VBEn-on for the NPN bipolar B-E junction diode, but if it were VBEn(t)<0 the device would work in reverse active region as it is VBCn(t)>0. Neglecting the reverse recovery time of the anti-parallel diode D1, the subsequent phase is given by the following second re-circulating phase before the NPN conduction time.

Second re-circulating phase before the NPN conduction time (t1<t<t2 and t13<t<t14): In this phase the NPN bipolar transistor acts as two uncoupled/independent diodes. In fact, the external diode D1 is turned off and the NPN device continues to be inactive but, contrary to the previous first re-circulating phase, both of its two B-E and B-C junctions are forward biased in order to complete the residual demagnetization of the Lp inductor until the forcing re-circulating current I LP, that imposes the negative (extractive) collector current, reaches the zero value. Voltage across the filter capacitor C continues to increase and charge the capacitor Cn in series to the forward biased NPN base-emitter junction whereas the capacitor Cp continues to discharge through the breakdown resistance Rb. When the inductive resonant current reverses, after t instant, the successive phase starts and the NPN device Q1 conducts carrying a positive (coming in) collector current I Cnpn. In this second re-circulating stage, currents and voltages on the driving network are represented by the information in Figure 8. () () tVtV C= () () () onBEn1DBCnBEn VtVtVtV −<−= where () onBCnBCn VtV −> and () on1D1D VtV −> () () dttIC 1VtV 0t Cn n a1CnorCn ∫+= where () −= 0Cna1Cnor tVV () () dttI C 1VtV 0t Cp p a1CporCp ∫−= where () −= 0Cpa1Cpor tVV () ()() tVdt dCtI CnnCn ⋅= () ()() tVdt dCtI CppCp ⋅−= () () () () () () tItItItItItI RS1DLPCpCnBCn =−=+= () () () () () tVtVtVtVtV BEnBEpRbCpCn −==+ with () () 0tVtV EBpBEp >−=

Figure 8. First stage: second re-circulating phase before the NPN conduction time

Stage 2: t2<t<t4: (NPN conduction time: V(t)>VCnpnon-char+VBEsatnpn during filter capacitor C charging phase for t2<t<t3 with and V(t)>VCnpnon-dischar+VBEsatnpn during filter capacitor C discharging phase for t3<t<t4 with ). From the t2 instant V(t) voltage is higher than the VCnpnon-char+VBEsatnpn value and increases up to reach its maximum value at t3. NPN transistor Q1 is turned on under zero voltage switching (ZVS) and the current in the resonant load inductor increases. Capacitor C n continues to be charged up by the source V(t), whereas capacitor Cp discharges through the breakdown resistance Rb inserted between the bases of the AM09799v1 L c Cp Cn Cs Rs Rb Ls VRs IRs VCn VCp ICn ICp IRb VRb IBnpn VBCn IEnpn ILP Lp VDD VCs VBEn VBEp VC GND IBnpn VBCnVB ICnpn VBEn NPN base-collector diode conductionNPN base-collector diode conduction NPN base-emitter NPN base-emitter diode conductiondiode conduction Second re-circulating phase before NPN conduction () () tVtV C= () onBEnBEn VtV −= () onBCnBCn VtV −= and () () on1DCEnEC n VtVtV −<−= () () dttIC 1VtV 1t Cn n b1CnorCn ∫+= where () −= 1Cnb1Cnor tVV () () dttIC 1VtV 1t Cp p b1CporCp ∫−= where () −= 1Cpb1Cpor tVV () ()() tVdt dCtI CnnCn ⋅= () ()() tVdt dCtI CppCp ⋅−= () () () () () () () () tItItItItItItItI RSEnpnLPEnpnCnpnCpCnBnpn =+=+=+= () () () () () tVtVtVtVtV BEnBEpRbCpCn −==+ with () () 0tVtV EBpBEp >−= ()() 0tVdt d > ()() 0tVdt d <

AN3400 Steady-state stage-wise circuit analysis Doc ID 018840 Rev 1 19/78 According to the agreement of the previous images, the following equations are valid in the driving section during the NPN conduction stage for t2<t<t4: System of equations 3 where VBEn-sat is the voltage of the forward conducting B-E junction diode of the NPN bipolar and IBnpn-on is the base current for the NPN bipolar working in saturation state.

Stage 3: t4<t<t5: (NPN storage time: VCnpnoff-char+VBEsatnpn<V(t)<VCnpnon-dischar+VBEsatnpn with ) The decreasing voltage V(t) across the filter capacitor C equals the V Cnpnon-dischar+VBEsatnpn value at t4 instant. At this point the voltage on the capacitor Cn starts to decline but the stored charges of the NPN bipolar base keep the NPN conducting with a negative base current (extraction base current IBnpn-off) while the Cp capacitor maintains its discharging phase. After the stored excess charges have disappeared, the operating point of the NPN enters its active region and V CEnpn voltage begins to increase while the collector current ICnpn drops. Therefore, the collector current ICnpn fall time phase is included in this state until the NPN bipolar Q1 is gradually soft switched on turn-off. In this stage, currents and voltages on the driving network are represented by the information in Figure 11. () () tVtV C= () satBEnBEn VtV −= () satCEnCEn VtV −= () () dttI C VtV t t Cn n CnocCn ∫+= 1 where () −− == 21 tVVV CncharCnpnonCnoc () () dttICVtV t t Cp p Cp ocCp ∫−= where () −= 21 tVV CpCpoc () ()() tV dt dCtI CnnCn ⋅= () ()() tVdt dCtI CppCp ⋅−= () () () () () () tItItItItItI RSLPEnpnCpCnonBnpn =−=+=− where () () tItI Cnp nLP = () () () () () tVtVtVtVtV BEnBEpRbCpCn −==+ with () () 0>−= tVtV EBpBEp () () () () tVtVtVtV BEnCnRSC ++= ()() 0tV dt d <

Figure 11. Third stage: NPN storage phase where IBnpn-off is the extracting base current during the storage time of the NPN bipolar.

Stage 4: t5<t<t6: (dead time after the NPN conduction phase: 0<V(t)<VCnpnoff-char+VBEsatnpn with ) At t5 instant, the load inductor current ILP continues to decay and the resonant current is commutated from the NPN bipolar Q1 to the snubber capacitor Cs that discharges. As a result, the voltage on the common emitter node of the two switches decreases linearly from the upper rail to the lower rail until the emitter voltage of the PNP transistor Q2 begins to go negative with respect to the lower rail (ground reference) at t 6 and the anti-parallel diode D2 of the PNP transistor starts to conduct beginning the next fifth stage. At the end of this “dead time” stage, the voltage on the capacitor C p is reduced AM09802v1 L c Cp Cn Cs Rs Rb Ls VRs IRs VCn VCp ICn ICp IRb VRb IBnpn IEnpn ILP Lp VDD VCs VBEn VBEp VC GND ICnpn VCEn NPN storage phase () () tVtV C= () satBEnBEn VtV −= () satCEnCEn VtV −≥ () () dttIC 1VtV 4t Cn n 1CnosCn ∫−= where () −= 4Cn1Cnos tVV () () dttI C 1VtV 4t Cp p 1CposCp ∫−= where () −= 4Cp1Cpos tVV () ()() tV dt dCtI CnnCn ⋅−= () ()() tV dt dCtI CppCp ⋅−= () () () () () () tItItItItItI RSEnpnLPCpCnoffBnpn =−=−=− where () () tItI CnpnLP = () () () () () tVtVtVtVtV BEnBEpRbCpCn −==+ with () () 0tVtV EBpBEp >−= () () () () tVtVtVtV BEnCnRSC ++−= ()() 0tV dt d <

to the minimum value whereas the voltage on the capacitor Cn keeps nearly constant. Figure 12. Fourth stage: dead time after NPN conduction phase

currents and voltages on the driving network are depicted by the information in Figure 14. Figure 14. Fifth stage: first re-circulating phase before PNP conduction time with

given by the following reported second re-circulating phase before the PNP conduction time. current ICpnp to the PNP bipolar Q2 and the successive PNP conduction phase begins. Figure 15. Fifth stage: second re-circulating phase before the PNP conduction time

AN3400 Steady-state stage-wise circuit analysis Doc ID 018840 Rev 1 25/78 According to the agreement of the previous image, the following equations are valid in the driving section during the second re-circulating stage for t7<t<t8: System of equations 7

Stage 6: t8<t<t10: (PNP conduction time: V(t)<-VCpnpon-char-VEBsatpnp during filter capacitor C charging phase for t8<t<t9 with and V(t)<-VCpnpon-dischar-VEBsatpnp during filter capacitor C discharging phase for t9<t<t10 with ). From the t8 instant V(t) voltage is lower than the -VCpnpon-char-VEBsatpnp value and decreases reaching its minimum value at t9. PNP transistor Q2 turns on under zero voltage switching and the current in the resonant load inductor increases in module. Capacitor Cp continues to be charged up by the source V(t), whereas capacitor Cn discharges through the breakdown resistance Rb. At t9 instant the voltage on filter capacitor C reaches its maximum inverse (negative) value. After this time V(t) decreases negatively in module whereas the capacitor Cp continues to charge until it reaches its maximum value and the capacitor Cn to discharge maintaining a share of conduction current on the base IBp of the PNP bipolar Q2. During this stage the base current IBp of the PNP bipolar transistor is the sum of the currents ICn and ICp in both capacitors. In this way, it is possible to consider the voltage signal VCn, as a voltage source when the PNP device Q2 is conducting. In this stage, currents and voltages on the driving network are represented by the information in Figure 16 and 17. () () tVtV C−= () onEBpEBp VtV −= () onCBpCBp VtV −= and () () on2DECpCEp VtVtV −<−= () () dttI C 1VtV 7t Cn n b2CnorCn ∫−= where () −= 7Cnb2Cnor tVV () () dttI C 1VtV 7t Cp p b2CporCp ∫+= where () −= 7Cpb2Cpor tVV () ()() tV dt dCtI CnnCn ⋅−= () ()() tV dt dCtI CppCp ⋅= () () () () () () () () tItItItItItItItI RSEnpnLPEpnpCpnpCpCnBpnp =+=+=+= () () () () () tVtVtVtVtV EBpEBnRbCpCn −==+ with () () 0tVtV BEnEBn >−= ()() 0tV dt d < ()() 0tV dt d >

AN3400 Steady-state stage-wise circuit analysis Doc ID 018840 Rev 1 27/78 According to the agreement of the previous images, the following equations are valid in the driving section during the conduction stage of the NPN for t8<t<t10: System of equations 8 where VEBp-on is the voltage of the forward conducting E-B junction diode of the PNP bipolar and IBpnp-on is the base current with PNP bipolar working in saturation state.

Stage 7: t10<t<t11: (PNP storage time: -VCpnpon-dischar-VEBsatpnp<V(t)<-VCpnpoff-char-VEBsatpnp with ) Voltage V(t) across the filter capacitor C decreases, in module, negatively up to equal the -VCpnpon-dischar-VEBsatpnp value at t10 instant. At this point the capacitor voltage Cp starts to decline and the excess charges stored in the PNP device Q2 base keeps it conducting with a negative base current (coming-in base current IBpnp-off) while the Cn capacitor maintains its discharging phase. After the stored excess charges have disappeared the operating point of the PNP enters its active region and the VECpnp voltage begins to increase while the collector current ICpnp falls down. Therefore, the collector current ICpnp fall time phase is included in this state until the PNP bipolar Q2 is gradually soft-switched on turn-off. In this stage, currents and voltages on the driving network are represented by the information in Figure 18. () () tVtV C−= () satEBpEBp VtV −= () satECpECp VtV −= () () dttIC 1VtV 10t 8t Cn n 2CnocCn ∫−= where () −= 8Cn2Cnoc tVV () () dttI C 1VtV 10t 8t Cp p 2CpocCp ∫+= where () −== 8CpCp npchar2Cpoc tVVV () ()() tV dt dCtI CnnCn ⋅−= () ()() tVdt dCtI CppCp ⋅= () () () () () () tItItItItItI RSLPEpnpCpCnonBpnp =−=+=− where () () tItI CpnpLP = () () () () () tVtVtVtVtV EBpEBnRbCpCn −==+ with () () 0tVtV BEnEBn >−= () () () () tVtVtVtV EBpCpRSC ++= ()() 0tV dt d >

Figure 18. Seventh stage: PNP storage phase where IBpnp-off is the coming-in current during the storage time of the PNP bipolar.

Stage 8: t11<t<t12: (dead time after the PNP conduction phase: -VCpnpoff-char-VEBsatpnp <V(t)<0 with ) At t11 instant, the current ILP in the load inductor has started to decay and the resonant current is commutated from the PNP bipolar Q2 to the snubber capacitor Cs that charges. As a result, the voltage on the common emitter node of the two switches increases linearly AM09809v1 VEBn IBpnp ICpnp IEpnp VEBp VECp L c Cp Cn Cs Rs Rb Ls VRs IRs VCn VCp ICn ICp IRb VRb ILP Lp VDD VCs VC GND PNP storage phase () () tVtV C−= () satEBpEBp VtV −= () satECpECp VtV −≥ () () dttI C 1VtV 11t 10t Cn n 2CnosCn ∫−= where () −= 10Cn2Cnos tVV () () dttI C 1VtV 11t 10t Cp p 2CposCp ∫−= where () −= 10Cp2Cpos tVV () ()() tV dt dCtI CnnCn ⋅−= () ()() tV dt dCtI CppCp ⋅−= () () () () () () tItItItItItI RSEpnpLPCnCpoffBpnp =−=−=− where () () tItI CpnpLP = () () () () () tVtVtVtVtV EBpEBnRbCpCn −==+ with () () 0tVtV BEnEBn >−= () () () () tVtVtVtV EBpCpRSC ++−= ()() 0tV dt d >

transistor Q1 begins to conduct, commencing again a new cycle starting from the first stage. Figure 19. Eighth stage: dead time phase after PNP conduction

Steady-state stage-wise circuit analysis AN3400 30/78 Doc ID 018840 Rev 1 According to the agreement of the previous image, the following equations are valid in the driving section during the dead time after the PNP conduction phase for t11<t<t12: System of equations 10 where ICCBn is the discharging current of the NPN bipolar B-C junction capacitance and ICBCp is the charging current of the PNP bipolar C-B junction capacitance. The end of this stage represents the completion of one full conversion cycle and then the process repeats returning to the original operational stage in the complementary direction using the anti-parallel diode D1 before the NPN bipolar transistor Q1 conduction phase. After the operating modes of the bipolar transistors on the switching converter section have been identified, the corresponding Matlab models of the resonant driving network are created as explained in the following. () () tVtV C−= () satECpECp VtV −> () () () () () ( ) 00 <⇒>−−−==− tVtVtVVtVtV BEnCSCCBnDDEBnBEn () () () () () 00 <⇒>−==− tVtVtVtVtV EBpCSCBCpBEpEBp () () dttICVtV t t Cn n CnodCn ∫−= 112 1 where () −= 112 tVV CnCnod () () dttICVtV t t Cp p CpodCp ∫−= 112 1 where () −= 112 tVV CpCpod () ()() tVdt dCtI CnnCn ⋅−= () ()() tVdt dCtI CppCp ⋅−= () () () () () tItItItItI CSLPCB CpCCBnRS −=+= () ()() tVdt dCstI CSCS ⋅= () () () () () tVtVtVtVtV EBnBEpRbCpCn +==+ () () () () tVtVtVtV BEpCpRSC −+−=

6 Driving network modeling

Figure 20. Driving network modeling for th e NPN bipolar conduction phase simulation

Driving network modeling AN3400 32/78 Doc ID 018840 Rev 1 in which: System of equations 11 Two different conditions at the initial instant t2, respectively, one for the VCn voltage signal and the other for its function derivative, are needed to impose in order to obtain one, and only one, solution of the Equation 2, therefore solving the following Cauchy problem: System of equations 12 As a consequence of the LC filtering action on the voltage signal at the output of the secondary windings, Vs signal can be expressed, with a good approximation, as a sinusoidal voltage generator having the below reported mathematical expression valid in the entire time interval (t 0, t12): Equation 3 Then, imposing VBEn=VBEsat=constant for the NPN device base-emitter junction during its conduction phase (that is ), it is possible to change the System of equations 12 into the form with ω=2πf: bS CRRm ⋅⋅= with pn CCC == () bS RR2Ch +⋅= 1k = bB RC⋅=τ onBEnBEn VV −= () () tVtV filterCS −= dt dtV dt dVVtVktV dt dhtV dt dm BEnBSBBEnSCnCnCn ⋅−⋅+−=⋅+⋅+⋅ ττ2 () 12 γ=tVCn ()() 2 γ=⎥⎦ =tt Cn tV dt d VS t() As e n 2 πft()⋅= with t0 tt 12<< ()() 0tVdt d BEn =

AN3400 Driving network modeling Doc ID 018840 Rev 1 33/78 System of equations 13 Therefore, the second order linear differential equation with constant coefficients on the state variable VCn takes the form of the physics law that rules the motion of a dumped harmonic oscillator driven by an externally applied forcing signal given by the superimposition of two independent sinusoidal generators and . After having re-written this equation in the form: Equation 4 in which it is fixed: System of equations 14 it is possible to obtain the general solution as the sum of a transient solution (associated homogeneous equation solution or unforced equation) that depends on initial conditions, and a steady-state solution (particular solution) that is independent by the initial conditions but depends only on the amplitudes of the driving signals ( , and ), driving frequency (ω), undamped angular frequency (ω0), and the damping ratio (ξ). Steady-state solution is proportional to the driving forces with an induced phase change of φ as follows: Equation 5 where and are respectively module and phase of the frequency response function . A m Vtse nm AtVm ktVdt d m htV dt d BBEn CnCnCn2 () =tV 12Cn γ ()() 2 2tt Cn tV dt d γ=⎥⎦ () tsenm AV 1S ω⋅= )tcos(m AV B 2S ω⋅ω⋅⋅τ= m A m Vtsen m AtVtV dt d2tV dt d BBEn Cn 0Cn0Cn2 m 0 =ω km2 h h m ω =ξ⇒=ξω m A m VBEn () ( ) () () m Vtcosm Attsenm AjGtV 2 BEnB esteadystatCn () () 222 1jG ω−ω+ωξω =ω () ⎟⎟ ω−ω ξωω=ω∠=φ 2 02arctgjG ()ωjG

Driving network modeling AN3400 34/78 Doc ID 018840 Rev 1 Resolving the polynomial characteristic of Equation 4, the following can be obtained: Equation 6 with implying that λ1 and λ2 are distinct real roots and then the particular solution is on the forms: Equation 7 The general solution VCn is the sum of steady-state solution Equation 5 and the transient solution Equation 7 reported as follows: valid on the (t2,t4) time interval in which VBEn=constant for hypothesis. In order to free the VCn signal calculation by the imposition of its derivative value at the initial instant t2 on the Cauchy problem resolution referred to in the System of equations 12, the method used to simulate in Matlab environment the driving network, in each working phase for the bipolar devices, is based on resolving a system of two first order linear differential equations on the two state variables V Cn and VCp combined with each other as explained in the following. By simulating with the Matlab tool, the ODE45 solver algorithm has been used for the resolution of the initial value problem concerning the system of ordinary differential equations related to each operation phase of the opportunely modeled bipolars during the steady-state working condition. The ODE45 function uses the syntax expressed by the command: [t,Y]= ode45 (odefun, tspan, y0, options) Input arguments to the solver are listed as:

odefun → Function, expressed with a Matlab function-file, that evaluates the right side of the differential equations.
tspan → Vector specifying the interval of integration (t0,tf). The solver imposes the initial conditions at t0=tspan(1) and integrates from t0 to tf =tspan(end).
y0 → Vector of initial conditions.
options → Structure of optional parameters that change the default integration properties. Output arguments for the solver are the following:
t → Column vector of time points.
Y → Solution array. Each row in y corresponds to the solution at a time returned in the corresponding row of t. The solver integrates the system of differential equations y'=f(t,y) from time t0 to tf with initial conditions y0. Function f=odefun(t,y), for a scalar t and a column vector y, must return a column vector f corresponding to f(t,y). Each row in the solution array Y corresponds to a time returned in column vector T. The ODE45 solves with default integration parameters 002,1 2 02 ω−ξω±ξω−=λ⇒=ω+λ⋅ξω+λ () () 0 CRR4 RR4mk4h B S B 0 > ⋅⋅⋅ +⋅=− =ω−ξω=Δ () t t 1transientCn 21 ecectV ⋅λ⋅λ − ⋅+⋅= () () () tVtVtV transientCnesteadystatCnCn −− +=

AN3400 Driving network modeling Doc ID 018840 Rev 1 35/78 replaced by property values specified in 'options', an argument created with the 'odeset' function having the following syntax: options = odeset ('RelTol',value1,'AbsTol',value2) in which scalar relative error tolerance RelTol is set equal to 1e-5 (1e-3 by default) and the vector of absolute error tolerance AbsTol is set equal to 1e-8 (all components are 1e-6 by default).

NPN conduction phase modeling AN3400 36/78 Doc ID 018840 Rev 1

7 NPN conduction phase modeling

In order to adequately simulate the NPN conduction time phase through the Matlab tool, the function solution VCn of the System of equations 12 can be equivalently obtained, together with VCp function, resolving the following system of two first order linear differential equations on the two state variables VCn and VCp valid on the [t2, t4] time interval with the initial hypothesis of VBEn=constant and C=Cn=Cp: System of equations 15 As seen, only two conditions, respectively, for the VCn and VCp voltages at the initial instant t2, are needed to be imposed for the resolution of the System of equations 15. These two initial conditions and , are fixed in order to guarantee the continuity for the V Cn and VCp waveforms passing from the re-circulating phase to the NPN bipolar conduction time phase, being and the values for VCn and VCp functions obtained at the re-circulating phase final instant t2. After that, the two VCn and VCp functions have been obtained by resolving the previous system, the NPN bipolar base current IBnpn-on is directly given by the following formula: Equation 8 in which is a discharging voltage on the C p capacitor (that is ). After having determined, through the ODE45 simulator, in a rather large time interval (one half of the total working period), the VCn and VCp voltage functions that resolve the System of equations 15, then a research of the maximum value for the VCn function was imposed in order to determinate the final instant of the NPN conduction time t4. This NPN conduction time phase is preceded by the re-circulating phase which follows. ()() S BEn S S npnconCp b npnconCn bS npnconCn RC V RC VV RC R R C 1tV dt d −⋅⎟⎟ ()() npnconCp b npnconCn b npnc onCp V RC RC 1tV dt d −−− ⋅ () () −−+− = 2npnricCn2npnconCn tV tV () () −−+− = 2npnricCp2npnconCp tV tV () () tV=tV 2npnconCn2npnricCn +−−− () () tV=tV 2npnconCp2npnricCp +−−− () tV 2npnricCn −− () tV 2npnricCp −− dt dCtV dt dCtItItI npnconCpnpnconCnnpnconCpnpnc onCnonBnpn −−−−− ⋅−⋅=+= ()tV npnconCp − ()() 0tV dt d npnconCp <−

8 Modeling of re-circulating phase preliminary to the

Figure 21. Driving network modeling for the si mulation of the first re-circulating phase

Figure 22. Driving network modeling for the simulation of the second re-circulating phase

AN3400 Modeling of re-circulating phase preliminary to the NPN conduction time phase Doc ID 018840 Rev 1 39/78 signal opportunely modeled in order to take into consideration the effect of demagnetization current for the inductor Lp. Also in this case, for the NPN bipolar base current IBnpn, the formula below is valid during the whole re-circulating phase preliminary to the NPN conduction time phase: Equation 9 in which is a discharging voltage on the C p capacitor (that is dCtVdt dCtItItI npnricCpnpnri cCnnpnricCpnpnricCnBnpn −−−− ⋅−⋅=+= ()tV npnricCp− ()() 0tVdt d npnricCp <−

9 NPN storage time phase modeling

Figure 23. Driving network modeling for the NPN bipolar storage time phase simulation

Figure 24. Variability of the extractive current negative peak I Bnpn-off versus

NPN storage time phase modeling AN3400 42/78 Doc ID 018840 Rev 1 Therefore, it is important to fix correctly the two α1 and n parameters in order to opportunely model the transistor base resistance modulation effect during the storage time phase simulation. The following mathematical formula has been considered to make a connection among the storage time duration and the base currents developing during the conduction and storage time phases of the device (see References 3): Equation 12 In which:

with Aon-npn area subtended to the IBnpn-on current curve during the Ton conduction period;
with Astorage-npn the module of the area (positive) subtended to the IBnpn-off current curve during the Tstorage-npn storage time period;
σnpn is a time constant directly connected to the lifetime of the minority carriers (electrons) in the transistor base. Constant σnpn can be experimentally calculated, with a good approximation, supposing two triangular areas subtended respectively to the IBnpn-on and IBnpn-off current curves and, in this case, Equation 12 assumes the following simplified form: Equation 13 being IBnpn-on-max and the maximum values of the conduction and extraction (in module) currents. Consequently, the σnpn value can be mathematically and, in an approximate manner, determined if the values of the Tstorage-npn, IBnpn-on-max and IBnpn-off-max assumed (measured) by the devices during the applicative steady-state working conditions are well-known. Substituting the definitions of the IBnpn-on-average, IBnp-off-avarage and σnpn parameter to Equation 12, the following equation is obtained: Equation 14 +⋅σ= aver ageoffBnpn av erageonBnpn npnnpnstorage I I 1lnT npnon npnon averageonBnpn T A I −− = npnstorage npnstorage averageoffBnpn T A I −− = =σ⇒ +⋅σ= maxoffBnpn maxonBnpn npnstorage npn maxoffBnpn maxonBnpn npnnpnstorage I I 1ln T I I 1lnT maxoffBnpnI −− ε⋅+⋅σ= npn npnstor age npnon npnnpnstor age T T 11lnT

AN3400 NPN storage time phase modeling Doc ID 018840 Rev 1 43/78 in which the following is imposed: Equation 15 with εnpn parameter depending on the recombination phenomenon of a share of the amount of charges in base. Once the two parameters σnpn and Ton-npn are fixed and well-known (the latter parameter obtained from the simulation of the previous conduction period) Equation 14 is used to define the function of two independent variables: Equation 16 In order to determine the length of the time interval to set for the NPN storage time simulation with the ODE45 simulator, the following procedure has been applied through the Matlab tool:

m different ε(i)npn values, increasing, equally-spaced out and included between a minimum εmin-npn and a maximum εmax-npn value, are fixed in base to the recombination characteristics of the minority carriers in base of the bipolar examined, that is: Equation 17 and also with: Equation 18 Equation 19
m zeros of the defined function f(Tstorage-npn, εnpn) are evaluated with the Matlab tool for each ε(i)npn fixed: Equation 20
Tstorage-npn final value is obtained performing an arithmetical average operation among all the T(i)storage-npn so calculated: Equation 21 npnon npnstorage npn A A ε ⋅+⋅σ−=ε npn npnstorage npnon npnnpnstoragenpnnpnstorage T T 11lnT),T(f npn)i(ε for m1i ÷= with npnmaxnpnnpnmin )i( −− ε≤ε≤ε npnnpn )1j()j( +ε≠ε for )1m(1j −÷= npnnpnnpnnpn )k()1k()1k()k( ε−+ε=−ε−ε for )1m(2k −÷= 0))i(,)i(T(f npnnpnstorage =ε− for m1i ÷= npnstorageT − = () ∑ −−− ⋅= m npnstoragenpnsto rag enpnstorage )i(T m

NPN storage time phase modeling AN3400 44/78 Doc ID 018840 Rev 1 Setting the values εmin-npn, εmax-npn with the two parameters σnpn and Ton-npn well-known, a realistic evaluation of the effective NPN device storage time can be obtained applying the procedure of calculation previously explained. After having found, with the ODE45 simulator, in the calculated time interval T storage-npn, the solutions of the System of equations 18 for the VCn and VCp voltage functions, then the NPN bipolar base current IBnpn-off is given by the following formula: Equation 22 in which both VCn-npnsto(t) and VCp-npnsto(t) are discharging voltages respectively on the Cn and Cp capacitors (that is and ). dt dCtV dt dCtItItI npnstoCpnpnstoCnnpnstoCpnpnstoCnoffBnpn −−−−− ⋅+⋅−=−= ()() 0tV dt d npnstoCn <− ()() 0tV dt d npnstoCp <−

10 Modeling of the dead time after the NPN storage time

to the working condition, respectively, of the NPN and PNP device is considered. Figure 25. Driving network modeling for the simulation of the dead time phase after the NPN

on the charge phase of the (variable) NPN base-collector junction capacitance CCBnpn;
on the discharge phase of the (variable) PNP collector-base junction capacitance CBCpnp. Then, imposing the previous assumptions, combining, with each other, the equations of the System of equations 5, describing the working conditions of the NPN bipolar during this AM09815v1 Cp Cn Cs Rs Rb VRs IRs VCn VCp ICn ICp IRb VRb ILP Lp Q2 VCs GND ICCBn VCCBn ICs VCBCp ICBCp VCEBn VDD VCBEp ICBEp IBpnp ICEBn IBnpn Vs Cp CnRs Rb VRs IRs VCn VCp ICn ICp IRb VRb ILP VCs GND ICCBnVCCBn ICs VCBCp ICBCp VCEBn VDD VCBEp ICBEp IBpnp ICEBnIBnpn Vs Cs ⇒≅ 0I,I CBEpCEBn CCBn Bnpn II ≅ , CBCpBpnp II ≅ and LPCS II ≅ ()() tV dt dCI CCBnCBnpnCCBn ⋅= ()() tV dt dCI CB CpBCpnpCBCp ⋅−=

Modeling of the dead time after the NPN storage time phase AN3400 46/78 Doc ID 018840 Rev 1 phase, the following system of two first order linear differential equations is valid on all the [t5,t6] time interval with C=Cn=Cp: System of equations 19 in which VBEn= −VCEBn<0 and VEBp= −VCBEp<0 is an opportunely modeled signal complying with the following function: Equation 24 in which ψ1 is a constant depending on the initial value of the VCEBn voltage at t=t5-. The length of this dead time interval fixed for the simulation, in which the VCn and VCp voltage functions are determined through the ODE45 simulator, is imposed to be given by the following formula in which T npnsto=t5−t4, Tnpncon=t4−t2 and Tnpnric=t2−t0: Equation 25 This last working operation phase described completes the resonant driving network modeling with reference to the variation over a one-half period of the voltage signal V(s) across the filter capacitor and in particular concerning the time intervals, in sequence, shortly before (re-circulating phase), during (conduction phase) and afterwards (dead time) the NPN bipolar device functional stage. In the second one-half period the voltage signal V(s) has an opposite polarity compared to the first one and an analytical procedure similar to the NPN device modeling technique is applied for the PNP bipolar device interested in being simulated during its sequential working condition phases, as subsequently shown. ()() S CEBn S S CBCpnpndeadCp b npndeadCn bS npndeadCn RC V RC VICVRCVRRCtVdt d 11111 ()() S CEB n S S CCBnnpndeadCp b npndeadCn bS npndeadCp RC V RC VI C V RC V RRC tV dt d −⋅−⋅ −⋅⎟⎟ 11111 () () = 55 −−+− tVtV npnstoCnnpndeadCn () () = 55 −−+− tVtV npnstoCpnpndeadCp S CS CBnpn CCBn CEBn t C I C I=V ψ+⋅⎟⎟ npnricnpnconnpns to56npndead TTTf2 1tt=T −−−=−

11 Modeling of the re-circulating phase preliminary to

Figure 26. Driving network modeling for the si mulation of the first re-circulating phase

Figure 27. Driving network modeling for the simulation of the second re-circulating phase

AN3400 Modeling of the re-circulating phase preliminary to the PNP conduction time phase Doc ID 018840 Rev 1 49/78 where: System of equations 21 During the simulation phase, solutions for the VCn and VCp voltage functions have been calculated with the ODE45 simulator in a time interval as large as the length of the forcing signal Is opportunely modeled in order to take into consideration the effect of demagnetization current for the inductor L For the PNP bipolar base current IBpnp, the following formula reported is valid during the whole re-circulating phase preliminary to the PNP conduction time: Equation 26 in which VCn-pnpric(t) is a discharging voltage on the Cn capacitor (that is ). CBpCpCn2DLPRS1S IIIIIII =+=−== for t6<t<t7; =SI BpCpCn2ELPRS2S IIIIIII =+=+== for t7<t<t8; dCtVdt dCtItItI pnpricCppnpricCnpnpricCppnpricCnBpnp −−−− ⋅+⋅−=+= ()() 0tVdt d pnpricCn <−

12 PNP conduction phase modeling

Figure 28. Driving network modeling for the PNP bipolar conduction time phase simulation

AN3400 PNP conduction phase modeling Doc ID 018840 Rev 1 51/78 After that the two VCn and VCp functions have been obtained by resolving the previous system, the PNP bipolar base current IBpnp-on is directly given by the following formula: Equation 27 in which VCn-pnpcon(t) is a discharging voltage on the Cn capacitor (that is ). After having determined, through the ODE45 simulator, in a rather large time interval (one half of the total working period), the VCn and VCp voltage functions that resolve the System of equations 22, a research of the maximum value for the VCp function was imposed in order to determinate the final instant of the PNP conduction time t10. dCtVdt dCtItItI pnpconCppnpconCnpnpconCppnpconCnonBpnp −−−−− ⋅+⋅−=+= ()() 0tV dt d pnpconCn <−

13 PNP storage time phase modeling

Figure 29. Driving network modeling for the PNP bipolar storage time phase simulation

AN3400 PNP storage time phase modeling Doc ID 018840 Rev 1 53/78 in which VEBp is a constant voltage and RBase-pnp(t) is imposed to have the same increasing variability law as the RBase-npn(t) variable resistance: Equation 28 in which α2 and p (this last integer number) coefficients are determined so that RBase-pnp(t) has a fixed and constant mean value RBase-pnp-mean during the PNP storage time period of length equal to Δpnp seconds: Equation 29 Then, as already determined for the NPN storage time calculation, once the two parameters σpnp (or time constant directly connected to the lifetime of the minority carriers (holes) in the transistor base) and Ton-pnp (obtained from the simulation of the previous PNP bipolar conduction period) are fixed and well-known , a function of two independent variables is defined for the calculation of the PNP storage time as follows: Equation 30 in which εpnp parameter, depending on the recombination phenomenon of a share of the amount of charges in base, is given by: Equation 31 Therefore, varying the parameter εpnp from a minimum to a maximum value, imposed in base to the recombination characteristics of the minority carriers in base of the bipolar examined, the value Tstorage-pnp, that determines the storage time final instant t11, can be obtained finding the zeroes of the functions f(Tstorage-pnp, εpnp) for each fixed εpnp value and effectuating a mean operation among the Tstorage-pnp values so obtained. After having found, with the ODE45 simulator, in the calculated time interval Tstorage-pnp, the solutions of the System of equations 23 for the VCn and VCp voltage functions, then the NPN bipolar base current IBpnp-off is given by the following formula: Equation 32 with p 2pnpBase t)t(R ⋅α=− pnpt0 Δ≤≤ () = Δ +⋅Δ⋅ =α⇒⋅Δ= + −−Δ −−− ∫ 1p pnp pnpmeanpnpBase 20 pnpBase pnp meanpnpBase 1pR dt)t(R1R pnp 1011pnpStoragepnp ttT −==Δ −(by imposing ) p 1011 meanpnpBase tt 1pR +⋅= −− ε ⋅+⋅σ−=ε − pnp pnpstorage pnpon pnppnpstoragepnppnps torage T T 11lnT),T(f pnpon pnpstorage pnp A A dCtVdt dCtItItI pnpstoCnpnpstoCppnpstoCnpnpstoCpoffBpnp −−−−− ⋅+⋅−=−=

PNP storage time phase modeling AN3400 54/78 Doc ID 018840 Rev 1 in which both VCn-pnpsto(t) and VCp-pnpsto(t) are discharging voltages respectively on the Cn and Cp capacitors (that is and ). ()() 0tVdt d pnpstoCn <− ()() 0tVdt d pnpst oCp <−

14 Modeling of the dead time after the PNP storage time

according to working condition respectively of the PNP and NPN device, is considered. Figure 30. Driving network modeling for the simulation of the dead time after the PNP storage

on the discharge phase of the (variable) NPN base-collector junction capacitance CCBnpn;
on the charge phase of the (variable) PNP collector-base junction capacitance CBCpnp. AM09820v1 Cp Cn Cs Rs Rb VRs IRs VCn VCp ICn ICp IRb VRb ILP Lp Q2 VCs GND ICCBn VCCBn ICs VCBCp ICBCp VCEBn VDD VCBEp ICBEp IBpnp ICEBn IBnpn Vs Cp CnRs Rb VRs IRs VCn VCp ICn ICp IRb VRb ILP VCs GND ICCBnVCCBn ICs VCBCp ICBCp VCEBn VDD VCBEp ICBEp IBpnp ICEBnIBnpn Vs Cs ⇒≅ 0I,I CBEpCEBn CCBn Bnpn II ≅ , CBCpBpnp II ≅ and LPCS II ≅ ()() tV dt dCI CCBnCBnpnCCBn ⋅−= ()() tV dt dCI CB CpBC pnpCBCp ⋅=

Modeling of the dead time after the PNP storage time phase AN3400 56/78 Doc ID 018840 Rev 1 Then, after having imposed the previously listed assumptions, combining, with each other, the equations of the System of equations 10, describing the working conditions of the PNP bipolar during this phase, the following system of two first order linear differential equations has validity on all the [t 11,t12] time interval in which the signal has the polarity shown on the previous figure and imposed C=Cn=Cp: System of equations 24 in which VBEn= −VCEBn<0 and VEBp= −VCBEp<0 is an opportunely modeled signal complying with the following function: Equation 34 in which Ψ2 is a constant depending on the initial value of the VCBEp voltage at t=t11-. The length of this dead time interval fixed for the simulation, in which the VCn and VCp voltage functions are determined through the ODE45 simulator, is imposed to be given by the following formula in which T pnpsto=t11-t10, Tpnpcon=t10-t8 and Tpnpric=t8-t6: Equation 35 This last working operation phase described completes the resonant driving network modeling with reference to the variation over the whole period of the voltage signal V(s) across the filter capacitor and covering the time intervals, relating to the re-circulating, conduction and dead time phases for both NPN and PNP bipolar devices in their functional stages. The accuracy of the modeling technique proposed is verified by comparing the simulation results obtained using the Matlab tool with experimental results of the driving network circuital implementation response in steady-state working condition for the bipolar devices. V S t() As e n 2 πft π–()⋅–= ()() S CBEp S S CBCppnpdeadCp bS pnpdeadCn b pnpdeadCn RC V RC VICVRRCVRCtVdt d 11111 ()() S CB Ep S S CCBnpnpdeadCp bS pnpdeadCn b pnpde adCp RC V RC VICVRRCVRCtVdt d 11111 () () = 1111 −−+− tVtV pnpstoCnpnpdeadCn () () = 1111 −−+− tVtV pnpstoCppnpdeadCp S CS BC pnp CB Cp CBEp tC I C I=V ψ+⋅⎟⎟ npnricnpnconnpnstonpndeadpnpricpnpconpnpsto1112pnpdead TTTTTTTf

AN3400 Experimental results Doc ID 018840 Rev 1 57/78

15 Experimental results

Two commercially available power bipolar junction transistors, that find application in electronic lamp ballasts, were chosen for the experimental acquisition on the board tested. In particular, a complementary pair of ST power bipolar transistors, the NPN device STX83003 and PNP device STX93003 (in TO-92 package), respectively, were employed on the common emitter half bridge section to supply a 15 W CFL board in order to verify their compatibility on the resonant driving circuit solution. Values of the components used on the half bridge voltage fed topology optimized board setting and the main datasheet electrical specifications of the above mentioned devices are the following.

15.1 Applicative parameters

Setting of the driving network components (see Figure 1):
Power bipolar transistors specifications: –Q 1 → High voltage fast-switching NPN power bipolar transistor STX83003 in TO-92 package with Ic=1 A, BVceo=400 V and BVces=700 V; VCESAT=1 V@IC=350 mA, IB=50 mA and hFE = 25 (TYP) @ IC= 350 mA and VCE=5 V. –Q 2 → High voltage fast-switching PNP power bipolar transistor STX93003 in TO-92 package with IC=-1 A, BVceo=-400 V and BVces= -500 V; VCESAT=-500 mV @ IC= -350 mA, IB =-50 mA and hFE = 25 (TYP) @ IC= -350 mA and VCE=-5 V. An evaluation of switching performances of the devices during the normal working operation was made in “open board” (at 25 °C ambient temperature) conditions with 230 V input voltage values and 50 Hz frequency. In particular, the following images depict the functionality of the high side NPN bipolar transistor in steady-state operation. 4007N1D,D,D,D 4321 = ;1 5 9 BAD,D 65 = V400/F7.4C1 μ= ;V 100/nF47C2 = ;n F 100CC 43 == ;n F 2.1C5 = V630/nF7.4C6 = ;V 250/nF100CC 87 == Ω= 2.8Rfuse ; Ω= 2.8R2 ; Ω= k330R3 ; Ω= 330R4 ; Ω= k470R5 H100L1 μ= mH3.2A1T = ;3N B1T = turns.

Figure 31. STX83003 (NPN) bipolar transist or during steady-state operation with

230 V input voltage: base current (IB1), collector current (IC1),

Figure 32. STX83003 (NPN) bipolar transist or during steady-state operation with

230 V input voltage: base current (IB1), collector current (IC1), voltage on

Figure 33. STX83003 (NPN) bipolar transist or during steady-state operation with Figure 34. STX83003 (NPN) bipolar transist or during steady-state operation with bipolar case overheating phenomena.

Simulation results with the Matlab tool AN3400 62/78 Doc ID 018840 Rev 1

16 Simulation results with the Matlab tool

In order to evaluate the reliability of the modeling method described and relating to a complementary pair solution of bipolar transistors driven by a resonant network, results of the simulative analysis, implemented with the Matlab tool, have been compared with the applicative results obtained while testing the 15 W CFL optimized board. Therefore, the following listed conditions and assumptions have been imposed so as to perform the comparison.

16.1 Simulative parameters

Forcing signal generator: Re-circulating phase preliminary to the NPN bipolar conduction time phase (t0<t<t2) Signal IS modeled in the re-circulating interval t0<t<t2 with Trecn=t2−t0=2.35 µsec as: System of equations 25 () ( ) ft2senAtVS π⋅= with V65.7A = and kHz45ffreq == for f 1t0 << . nF100CCCCap pn ==== ;n F 2.1CS = ; Ω= 2.8RS ; Ω= 330Rb () V1=tV 00npnri cCn γ=− , () V9.3=tV 00npnricCp ϑ=− (initial values fixed) V5.02 VV onBEn BEn == − () 1 1 exp1 βα +⎟⎟ ⎛−−= ttI S for αttt ≤≤0 with 0, 11 >βα and ) %(55 02 ttt −=α ()tIS = () 2 2 exp1 βα +⎟⎟ ⎛−+−= ttI S for βα ttt ≤< with 0 , 22 >βα and ) %(60 02 ttt −=β () 313 βγ +⋅−= ttI S for 2ttt ≤<β with 0 , 31 >βγ

Figure 39. Current source signal Is modeling for the simulation on the re-circulating

Applicative analysis provides the following results: so σnpn is experimentally calculated by the Equation 13 as: Equation 36 AM09829v1 V1VBEn = V1VBEn = =⋅=⇒== −−−−− eappl icativperiodesteadystateapplicativstorageeapplicativperiodesteadystat T%11T45000 f s44.2s1044.2 45000 111.0 6 μ=⋅≈⋅= − A10150I 3 maxonBnpn −− ⋅= and A1055I 3 maxoffBnpn −− ⋅= sec108.1 1055 101501ln 1044.2 6 npn ⋅=σ n 1npnBase t)t(R ⋅α=− with () () n eapplicativstor age meannpnBase T 1nR −− +⋅ =α and Ω=−− 2R m eannpnBase , 3n = npn)i(ε for m1i ÷= with npnmaxnpnnpnmin )i( −− ε≤ε≤ε with: 100m = 15.0npnmin =ε − and 25.0npnmax =ε −

Simulation results with the Matlab tool AN3400 64/78 Doc ID 018840 Rev 1 Dead time after the NPN storage time phase (t5<t<t6)

Applicative analysis result provides ICnpn-max=330 mA –I CBCp=ICCBn=10 mA – Ψ1=0.5 Re-circulating phase preliminary to the PNP bipolar conduction time phase (t6<t<t8)
Signal IS modeled in the re-circulating interval t6<t<t8 as already done for the re-circulating interval t0<t<t2 with Trecp=t8−t6=2.35 µsec. PNP conduction time phase (t8<t<t10)
VEBp=0.8 V PNP storage time phase (t10<t<t11)
VEBp=0.8 V
σnpn=σpnp
RBase-npn(t)=RBase-pnp(t) – m=100 – εmin-pnp=0.15 and εmax-pnp=0.25 Dead time after the PNP storage time phase (t11<t<t12)
Applicative analysis result provides ICpnp-max=330 mA
with –I CBCp=ICCBn=10 mA – Ψ2=0.5 S CS CBnpn CCBn CEBn tC I C I=V ψ+⋅⎟⎟ − with: mA2648.0mA3308.0II maxCnpnCS =⋅=⋅= − pF45CCB npn = (meant as average capacity value) V4.0 VV onEBp EBp == − pnp)i(ε for m1i ÷= with pnpmaxpnppnpmin )i( −− ε≤ε≤ε with: S CS BCpnp CBCp CBEp tC I C I=V ψ+⋅⎟⎟ mA2648.0mA3308.0II maxCpnpCS =⋅=⋅= − pF45CBCpnp = (meant as average capacity value)

Figure 40. Re-circulating phase preliminary to the NPN conduction time phase

Figure 41. NPN conduction time phase

Figure 42. NPN storage time phase

Figure 43. Dead time phase after the NPN storage time phase

Figure 44. Re-circulating phase preliminary to the PNP conduction time phase

Figure 45. PNP conduction time phase

Figure 46. PNP storage time phase

in which Tpnpdead is the duration of the dead time phase after the PNP storage time phase. voltage value research in it. Figure 48. Driving network simulation results: filter capacitor voltage signal (V s),

17 Conclusions

A comprehensive description of a self-oscillating resonant driving system for compact fluorescent lamps (CFL), using a complementary pair of bipolar transistors on the half bridge converter section was made using a stage-wise circuit analysis in steady-state working condition for the devices. An analytical model has been developed to describe both of the resonant driving network functional characteristics and the physics of the bipolar devices during each working operation phase in steady-state condition. Then, a simulation procedure of the corresponding behavior model in Matlab environment has been carried out in order to verify the correctness of the modeling technique proposed. Finally, the accuracy of this approach/method is verified by comparing the simulation results with experimental ones obtained by the driving network circuital implementation response. Two commercially available complementary ST power bipolar junction transistors in TO-92 package (respectively NPN device STX83003 and PNP device STX93003), which find application in electronic lamp ballast applications, were chosen for the experimental analysis on a 15 W CFL board prototype. From the comparison of the simulation results with the signals acquired on the 15 W CFL board tested, the measured data are observed to agree closely with those provided by Matlab software tool, therefore validating the modeling method developed for the resonant driving network. In particular, results of simulation observed to be in good correspondence with measured experimental data are the values of the parameters , and for both devices. mA150IBon ≅ , mA60IBoff −≅ and sec 3.2TStorage μ≅

18 References

“Resonant Driving Circuit with a Complementary Pair Of Power Bipolar Transistor For CFLs”, STMicroelectronics Catania. 2. “Resonant Driving System for a Fluorescent Lamp”, Patent No.:US6, 628,090 B1, Date of Patent: Sep.30, 2003 3. “The Determination of the Bipolar Transistor Commutation Time Components by Using a Virtual Circuit” Hyperion University of Bucharest, Faculty of Mathematics-Informatics, ROMANIA

Table 1. Document revision history 28-Nov-2011 1 Initial release.

Summary

Analysis and simulation of a BJT complementary pair in a self-oscillating CFL solution 28-Nov-2011

Description