AN3392 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Application overview
- 2 Application information
- 3 SPV1020 description
- 4 Output voltage ripple
- 5 Application efficiency
- 6 SPV1020 functions
- 6.1 Operating modes
- 6.2 OFF-state
- 6.3 Burst mode
- 6.4 Normal/MPPT mode
- 7 Voltage regulation
- 7.1 Overvoltage protection
- 7.2 Overcurrent protection
- 7.3 Current balance
- 7.4 SPI serial peripheral interface
- 8 Pin description
- 8.1 Pin connection
- 9 Absolute maximum ratings
- 10 External component selection
- 10.1 Power and thermal considerations
- 10.2 Inductor selection
- 10.3 Bootstrap capacitors
- 10.4 Internal voltage rail capacitors
- 10.5 Input voltage capacitors
- 10.6 Input voltage partitioning
the MPPT is computed in the main centralized inverter. avoids the use of electrolytic capacitors, which can severely limit the system lifetime. cycle can range from 5% to 90% in steps of 0.2%. overvoltage or overtemperature. Figure 1. STEVAL-ISV009V1 demonstration board
1 Application overview
connected application and consists of a photovoltaic field and an electronic section. Figure 2. SPV1020 output series connection produced power to the characteristics of the public electrical grid. Other electronic components are the bypass diodes and the blocking diodes. protection and system functionality in case of damaged or shaded panels.
- Anti-Island control, a safety control forcing the system to disconnect from the grid when it is OFF for maintenance.
- Inverter control, for converting the DC power generated by the PV field to AC power compatible with the power on the public grid (voltage and current amplitude, frequency and phase).
- The MPPT (maximum power point tracking) control, allowing the extraction of the maximum amount of power possible from the PV field in order to maximize the power sourced to the grid. A limitation of the architecture in Figure 2 is that the MPPT control performs properly only when the PV field is uniformly irradiated. A first evolution of the above architecture is shown in Figure 3 (string-distributed), where the inverter includes more DC-DC converter sub-blocks, each implementing its own MPPT algorithm.
Figure 3. Photovoltaic system with multi-string inverter the problem of the partial shading on each panel.
require a DC-DC block and related controller. Figure 4. Photovoltaic panel for a distributed architecture
2 Application information
voltage higher than the input voltage. Figure 5. Step-up converter single-ended architecture generated by a PWM controller. decreases while the output voltage increases. Figure 6 shows the behavior of the current on the inductor. Figure 6. Step-up converter in continuous mode
- Continuous mode (CM);
- Discontinuous mode (DCM); depending on whether the current on the inductor becomes zero (DCM), or not (CM), within the switching period.
Figure 7. Step-up converter in discontinuous mode higher when it works in CM, if the switching frequency is constant. Worst case for L in the above formula is D = 50%.
3 SPV1020 description
when supplied by photovoltaic panels. Figure 8. Boost converter interleaved 4-phase architecture flow from the output to the input.
4 Output voltage ripple
smaller the current ripple (Ib-Ia). In IL-4 architecture, output current is the sum of the four currents flowing in each inductor. ripple. Figure 11 shows both the current in each branch and the final IOUT. Figure 11. Step-up current waveforms or interleaved 4-phase architecture
5 Application efficiency
In designing a boost application, a typical constraint is the maximum output current ripple. Once frequency, input, and output voltage are defined, this ripple is directly related to the inductance value in the application: Equation 3 The inductance value can be designed for a single-ended architecture and then divided by 4 in the case of IL-4 architecture. Each inductor, due to its internal resistance (RL), can affect system efficiency. For high current applications, an inductor with a compact geometry may compromise the efficiency requirements. Using the same ferromagnetic material, higher inductance can be achieved by increasing the inductor geometry, or by increasing the number of turns but using a thinner wire. In order to save space and cost, the latter solution is preferred but this increases the internal resistance and the saturation current of the inductor. Iripple ILmax ILmin Vin Fsw
6 SPV1020 functions
- OFF-state
- Burst mode
- Normal (or MPPT) mode.
Figure 12. SPV1020 general FSM (finite state machine)
6.2 OFF-state
thresholds are 6.5 V (UVLO_H) for turn-on and 6.0 V for turn-off (UVLO_L). node through the intrinsic diode of the synchronous rectifiers. returns to its default value.
6.3 Burst mode
decreased down to 0 (the phase is always OFF). checks if the input voltage is greater than the minimum threshold or not. Figure 13. Burst mode FSM When all four phases are active, the system enters normal (or MPPT) mode.
6.4 Normal/MPPT mode
executing an MPPT algorithm.
Figure 19. Normal/MPPT mode, DCM vs. CM FSM
Figure 20. Input voltage partitioning, sample circuit
7 Voltage regulation
In order to protect both the device itself and the load, the SPV1020 implements a dual control of the output voltage (VOUT). Control of VOUT is done through the VOUT_SNS pin, connected to VOUT by a resistive divider (see Section 10 for resistance values). The control consists of comparing VOUT_SNS with two internal thresholds: 1. 1.00 V, for voltage regulation 2. 1.04 V, for overvoltage protection. When V OUT_SNS increases up to 1 V, the output feedback loop enters regulation, limiting the output voltage. Regulation is achieved by creating an upper limit for the DC generated by the MPPT algorithm. The stability of the loop must be externally compensated by connecting a resistor and a capacitor (pole-zero combination) between the PZ_OUT pin and SGND pin (see Section 10 for values).
7.1 Overvoltage protection
If the VOUT_SNS exceeds 1.04 V, a fault signal is generated and transmitted to the fault controller which stops the drivers and produces a fault, setting the bit OVV in the status register. This information is accessible through the SPI interface by the Read Status command (op code 0x07). When V OUT_SNS drops back down to 1.04 V the DC-DC converter is switched ON again and the converter restarts the MPP search from the minimum duty cycle (5 %).
7.2 Overcurrent protection
To guarantee the safety of the entire application, the SPV1020 implements an overcurrent protection on the low-side power switches. In fact, when Lx is accidentally shorted to V in or VOUT, or when the current flowing through the inductor exceeds the peak current limit (4.5 A), the related low-side power switch is immediately turned OFF and the linked synchronous rectifier is enabled to turn on. The low-side power switch is turned on again at the next PWM cycle. In the case of overcurrent on branch x [x = 1..4], the related OVC bit of the status register is set. This information is accessible through the SPI interface by the Read Status command (op code 0x07).
7.3 Current balance
Different parasitic resistances between the four branches of the IL-4 architecture can be the root cause of unbalanced current flow between the four branches. This should be avoided as it may result in lower efficiency or damage to external components (inductors) and/or the SPV1020. It is recommended that the four branches in the PCB layout have symmetrical paths and the inductors be matching or from the same production lot.
7.4 SPI serial peripheral interface
- XCS (or SS)
- SPI_CLOCK (or SCLK)
- SPI_DA TA_IN (or MOSI)
- SPI_DATA_OUT (or MISO).
Figure 21. SPI interface: master/slaves connection example control bits CPOL = 1, and CPHA = 1). The bit order of each byte is MSB first. by the master during each transmission.
Figure 22. Frame structure: register read operation transmitted, see Figure 22. In other words, the master must transmit a byte to receive a byte. as a new one, starting with a command byte. Table 1. Data format for words longer than 8 bits
certain width and sets the direction of the related data. Table 2. Commands list
00 Reserved Reserved
01 NOP No operation
02 SHUT Shuts down SPV1020
03 Turn-on Required only after SHUT command
04 Read current Read Read 10 bits in 2 bytes (MSB is first received bit)
05 Read vin Read Read 10 bits in 2 bytes (MSB is first received bit)
06 Read pwm Read Read 9 bits in 2 bytes (MSB is first received bit)
07 Read status Read Read 7 bits:
8 Pin description
Table 3. Pin description
34 V in Supply DC input power
Pins 17 and 18 are internally shorted and connected to pins 19 and 20. All of the VOUT pins must be connected to the VOUT rail of the PCB. 12,13,24,25 PGND Ground Power ground to be connected to the ground plane of the PCB. 1 SGND Ground Signal ground to be connected to the ground plane of the PCB. 22,23,26,27 LX1…4 I Boost inductor connection.
31 XCS I
36 VIN_SNS_M I Dedicated reference pin for voltage sensing. 2P Z _ O U T I / O This pin is used to compensate the feedback loop of the output voltage. A series of resistors and capacitors must be connected to SGND. biased through a resistor to SGND. must be connected from this pin to the ground plane of the PCB. 6 SPI_DAT A_OUT O Output pin for SPI data flow. If not used, this pin should be left floating.
8.1 Pin connection
Figure 23. Pin connection top view PowerSSO-36
9 Absolute maximum ratings
Table 4. Maximum ratings
10 External component selection
both the best chip functionality and system efficiency. Figure 24. STEVAL-ISV009V1 schematic (PowerSSO-36 package) kHz, connect a resistor between OSC_IN and SGND (see Section 10.11).
4 HEADER
External component selection AN3392 30/57 Doc ID 018749 Rev 1
10.1 Power and thermal considerations
The SPV1020 performance is strongly impacted by the power capability of the PowerSSO- 36 package, as well as the application board. According to the technical note TN0054, R TH(j-a) of the PowerSSO-36 can be decreased to 10 °C/W if the package is soldered onto a “2s2p” multi-layer board with thermal vias and a metal plate for an external heatsink. Starting from this value, it is possible to calculate the PMAX. Equation 6 Equation 7 The SPV1020 efficiency (η ) is ≥ 98%; the thermal shutdown threshold is 140 °C; typical ambient temperature (TAMB) for a photovoltaic application is 85 °C. Calculating maximum power dissipation Pd: Equation 8 Equation 9 If the package is soldered onto a “2s2p” multi-layer board with thermal vias, the RTH(j-a) is 20 °C/W and then PMAX is 138 W. (PCB with 4 layers: 2 soldered layers, top and bottom, and 2 power layers (inner layers for power dissipation).
10.2 Inductor selection
Inductor selection is a critical element for this application. Inductor selection must take into account the following application conditions:
- Maximum input current (i.e. Imp and Isc of the PV panel)
- Maximum input voltage (i.e. Vmp and Voc of the panel)
- Overcurrent threshold of the SPV1020
- Maximum duty cycle, according to maximum output voltage Input current from the PV panel is split between the 4 inductors of each branch, so: Equation 10 TJ TAMB RTH j a–() PD⋅+= PD 1 η–() PMAX⋅= PD TJ TAMB– RTH j a–() PMAX PD ILx rms() Imp
AN3392 External component selection Doc ID 018749 Rev 1 31/57 According to Figure 6, during the charge phase (switch ON), peak current on each inductor depends on the applied voltage (Vin), on the inductance (Lx) and on the time (TON). Equation 11 Taking into account the overcurrent threshold (4.5 A): Equation 12 Finally, inductance should be chosen according to the following formula: Equation 13 Considering the possible unbalance of the currents and the inductance drop due to self heating effect, a more conservative choice would be to replace 4.5 A with 3.15 A (70%). Triggering the overcurrent threshold will cause limitation of the duty cycle and consequently limitation of the input and output powers. Usually, inductances ranging between 22 µH to 100 µH satisfy most application requirements. Critical parameters for the inductor choice are inductance (analyzed above), Irms current, saturation current, and size. The current flowing through an inductor causes its internal temperature increase (self- heating effect). Irms typically indicates the current value causing a temeprature increase of 20, 30, or 40 °C. The higher the temeprature, the higher the inductance drop with respect to its nominal value. For the same physical size, smaller inductance values provide for faster response to load transients and higher efficiency. Inductor size also affects the maximum current deliverable to the load. The saturation current of the inductor should be higher than the peak current limit of the input source. The suggested saturation current should be > 4.5 A. Inductors with low series resistance are suggested to guarantee high efficiency.
10.3 Bootstrap capacitors
C1, C2, C3, and C4 are four capacitors used to guarantee internal functionality of the SPV1020. Their role is to maintain the required voltage level on pins CB1, CB2, CB3, and CB4 even during the charging phase of the inductors. Capacitance value is the same for all four capacitors and is not application dependant. The suggested value is in the range of 22 nF to 100 nF . Each capacitor switches synchronously with the related inductor (at 100 kHz). The maximum voltage is fixed by the internal voltage regulator (~5 V). ILx pk() ILx rms() 1 2--- Vmp Lx A5.4)pk(ILx < Lx 2--- Vmp TON× 2--- Vmp TON⋅
4.5 Imp
External component selection AN3392 32/57 Doc ID 018749 Rev 1 Low ESR capacitors are a good choice to increase the entire system efficiency.
10.4 Internal voltage rail capacitors
C7 is a tank capacitor used to guarantee the voltage level (5 V) of the internal SPV1020 voltage regulator. The suggested value is 470 nF and is not application dependent. The voltage range is the same as for the boost capacitors. Maximum voltage must be higher than 5 V. Low ESR capacitors are recommended in order to increase the entire system efficiency.
10.5 Input voltage capacitors
C5 is the input capacitance added at the input to reduce the voltage ripple. The maximum voltage of this capacitor is dependent upon the input source (typically between 25 V and 50 V). Low-ESR capacitors are recommended in order to increase the whole system efficiency. Suggested minimum input capacitance is 2 µF . In order to reduce the ESR effect, it is suggested to split the input capacitance into 2 capacitors connected in parallel. Another capacitor (C11) is connected to the supply input pin of the SPV1020 (V in). Its role is to stabilize the voltage as much as possible on this pin which may be affected by the ripple of the PV panel voltage. Considering the maximum current (Isc) provided by the PV panel connected at the input, the following formula can be used to select the proper capacitance value (Cin) for a specified maximum input voltage ripple (V in_rp_max): Equation 14
10.6 Input voltage partitioning
The input voltage must be scaled to the reference voltage (1.25 V) of the ADC integrated in the SPV1020. R1 and R2 are the 2 resistors used for partitioning the input voltage. When the the open circuit voltage (Voc) of the PV panel is known, the said R1 and R2 must be selected according to the following rule: Equation 15 Cin Isc
AN3392 External component selection Doc ID 018749 Rev 1 33/57 In order to optimize the efficiency of the entire system, the selection of R1 and R2, should take their power dissipation into account. Assuming negligible the current flowing through pin VIN_SNS, maximum power dissipation of the series R1+R2 is: Equation 16 Empirically, R1 and R2 should be selected according to: Equation 17 Note: In order to guarantee the proper functionality of pin VIN_SNS, current flowing in the series R1+R2 should be in the range between 20 µA and 200 µA.
10.7 Input voltage sensing capacitor
C9 is placed in parallel with R2 and as close as possible to pin VIN_SNS. Its role is to stabilize as much as possible the voltage sensed by pin VIN_SNS. Critical parameters for the capacitor are: capacitance, maximum voltage, and ESR. Maximum voltage: if R1 and R2 have been properly chosen, to partition V in to 1.25 V, then the maximum voltage of this capacitor can be in the range from 3.3 V or higher. The capacitance value depends on the time constant (τin) composed with R1+R2 (τin= C6*R1//R2) and by the system switching frequency (FSSW = 4*FSW). Assuming R1 >> R2 (so, R1//R2 ~= R2): Equation 18 so, Equation 19 Note: Even if the SPV1020 controls each phase at F SW (by default 100 kHz), the system switching frequency (FSSW) is four times the single-phase switching frequency (by default 400 kHz).
10.8 Output voltage capacitors
A minimum output capacitance must be added at the output, in order to reduce the voltage ripple. Pvin_sns Voc() Pvin_sns 1% V in_max Iin_max⋅()« τ in 10 1 Fssw C9 10 1 Fssw
External component selection AN3392 34/57 Doc ID 018749 Rev 1 Critical parameters for capacitors are: capacitance, maximum voltage and ESR. Maximum voltage of this capacitor is strictly dependent upon the output voltage range. The SPV1020 can support up to 40 V. The minimum suggested voltage for these capacitors is 50 V . Low ESR capacitors are a good choice in order to increase the entire system efficiency. The suggested minimum output capacitance is 28 µF . In the case of series connection (see Appendix B: SPV1020 parallel and series connection), it is suggested to increase the output capacitance up to 100 µF . In order to reduce the ESR effect it is suggested to split the output capacitance into three capacitors connected in parallel. In accordance with the maximum current (Isc) provided by the PV panel connected at the input, the following formula can be used in order to select the proper capacitance value (Cout) for a specified maximum output voltage ripple (V out_rp_max): Equation 20 It is suggested to split the capacitance into four capacitors, each to be connected to each of the four VOUT pins of the SPV1020. This helps to balance the impedance of the four tracks.
10.9 Output voltage partitioning
R3 and R4 are the two resistors used for partitioning the output voltage. If VOUT_MAX is the maximum output voltage at the load, then R3 and R4 must be selected according to the following rule: Equation 21 Also, in order to optimize the efficiency of the entire system, when selecting R3 and R4, their power dissipation must be taken into account. Assuming negligible current flowing through pin VOUT_SNS, maximum power dissipation in the series connection of R3 and R4 is: Equation 22 Empirically, R3 and R4 should be selected according to: Equation 23 Cout Isc Pvout_sns Vout_max() Pvout_sns 1% V out_max Iout_max⋅()«
AN3392 External component selection Doc ID 018749 Rev 1 35/57 Note: In order to guarantee the proper functionality of V OUT_SNS current flowing in the series, connection of R3 and R4 should be between 20 µA and 200 µA.
10.10 Output voltage sensing capacitor
C10 is placed in parallel with R4 and is as close as possible to VOUT_SNS. Its role is to maximize the stability of the voltage sensed by the VOUT_SNS pin. If R3 and R4 are chosen properly and partition VOUT to 1.25 V, the voltage rating of this capacitor can be 3.3 V or higher. The capacitance value depends on the time constant (τout) composed with R4 (τout= C8*R3//R4) and by the system switching frequency (FSSW = 4*FSW). Assuming R4<<R3 (so, R3//R4 ≅ R4): Equation 24 so, Equation 25 Note: Even if the SPV1020 controls each phase at F SW (by default 100 kHz), the entire system switching frequency (System-Fswitch) is four times the single-phase switching frequency (by default 400 kHz).
10.11 Internal oscillator frequency
The SPV1020 controls the boost application by a PWM signal operating at the default switching frequency of 100 kHz. Default switching frequency is guaranteed by connecting the OSC_IN pin to 5 V (VREG). The user can change the default value by placing a proper resistor (R6), as shown in Figure 24, to ground. The internal oscillator works with an integrated resistor of 120 kΩ. Frequency is proportional to the current provided to the oscillator block. To change F switch to the desired switching frequency, R7 must be selected according to the following formula: Equation 26 TOUT 10 1 Fssw C10 10 1 FSSW
External component selection AN3392 36/57 Doc ID 018749 Rev 1
10.12 Diode selection
The SPV1020 requires 3 Schottky diodes: D1, D2 and D3, as shown in Figure 24. D3 (with C11) protects the SPV1020 supply by filtering system switching noise. D3 should be chosen for low forward drop so that it doesn’t impact system efficiency. Maximum forward current is according to the maximum current required by the SPV1020. A safe choice is around 20 mA. Maximum voltage applied to D3 depends on the PV panel, and does not exceed 45 V due to the maximum allowable SPV1020 input voltage. D1 is the alternative path for current flow when the SPV1020 is down and V in is higher than VOUT. D2 is a bypass diode. It turns on in the case of shaded cells and provides an alternative path for the current flowing from other panels. D1 and D2 are power Schottky diodes that must support both:
- Forward current comparable with the maximum current provided by the PV cells. Assuming a PV panel with 6” poly crystalline silicon solar cells, then the maximum current is 9 A.
- Maximum reverse voltage according to the output voltage partitioning. This should be at least 45 V due to the voltage rating of the SPV1020. Furthermore, the forward voltage and reverse current of D1 and D2 should be as low as possible in order to minimize the impact on system efficiency.
10.13 Protection devices
The SPV1020 demo board uses a protection Transil™ D4 to trigger voltage spikes higher than 45 V (AMR of the SPV102) on the V OUT pins. This component must be chosen according to the following rules: VBR > V OUT_max; and VCL ≤ 45 V. The STEVAL-ISV009V1 uses D4 which has VBR = 37 V and VCL = 40 V.
10.14 Pole-zero compensation
The SPV1020 controls the whole system stability by an internal loop on VOUT_SNS. The transfer function of the loop depends on both the output capacitor and load. Even though the stability can be fine tuned by trimming R5 and C8 on pin PZ_OUT, as shown in Figure 24, their suggested values (R5 = 1 kΩ and C8 = 22 nF) guarantee stability in most applications. In order to increase system response to output voltage changes without causing overvoltage threshold triggering, C8 can be decreased down to 2.2 nF .
11 Layout guidelines
problems and electromagnetic interference. and a poor tracking of the MPPT. possible. This reduces radiation and electromagnetic resonance problems. thermal vias as well), and also increase efficiency. Boost capacitors must be connected as close as possible to the Lx and CBx pins. The output and input capacitors should be very close to the device. Figure 25. PCB layout example (top view)
Figure 26. PCB layout example (bottom view)
12 Bill of material
application with VOC = 30 V, Imp = 9 A, Vout_max = 36 V and FSW = 100 kHz. Table 5. Bill of material
Table 5. Bill of material (continued)
The following figure shows how to connect the STEVAL-ISV009V1 to a photovoltaic panel. Figure 27. STEVAL-ISV009V1 application schematic to guarantee the voltage level required by the specific application. Maximum voltage for the STEVAL-ISV009v1 is 36 V, according to R3/R4 partitioning. panels), a minimum redundancy (10%) on Ns_min is suggested.
SPV1020 parallel and series connection AN3392 42/57 Doc ID 018749 Rev 1 Appendix B SPV1020 parallel and series connection The output pins of the SPV1020s can be connected both in parallel and in series. In both cases the output power (Pout) depends on light irradiation of each panel (Pin), application efficiency, and on the specific constraint of the selected topology. The objective of this section is to explain how output power is impacted by the selected topology. Examples with three PV panels are presented, but the result can be extended to a larger number of PV panels. In the case of the SPV1020 being ON (I.e. there is enough light irradiation so that Vin =
6.5 V):
In the case of the SPV1020 being OFF , the system efficiency depends on the drop of the bypass diode D1 (according to the schematic in Figure 24): Equation 30 Finally, in the case of the panel being completely shaded: Equation 31 Poutx η= Pinx x 1..3=[] Poutx η bp P= inx x 1..3=[] Poutx 0=
Figure 28. SPV1020, output parallel connection
AN3392 SPV1020 parallel and series connection Doc ID 018749 Rev 1 45/57 In the case where the irradiation is the same for each panel: Equation 40 Equation 41 Equation 42 Equation 43 so, Equation 44 For example, assuming Pout = 90 W and, if desired VOUT = 90 V, then Voutx = 30 V. Lower irradiation for one panel, for example on panel 2, causes lower output power, so lower Vout2 due to the Iout constraint: Equation 45 The output voltage (VOUT) required by the load can be supplied by the 1st and 3rd SPV1020 but only up to the limit imposed by their R3/R4 partitioning. Some examples can help to understand the various scenarios assuming the following conditions: R3/R4 limiting Voutx = 40 V and desired VOUT = 90 V. Example 1: Panel 2 has 75% of the irradiation that panels 1 and 3 have: Pin1 Pin2 Pin3== Pout 3 Poutx x 1..3 =[]⋅= Poutx 1 3---Pout= Poutx Voutx Ioutx Voutx Iout ⋅=⋅= Voutx 1 3---Vout= Voutx Poutx Vout2 3 4--- Vout1 3 4--- Vout3⋅=⋅= Pout1 Pout2 Pout3== Pout2 3 4---Pin1 22.5W== Pout Pout1 Pout2 Pout3 82.5W =++=
SPV1020 parallel and series connection AN3392 46/57 Doc ID 018749 Rev 1 Two of the SPV1020s (1st and 3rd) supply most of the voltage drop due to the lower irradiation on panel 2. Note: The SPV1020 is a boost controller, so Voutx must be higher than Vinx, otherwise the SPV1020 turns off and the input power is transferred to the output stage through the bypass diode D1 (refer to the schematic in Figure 24). Example 2: Panel 2 has 25% more irradiation than panels 1 and 3: In this case the system is at its limit. A lower irradiation on panel 2 impacts Vout1 and/or Vout3 which are already delivering as much voltage as possible (40 V), imposed by R3/R4 partitioning. Example 3: Panel 2 completely shaded. In this case the maximum V OUT can be 80 V (Vout1+Vout3). Diode D2 (refer to schematic in Figure 24) across the 2nd SPV1020 allows Iout to flow. Iout Pout Vout1 Vout3 30 Vout2 22.5 Vout2 1 4--- Vout1 1 4--- Vout3⋅=⋅= Pout1 Pout2 30== Pout2 1 4---Pin1 7.5W== Pout Pout1 Pout2 Pout3 67.5W =++= Iout Pout Vout1 Vout3 30 Vout2 7.5
- Agilent Technologies E4360A Modular SAS Mainframe with module E4361A
- Chroma 6314A DC ELECTRONIC LOAD Mainframe
- LeCroy WaveRunner 6100 A.
- Agilent 34401A digit Multimeter (as voltmeter)
- Agilent U1242 digital Multimeter (as ammeter)
- STEVAL-ISV009V1 (SPV1020 application board)
The following image shows the setup of the above environment. Figure 30. Measurement environment efficiency at P=96 W is 97 %.
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 6. PowerSSO-36 mechanical data
Figure 43. PowerSSO-36 package dimensions
Table 7. Document revision history 09-May-2012 1 Initial release.