AN3383 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 29
Technical content
Datasheet sections
- 1 Functional description of the demonstration board
- 1.1 Connections
- 1.2 Output configuration
- 1.3 Schematic and block diagrams, PCB layout, bill of material
- 2 Test results
- 3 Thermal test results
- 4 Design guidelines for schematic and PCB layout
- 4.1 Schematic
- 4.1.1 Main driver for selection of components
- 4.1.2 Decoupling capacitors
- 4.1.3 Output filter
- 4.2 PCB layout
- 5 Revision history
components. It is a complete solution for the digital audio power amplifier. Figure 1. STA350BW 2.0-channel demonstration board
Functional description of the demonstration board AN3383 4/29 Doc ID 018691 Rev 1
1 Functional description of the demonstration board
The following terms used in this application note are defined as follows:
- THD+N vs. Freq: Total harmonic distortion plus noise versus frequency curve
- THD+N vs. Pout: Total Harmonic Distortion (THD) plus noise versus output power
- S/N ratio: Signal-to-noise ratio
- FFT: Fast Fourier Transform Algorithm (method)
- CT: Channel separation L to R, or R to L channel crosstalk The equipment used includes the following:
- Audio Precision (System 2700) by AP Co., USA)
- DC power supply (4.5 V to 26 V)
- Digital oscilloscope (TDS3034B by Tektronix)
- PC (with APWorkbench GUI control software installed)
1.1 Connections
Power supply signal and interface connection 1. Connect the positive voltage of 24V DC power supply to the +Vcc pin and negative to GND. 2. Connect the APWorkbench board to the J1 connector of the STA350BW demonstration board. 3. Connect the S/PDIF signal cable to the RC A jack on the APWLink board, connecting to the signal source such as Audio precision or DVD player. Note: The voltage range of the DC power supply for V CC is 4.5 V to 26 V.
1.2 Output configuration
The STA350BW demo board is specifically configured in 2 BTL channels. For the software setup, please refer to the APWUserManualR1.0.pdf.
1.3 Schematic and block diagrams , PCB layout, bill of material
Figure 2. Schematic diagram
Figure 3. Block diagram of test connections with equipment
Table 1. Bill of material
1 Jack Through-hole 4P Speaker Jack 1 J7 Any source
2 MCAP Through-hole 680NF-M(63V) Capacitor 2 C415SL, C416S Any source
3 Terminal Through-hole 2P Pitch: 5 mm Connector Terminal 1 CN2 Phoenix
5 CCAP CAP0603 50 volt NPO 330 pF +/- 10% 2 C418A, C425 Murata
6 CCAP CAP0603 50 volt NPO 680 pF +/- 10% 1 C9 Murata
7 CCAP CAP0603 50 volt 1 nF +/- 10% 1 C3 Murata
9 CCAP CAP0603 50 volt 100 nF +/- 10% 15
10 CCAP CAP1206 50 volt 1 µF +/-10% 2 C426A, C426B Murata
11 RES R1206 4R7, +/-5% 1/4W 4 R424A, R424B,
12 RES R1206 20 +/-5% 1/4W 2 R422A, R423 Murata
13 RES R0603 0 ohm 1/16W 1 R31 Murata
14 RES R0603 2R2 +/-5% 1/16W 1 R32 Murata
15 RES R0603 10K +/-5% 1/16W 1 R1 Murata
17 RES R0603 NS 2 R4, R5
18 ECAP Through-hole 22 µF/ 16 V 1 C12 Rubycon/
19 ECAP Through-hole 1000 µF / 35 V 105 Centigrade 1 C428 Rubycon/
20 Plastic rod Hexagonal rod 15 mm length,
21 Plastic rod Hexagonal rod 8 mm length,
22 IC PSSO36 STA350BW 1 IC1 ST
23 Coil Through-hole 15 µH Choke Coil (1014P-01-150L) 4 L421A, L421B,
2 Test results
All the results and graphs are from measures using equipment from Audio Precision. Figure 6. Efficiency (2 channels, BTL configuration), V CC = 26 V, RL = 6 ohm
3 Thermal test results
Figure 17. Output power = 2 x 5 W, V CC = 26 V, load = 6 ohm, frequency = 1 kHz Figure 18. Output power = 2 x 10 W, V CC = 26 V, load = 6 ohm, frequency = 1 kHz
4 Design guidelines for schematic and PCB layout
4.1 Schematic
4.1.1 Main driver for selection of components
- Absolute maximum rating: STA350BW VCC = 30 V
- Bypass capacitor 100 nF in parallel to 1 µF for each power VCC branch. Preferable dielectric is X7R
- Vdd and Ground for PLL filter separated from the other power supply
- Coil saturation current compatible with the peak current of application
4.1.2 Decoupling capacitors
inductance with the copper wire on the PC board.
4.1.3 Output filter
Figure 21. Output filter
- The key function of a snubber network is to absorb energy from the reactance in the
pulse energy such as a spike in the power circuit which is dangerous to the system.
Figure 26. Recommended power-up and power-down sequence
4.2 PCB layout
The following figures illustrate layout recommendations. Figure 27. Snubber network soldered as close as possible to the related IC pin
For better thermal dissipation, it is recommended that 2-ounce copper be used in the PCB. Figure 30. Large ground planes on the top and bottom sides of the PCB
5 Revision history
Table 3. Document revision history 08-Apr-2011 1 Initial release.